sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity
gem5/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt

865 lines
98 KiB
Plaintext
Raw Normal View History

ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
---------- Begin Simulation Statistics ----------
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
sim_seconds 0.473434 # Number of seconds simulated
sim_ticks 473433799500 # Number of ticks simulated
final_tick 473433799500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
host_inst_rate 169995 # Simulator instruction rate (inst/s)
host_op_rate 189642 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 52106394 # Simulator tick rate (ticks/s)
host_mem_usage 499160 # Number of bytes of host memory used
host_seconds 9085.91 # Real time elapsed on the host
sim_insts 1544563083 # Number of instructions simulated
sim_ops 1723073895 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 48384 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 156296704 # Number of bytes read from this memory
system.physmem.bytes_read::total 156345088 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 48384 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 48384 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 71931712 # Number of bytes written to this memory
system.physmem.bytes_written::total 71931712 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 756 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2442136 # Number of read requests responded to by this memory
system.physmem.num_reads::total 2442892 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1123933 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1123933 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 102198 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 330134232 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 330236430 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 102198 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 102198 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 151936157 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 151936157 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 151936157 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 102198 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 330134232 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 482172587 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 2442892 # Total number of read requests seen
system.physmem.writeReqs 1123933 # Total number of write requests seen
system.physmem.cpureqs 3566825 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 156345088 # Total number of bytes read from memory
system.physmem.bytesWritten 71931712 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 156345088 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 71931712 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 1286 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 151934 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 156031 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 154856 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 153024 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 150249 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 152372 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 153472 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 154746 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 153379 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 151879 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 152199 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 152305 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 150118 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 153271 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 150713 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 151058 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 70393 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 72288 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 71658 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 69978 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 69490 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 69799 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 70024 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 70449 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 69754 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 69615 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 69971 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 69698 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 68976 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 71736 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 70217 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 69887 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 473433771000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 2442892 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
system.physmem.writePktSize::2 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
system.physmem.writePktSize::6 1123933 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
system.physmem.rdQLenPdf::0 1613567 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 411043 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 122672 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 76227 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 63723 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 50754 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 36534 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 28949 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 23035 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 15102 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 43358 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 46512 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 47775 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 48422 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 48759 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 48833 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 48858 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 48865 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 48866 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 48867 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 48867 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 48867 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 48867 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 48867 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 48867 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 48866 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 48866 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 48866 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 48866 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 48866 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 48866 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 48866 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 48866 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 5509 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 2355 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 1092 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 445 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 108 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 34 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 39045821973 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 121584903973 # Sum of mem lat for all requests
system.physmem.totBusLat 9766424000 # Total cycles spent in databus access
system.physmem.totBankLat 72772658000 # Total cycles spent in bank access
system.physmem.avgQLat 15991.86 # Average queueing delay per request
system.physmem.avgBankLat 29805.24 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 49797.10 # Average memory access latency
system.physmem.avgRdBW 330.24 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 151.94 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 330.24 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 151.94 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 3.01 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.26 # Average read queue length over time
system.physmem.avgWrQLen 10.90 # Average write queue length over time
system.physmem.readRowHits 966664 # Number of row buffer hits during reads
system.physmem.writeRowHits 336338 # Number of row buffer hits during writes
system.physmem.readRowHitRate 39.59 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 29.93 # Row buffer hit rate for writes
system.physmem.avgGap 132732.55 # Average gap between requests
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.numCycles 946867600 # number of cpu cycles simulated
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.BPredUnit.lookups 299593765 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 245452602 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 16045022 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 170764551 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 155662191 # Number of BTB hits
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.BPredUnit.usedRAS 18346296 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 201 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 291830558 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 2150759454 # Number of instructions fetch has processed
system.cpu.fetch.Branches 299593765 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 174008487 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 427702866 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 82463506 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 122599229 # Number of cycles fetch has spent blocked
Stats: Update stats to reflect SimpleMemory bandwidth This patch simply bumps the stats to reflect the introduction of a bandwidth limit of 12.8GB/s for SimpleMemory.
2012-09-18 16:30:04 +02:00
system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.fetch.PendingTrapStallCycles 88 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 282801731 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 5377782 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 908156186 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.634401 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.243337 # Number of instructions fetched each cycle (Total)
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.fetch.rateDist::0 480453401 52.90% 52.90% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 22859151 2.52% 55.42% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 38736937 4.27% 59.69% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 47688218 5.25% 64.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 40498646 4.46% 69.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 46746329 5.15% 74.54% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 38999717 4.29% 78.84% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 18064778 1.99% 80.83% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 174109009 19.17% 100.00% # Number of instructions fetched each cycle (Total)
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.fetch.rateDist::total 908156186 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.316405 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.271447 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 320351849 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 103310609 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 403372314 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 15098642 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 66022772 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 46034722 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 704 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 2339352792 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 2529 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 66022772 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 341796573 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 48717971 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 14906 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 395855837 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 55748127 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 2282794185 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 39847 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 4611517 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 42695661 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 2257537981 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 10537280026 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 10537275559 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 4467 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1706320026 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 551217955 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 838 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 835 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 129599333 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 622569059 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 218142237 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 84983278 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 64739003 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 2182778805 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 865 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 2010794421 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 4810108 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 455220170 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 1060725588 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 683 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 908156186 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.214150 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.929063 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iq.issued_per_cycle::0 247277493 27.23% 27.23% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 133932127 14.75% 41.98% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 156228000 17.20% 59.18% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 116195915 12.79% 71.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 125706835 13.84% 85.82% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 75923793 8.36% 94.18% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 39533015 4.35% 98.53% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 10697910 1.18% 99.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 2661098 0.29% 100.00% # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iq.issued_per_cycle::total 908156186 # Number of insts issued each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iq.fu_full::IntAlu 703286 2.81% 2.81% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 4771 0.02% 2.83% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 2.83% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.83% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.83% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.83% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 2.83% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.83% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.83% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.83% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.83% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.83% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.83% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.83% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.83% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 2.83% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.83% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 2.83% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.83% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.83% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.83% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.83% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.83% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.83% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.83% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.83% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.83% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.83% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.83% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 19012865 76.06% 78.90% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 5274676 21.10% 100.00% # attempts to use FU when none available
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iq.FU_type_0::IntAlu 1230823853 61.21% 61.21% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 930532 0.05% 61.26% # Type of FU issued
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 72 0.00% 61.26% # Type of FU issued
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 30 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 15 0.00% 61.26% # Type of FU issued
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.26% # Type of FU issued
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iq.FU_type_0::MemRead 585374477 29.11% 90.37% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 193665439 9.63% 100.00% # Type of FU issued
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iq.FU_type_0::total 2010794421 # Type of FU issued
system.cpu.iq.rate 2.123628 # Inst issue rate
system.cpu.iq.fu_busy_cnt 24995598 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.012431 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 4959550302 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 2638184259 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1953078988 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 432 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 858 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 164 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 2035789802 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 217 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 63764603 # Number of loads that had data forwarded from stores
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 136642278 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 284566 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 187935 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 43295180 # Number of stores squashed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 386993 # Number of times an access to memory failed due to the cache being blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iew.iewSquashCycles 66022772 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 23145640 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 1044628 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 2182779773 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 5713944 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 622569059 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 218142237 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 798 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 173655 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 44651 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 187935 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 8601247 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 10177350 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 18778597 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1981378382 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 570935022 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 29416039 # Number of squashed instructions skipped in execute
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iew.exec_nop 103 # number of nop insts executed
system.cpu.iew.exec_refs 761630934 # number of memory reference insts executed
system.cpu.iew.exec_branches 237544754 # Number of branches executed
system.cpu.iew.exec_stores 190695912 # Number of stores executed
system.cpu.iew.exec_rate 2.092561 # Inst execution rate
system.cpu.iew.wb_sent 1962075581 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1953079152 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1293757962 # num instructions producing a value
system.cpu.iew.wb_consumers 2065123050 # num instructions consuming a value
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iew.wb_rate 2.062674 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.626480 # average fanout of values written-back
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.commit.commitSquashedInsts 459769347 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 182 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 16044351 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 842133415 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 2.046082 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.757625 # Number of insts commited each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.commit.committed_per_cycle::0 351966566 41.79% 41.79% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 194208080 23.06% 64.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 73932281 8.78% 73.64% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 35396184 4.20% 77.84% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 18675547 2.22% 80.06% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 31087553 3.69% 83.75% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 19760319 2.35% 86.09% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 10744228 1.28% 87.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 106362657 12.63% 100.00% # Number of insts commited each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.commit.committed_per_cycle::total 842133415 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1544563101 # Number of instructions committed
system.cpu.commit.committedOps 1723073913 # Number of ops (including micro ops) committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.commit.refs 660773838 # Number of memory references committed
system.cpu.commit.loads 485926781 # Number of loads committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.membars 62 # Number of memory barriers committed
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.commit.branches 213462438 # Number of branches committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.commit.int_insts 1536941889 # Number of committed integer instructions.
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.function_calls 13665177 # Number of function calls committed.
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.commit.bw_lim_events 106362657 # number cycles where commit BW limit reached
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.rob.rob_reads 2918613419 # The number of ROB reads
system.cpu.rob.rob_writes 4431868415 # The number of ROB writes
system.cpu.timesIdled 795856 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 38711414 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1544563083 # Number of Instructions Simulated
system.cpu.committedOps 1723073895 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1544563083 # Number of Instructions Simulated
system.cpu.cpi 0.613033 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.613033 # CPI: Total CPI of All Threads
system.cpu.ipc 1.631234 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.631234 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 9926647662 # number of integer regfile reads
system.cpu.int_regfile_writes 1933066427 # number of integer regfile writes
system.cpu.fp_regfile_reads 168 # number of floating regfile reads
system.cpu.fp_regfile_writes 190 # number of floating regfile writes
system.cpu.misc_regfile_reads 2888912367 # number of misc regfile reads
system.cpu.misc_regfile_writes 148 # number of misc regfile writes
system.cpu.icache.replacements 20 # number of replacements
system.cpu.icache.tagsinuse 632.636403 # Cycle average of tags in use
system.cpu.icache.total_refs 282800594 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 786 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 359797.193384 # Average number of references to valid blocks.
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.icache.occ_blocks::cpu.inst 632.636403 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.308904 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.308904 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 282800594 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 282800594 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 282800594 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 282800594 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 282800594 # number of overall hits
system.cpu.icache.overall_hits::total 282800594 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1137 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1137 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1137 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1137 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1137 # number of overall misses
system.cpu.icache.overall_misses::total 1137 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 39598000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 39598000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 39598000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 39598000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 39598000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 39598000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 282801731 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 282801731 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 282801731 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 282801731 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 282801731 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 282801731 # number of overall (read+write) accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34826.737027 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 34826.737027 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 34826.737027 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 34826.737027 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 34826.737027 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 34826.737027 # average overall miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 351 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 351 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 351 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 351 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 351 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 351 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 786 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 786 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 786 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 786 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 786 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 786 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28796000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 28796000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28796000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 28796000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28796000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 28796000 # number of overall MSHR miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36636.132316 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36636.132316 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36636.132316 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 36636.132316 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36636.132316 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 36636.132316 # average overall mshr miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dcache.replacements 9616903 # number of replacements
system.cpu.dcache.tagsinuse 4087.861296 # Cycle average of tags in use
system.cpu.dcache.total_refs 660505517 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 9620999 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 68.652488 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 3324501000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4087.861296 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.998013 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.998013 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 492433938 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 492433938 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 168071407 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 168071407 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 99 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 99 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 73 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 73 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 660505345 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 660505345 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 660505345 # number of overall hits
system.cpu.dcache.overall_hits::total 660505345 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 10054191 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 10054191 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 4514640 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 4514640 # number of WriteReq misses
ARM: Update stats for CBNZ fix.
2012-03-09 21:33:07 +01:00
system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dcache.demand_misses::cpu.data 14568831 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 14568831 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 14568831 # number of overall misses
system.cpu.dcache.overall_misses::total 14568831 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 192605585000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 192605585000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 133759941491 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 133759941491 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 146500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 146500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 326365526491 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 326365526491 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 326365526491 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 326365526491 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 502488129 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 502488129 # number of ReadReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 102 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 102 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 73 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 73 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 675074176 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 675074176 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 675074176 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 675074176 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020009 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.020009 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026159 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.026159 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.029412 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.029412 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.021581 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.021581 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.021581 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.021581 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19156.746177 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 19156.746177 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29628.041547 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 29628.041547 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 48833.333333 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 48833.333333 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22401.627591 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 22401.627591 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22401.627591 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 22401.627591 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 1880438 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 248831 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 88187 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1969 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.323302 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 126.374302 # average number of cycles each access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dcache.writebacks::writebacks 3473899 # number of writebacks
system.cpu.dcache.writebacks::total 3473899 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2327206 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 2327206 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2620625 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 2620625 # number of WriteReq MSHR hits
ARM: Update stats for CBNZ fix.
2012-03-09 21:33:07 +01:00
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dcache.demand_mshr_hits::cpu.data 4947831 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 4947831 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 4947831 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 4947831 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7726985 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 7726985 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1894015 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1894015 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 9621000 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 9621000 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 9621000 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 9621000 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 100672222000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 100672222000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 58875647012 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 58875647012 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 159547869012 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 159547869012 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 159547869012 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 159547869012 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015377 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015377 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010974 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010974 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014252 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.014252 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014252 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.014252 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13028.655032 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13028.655032 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31085.100705 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31085.100705 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16583.293734 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 16583.293734 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16583.293734 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 16583.293734 # average overall mshr miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.replacements 2427272 # number of replacements
system.cpu.l2cache.tagsinuse 31171.716737 # Cycle average of tags in use
system.cpu.l2cache.total_refs 8744168 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 2456984 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 3.558903 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 80002919000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 14002.042506 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 15.065518 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 17154.608713 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.427308 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.000460 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.523517 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.951285 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 29 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 6115863 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 6115892 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 3473899 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 3473899 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 1062992 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 1062992 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 29 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 7178855 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 7178884 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 29 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 7178855 # number of overall hits
system.cpu.l2cache.overall_hits::total 7178884 # number of overall hits
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu.l2cache.ReadReq_misses::cpu.inst 757 # number of ReadReq misses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.ReadReq_misses::cpu.data 1611122 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 1611879 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 831023 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 831023 # number of ReadExReq misses
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu.l2cache.demand_misses::cpu.inst 757 # number of demand (read+write) misses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.demand_misses::cpu.data 2442145 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 2442902 # number of demand (read+write) misses
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu.l2cache.overall_misses::cpu.inst 757 # number of overall misses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.overall_misses::cpu.data 2442145 # number of overall misses
system.cpu.l2cache.overall_misses::total 2442902 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 27934500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 84953945000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 84981879500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 55209394500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 55209394500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 27934500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 140163339500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 140191274000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 27934500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 140163339500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 140191274000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 786 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 7726985 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 7727771 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 3473899 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 3473899 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1894015 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1894015 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 786 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 9621000 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 9621786 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 786 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 9621000 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 9621786 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.963104 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.208506 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.208583 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.438763 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.438763 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963104 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.253835 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.253893 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963104 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.253835 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.253893 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36901.585205 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52729.678448 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52722.244970 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66435.459067 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66435.459067 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36901.585205 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 57393.537034 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 57387.187042 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36901.585205 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 57393.537034 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 57387.187042 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 1390172 # number of cycles access was blocked
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.blocked::no_mshrs 31316 # number of cycles access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 44.391749 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.writebacks::writebacks 1123933 # number of writebacks
system.cpu.l2cache.writebacks::total 1123933 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.overall_mshr_hits::total 10 # number of overall MSHR hits
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 756 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1611113 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 1611869 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 831023 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 831023 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 756 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 2442136 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 2442892 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 756 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2442136 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 2442892 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25190143 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 79130491462 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 79155681605 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 52276530586 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 52276530586 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25190143 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 131407022048 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 131432212191 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25190143 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 131407022048 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 131432212191 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.961832 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.208505 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.208581 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.438763 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.438763 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.961832 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.253834 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.253892 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.961832 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.253834 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.253892 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33320.294974 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 49115.419876 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 49108.011634 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62906.237957 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62906.237957 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33320.294974 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53808.232649 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53801.892262 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33320.294974 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53808.232649 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53801.892262 # average overall mshr miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink