2011-01-18 23:30:06 +01:00
---------- Begin Simulation Statistics ----------
2015-11-06 09:26:50 +01:00
sim_seconds 0.116576 # Number of seconds simulated
sim_ticks 116576497500 # Number of ticks simulated
final_tick 116576497500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2011-01-18 23:30:06 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
2016-03-17 18:25:11 +01:00
host_inst_rate 72932 # Simulator instruction rate (inst/s)
host_op_rate 87563 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 31139070 # Simulator tick rate (ticks/s)
host_mem_usage 321028 # Number of bytes of host memory used
host_seconds 3743.74 # Real time elapsed on the host
2015-04-30 21:17:43 +02:00
sim_insts 273037220 # Number of instructions simulated
sim_ops 327811602 # Number of ops (including micro ops) simulated
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2015-11-06 09:26:50 +01:00
system.physmem.bytes_read::cpu.inst 620608 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 4625216 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher 169088 # Number of bytes read from this memory
system.physmem.bytes_read::total 5414912 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 620608 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 620608 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 9697 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 72269 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher 2642 # Number of read requests responded to by this memory
system.physmem.num_reads::total 84608 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 5323612 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 39675373 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher 1450447 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 46449431 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 5323612 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 5323612 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 5323612 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 39675373 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher 1450447 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 46449431 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 84608 # Number of read requests accepted
2013-11-01 16:56:34 +01:00
system.physmem.writeReqs 0 # Number of write requests accepted
2015-11-06 09:26:50 +01:00
system.physmem.readBursts 84608 # Number of DRAM read bursts, including those serviced by the write queue
2013-11-01 16:56:34 +01:00
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
2015-11-06 09:26:50 +01:00
system.physmem.bytesReadDRAM 5414912 # Total number of bytes read from DRAM
2013-11-01 16:56:34 +01:00
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
2015-11-06 09:26:50 +01:00
system.physmem.bytesReadSys 5414912 # Total read bytes from the system interface side
2013-11-01 16:56:34 +01:00
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
2016-02-10 10:08:27 +01:00
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
2015-11-06 09:26:50 +01:00
system.physmem.perBankRdBursts::0 955 # Per bank write bursts
system.physmem.perBankRdBursts::1 811 # Per bank write bursts
system.physmem.perBankRdBursts::2 833 # Per bank write bursts
system.physmem.perBankRdBursts::3 2939 # Per bank write bursts
system.physmem.perBankRdBursts::4 10638 # Per bank write bursts
system.physmem.perBankRdBursts::5 59815 # Per bank write bursts
system.physmem.perBankRdBursts::6 159 # Per bank write bursts
system.physmem.perBankRdBursts::7 253 # Per bank write bursts
system.physmem.perBankRdBursts::8 227 # Per bank write bursts
system.physmem.perBankRdBursts::9 304 # Per bank write bursts
system.physmem.perBankRdBursts::10 3835 # Per bank write bursts
system.physmem.perBankRdBursts::11 811 # Per bank write bursts
system.physmem.perBankRdBursts::12 1140 # Per bank write bursts
system.physmem.perBankRdBursts::13 693 # Per bank write bursts
system.physmem.perBankRdBursts::14 643 # Per bank write bursts
system.physmem.perBankRdBursts::15 552 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
2015-11-06 09:26:50 +01:00
system.physmem.totGap 116576339000 # Total gap between requests
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2015-11-06 09:26:50 +01:00
system.physmem.readPktSize::6 84608 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
2015-11-06 09:26:50 +01:00
system.physmem.rdQLenPdf::0 64943 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 17781 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 471 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 311 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 234 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 214 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 178 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 159 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 176 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 53 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 21 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 22 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 18 # What read queue length does an incoming req see
2015-07-30 09:42:27 +02:00
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
2015-07-03 16:15:03 +02:00
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
2015-11-06 09:26:50 +01:00
system.physmem.bytesPerActivate::samples 22133 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 244.635973 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 206.851890 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 150.002141 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 2617 11.82% 11.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 8410 38.00% 49.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 7826 35.36% 85.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 1287 5.81% 91.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 1278 5.77% 96.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 443 2.00% 98.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 32 0.14% 98.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 31 0.14% 99.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 209 0.94% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 22133 # Bytes accessed per row activation
2016-02-10 10:08:27 +01:00
system.physmem.totQLat 841969540 # Total ticks spent queuing
system.physmem.totMemAccLat 2428369540 # Total ticks spent from burst creation until serviced by the DRAM
2015-11-06 09:26:50 +01:00
system.physmem.totBusLat 423040000 # Total ticks spent in databus transfers
2016-02-10 10:08:27 +01:00
system.physmem.avgQLat 9951.42 # Average queueing delay per DRAM burst
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2016-02-10 10:08:27 +01:00
system.physmem.avgMemAccLat 28701.42 # Average memory access latency per DRAM burst
2015-11-06 09:26:50 +01:00
system.physmem.avgRdBW 46.45 # Average DRAM read bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
2015-11-06 09:26:50 +01:00
system.physmem.avgRdBWSys 46.45 # Average system read bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2015-11-06 09:26:50 +01:00
system.physmem.busUtil 0.36 # Data bus utilization in percentage
system.physmem.busUtilRead 0.36 # Data bus utilization in percentage for reads
2013-11-01 16:56:34 +01:00
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
2015-11-06 09:26:50 +01:00
system.physmem.avgRdQLen 1.36 # Average read queue length when enqueuing
2013-11-01 16:56:34 +01:00
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
2015-11-06 09:26:50 +01:00
system.physmem.readRowHits 62473 # Number of row buffer hits during reads
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
2015-11-06 09:26:50 +01:00
system.physmem.readRowHitRate 73.84 # Row buffer hit rate for reads
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
2015-11-06 09:26:50 +01:00
system.physmem.avgGap 1377840.62 # Average gap between requests
system.physmem.pageHitRate 73.84 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 142967160 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 78007875 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 595896600 # Energy for read commands per rank (pJ)
2014-12-23 15:31:20 +01:00
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
2015-11-06 09:26:50 +01:00
system.physmem_0.refreshEnergy 7614160320 # Energy for refresh commands per rank (pJ)
2016-02-10 10:08:27 +01:00
system.physmem_0.actBackEnergy 63983019555 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 13820141250 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 86234192760 # Total energy per rank (pJ)
system.physmem_0.averagePower 739.725127 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 22625688019 # Time in different power states
2015-11-06 09:26:50 +01:00
system.physmem_0.memoryStateTime::REF 3892720000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
2016-02-10 10:08:27 +01:00
system.physmem_0.memoryStateTime::ACT 90057600731 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
2015-11-06 09:26:50 +01:00
system.physmem_1.actEnergy 24358320 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 13290750 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 63999000 # Energy for read commands per rank (pJ)
2014-12-23 15:31:20 +01:00
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
2015-11-06 09:26:50 +01:00
system.physmem_1.refreshEnergy 7614160320 # Energy for refresh commands per rank (pJ)
2016-02-10 10:08:27 +01:00
system.physmem_1.actBackEnergy 11183518845 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 60135492750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 79034819985 # Total energy per rank (pJ)
system.physmem_1.averagePower 677.968221 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 99984324847 # Time in different power states
2015-11-06 09:26:50 +01:00
system.physmem_1.memoryStateTime::REF 3892720000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
2016-02-10 10:08:27 +01:00
system.physmem_1.memoryStateTime::ACT 12698963903 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
2015-11-06 09:26:50 +01:00
system.cpu.branchPred.lookups 37744347 # Number of BP lookups
system.cpu.branchPred.condPredicted 20165678 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1746151 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 18664383 # Number of BTB lookups
system.cpu.branchPred.BTBHits 17300356 # Number of BTB hits
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2015-11-06 09:26:50 +01:00
system.cpu.branchPred.BTBHitPct 92.691818 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 7223561 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 3816 # Number of incorrect RAS predictions.
2014-12-23 15:31:20 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2011-01-18 23:30:06 +01:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
2011-05-23 17:59:13 +02:00
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2011-05-23 17:59:13 +02:00
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 191 # Number of system calls
2015-11-06 09:26:50 +01:00
system.cpu.numCycles 233152996 # number of cpu cycles simulated
2011-05-23 17:59:13 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
2015-11-06 09:26:50 +01:00
system.cpu.fetch.icacheStallCycles 12613908 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 334078036 # Number of instructions fetch has processed
system.cpu.fetch.Branches 37744347 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 24523917 # Number of branches that fetch has predicted taken
2016-02-10 10:08:27 +01:00
system.cpu.fetch.Cycles 217730977 # Number of cycles fetch has run and was not squashing or blocked
2015-11-06 09:26:50 +01:00
system.cpu.fetch.SquashCycles 3511013 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 1155 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 1 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 2593 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 89097958 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 22048 # Number of outstanding Icache misses that were squashed
2016-02-10 10:08:27 +01:00
system.cpu.fetch.rateDist::samples 232104140 # Number of instructions fetched each cycle (Total)
2015-11-06 09:26:50 +01:00
system.cpu.fetch.rateDist::mean 1.745924 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.249191 # Number of instructions fetched each cycle (Total)
2011-01-18 23:30:06 +01:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2016-02-10 10:08:27 +01:00
system.cpu.fetch.rateDist::0 58364721 25.15% 25.15% # Number of instructions fetched each cycle (Total)
2015-11-06 09:26:50 +01:00
system.cpu.fetch.rateDist::1 42980177 18.52% 43.66% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 30021674 12.93% 56.60% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 100737568 43.40% 100.00% # Number of instructions fetched each cycle (Total)
2011-01-18 23:30:06 +01:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
2014-09-20 23:18:53 +02:00
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
2016-02-10 10:08:27 +01:00
system.cpu.fetch.rateDist::total 232104140 # Number of instructions fetched each cycle (Total)
2015-11-06 09:26:50 +01:00
system.cpu.fetch.branchRate 0.161887 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.432870 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 28023980 # Number of cycles decode is idle
2016-02-10 10:08:27 +01:00
system.cpu.decode.BlockedCycles 70770832 # Number of cycles decode is blocked
2015-11-06 09:26:50 +01:00
system.cpu.decode.RunCycles 108573375 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 23115192 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1620761 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 6880073 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 135178 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 363549116 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 6170266 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 1620761 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 45363672 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 24814789 # Number of cycles rename is blocking
2016-02-10 10:08:27 +01:00
system.cpu.rename.serializeStallCycles 341984 # count of cycles rename stalled for serializing inst
2015-11-06 09:26:50 +01:00
system.cpu.rename.RunCycles 113350212 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 46612722 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 355770088 # Number of instructions processed by rename
system.cpu.rename.SquashedInsts 2890615 # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents 6644499 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 177384 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 7802434 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 21145232 # Number of times rename has blocked due to SQ full
system.cpu.rename.FullRegisterEvents 2810415 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 403411912 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 2534053104 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 350245362 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 194900491 # Number of floating rename lookups
2014-09-20 23:18:53 +02:00
system.cpu.rename.CommittedMaps 372230051 # Number of HB maps that are committed
2015-11-06 09:26:50 +01:00
system.cpu.rename.UndoneMaps 31181861 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 16825 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 16811 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 55467243 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 92417326 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 88498414 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1663819 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 1859064 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 353254299 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 27832 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 346438253 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 2301561 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 25470529 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 73751649 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 5712 # Number of squashed non-spec instructions that were removed
2016-02-10 10:08:27 +01:00
system.cpu.iq.issued_per_cycle::samples 232104140 # Number of insts issued each cycle
2015-11-06 09:26:50 +01:00
system.cpu.iq.issued_per_cycle::mean 1.492598 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.113201 # Number of insts issued each cycle
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2016-02-10 10:08:27 +01:00
system.cpu.iq.issued_per_cycle::0 47511464 20.47% 20.47% # Number of insts issued each cycle
2015-11-06 09:26:50 +01:00
system.cpu.iq.issued_per_cycle::1 78618745 33.87% 54.34% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 60884809 26.23% 80.57% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 34936770 15.05% 95.63% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 9533364 4.11% 99.73% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 607804 0.26% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 11184 0.00% 100.00% # Number of insts issued each cycle
2014-09-20 23:18:53 +02:00
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
2014-09-20 23:18:53 +02:00
system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle
2016-02-10 10:08:27 +01:00
system.cpu.iq.issued_per_cycle::total 232104140 # Number of insts issued each cycle
2011-04-20 03:45:23 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2015-11-06 09:26:50 +01:00
system.cpu.iq.fu_full::IntAlu 9573854 7.69% 7.69% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 7345 0.01% 7.69% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 7.69% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.69% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.69% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.69% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 7.69% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.69% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 7.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 7.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 255499 0.21% 7.90% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.90% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 127544 0.10% 8.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 93452 0.08% 8.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 56991 0.05% 8.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 707524 0.57% 8.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 297297 0.24% 8.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 683417 0.55% 9.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.48% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 53764278 43.17% 52.65% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 58976477 47.35% 100.00% # attempts to use FU when none available
2011-04-20 03:45:23 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2011-05-23 17:59:13 +02:00
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
2015-11-06 09:26:50 +01:00
system.cpu.iq.FU_type_0::IntAlu 110655125 31.94% 31.94% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 2148158 0.62% 32.56% # Type of FU issued
2015-03-02 11:04:20 +01:00
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.56% # Type of FU issued
2015-11-06 09:26:50 +01:00
system.cpu.iq.FU_type_0::SimdFloatAdd 6798099 1.96% 34.52% # Type of FU issued
2015-07-03 16:15:03 +02:00
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.52% # Type of FU issued
2015-11-06 09:26:50 +01:00
system.cpu.iq.FU_type_0::SimdFloatCmp 8667622 2.50% 37.03% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 3332487 0.96% 37.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 1592703 0.46% 38.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 20931016 6.04% 44.49% # Type of FU issued
2015-09-25 13:27:03 +02:00
system.cpu.iq.FU_type_0::SimdFloatMult 7182327 2.07% 46.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 7148965 2.06% 48.63% # Type of FU issued
2015-03-02 11:04:20 +01:00
system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 48.68% # Type of FU issued
2015-11-06 09:26:50 +01:00
system.cpu.iq.FU_type_0::MemRead 91923310 26.53% 75.21% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 85883155 24.79% 100.00% # Type of FU issued
2011-05-23 17:59:13 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2015-11-06 09:26:50 +01:00
system.cpu.iq.FU_type_0::total 346438253 # Type of FU issued
system.cpu.iq.rate 1.485884 # Inst issue rate
system.cpu.iq.fu_busy_cnt 124543678 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.359497 # FU busy rate (busy events/executed inst)
2016-02-10 10:08:27 +01:00
system.cpu.iq.int_inst_queue_reads 764166778 # Number of integer instruction queue reads
2015-11-06 09:26:50 +01:00
system.cpu.iq.int_inst_queue_writes 251741027 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 223260031 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 287659107 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 127022045 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 117425060 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 303322253 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 167659678 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 5063326 # Number of loads that had data forwarded from stores
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2015-11-06 09:26:50 +01:00
system.cpu.iew.lsq.thread0.squashedLoads 6685051 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 13552 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 10416 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 6122797 # Number of stores squashed
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2015-11-06 09:26:50 +01:00
system.cpu.iew.lsq.thread0.rescheduledLoads 155252 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 607596 # Number of times an access to memory failed due to the cache being blocked
2011-05-23 17:59:13 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2015-11-06 09:26:50 +01:00
system.cpu.iew.iewSquashCycles 1620761 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 2118966 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 346415 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 353282999 # Number of instructions dispatched to IQ
2014-09-20 23:18:53 +02:00
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
2015-11-06 09:26:50 +01:00
system.cpu.iew.iewDispLoadInsts 92417326 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 88498414 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 16799 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 8049 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 352915 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 10416 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 1220605 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 439066 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1659671 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 342448265 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 90703428 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 3989988 # Number of squashed instructions skipped in execute
2011-05-23 17:59:13 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
2015-11-06 09:26:50 +01:00
system.cpu.iew.exec_nop 868 # number of nop insts executed
system.cpu.iew.exec_refs 175290651 # number of memory reference insts executed
system.cpu.iew.exec_branches 31753222 # Number of branches executed
system.cpu.iew.exec_stores 84587223 # Number of stores executed
system.cpu.iew.exec_rate 1.468771 # Inst execution rate
system.cpu.iew.wb_sent 340943350 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 340685091 # cumulative count of insts written-back
system.cpu.iew.wb_producers 153596503 # num instructions producing a value
system.cpu.iew.wb_consumers 266530182 # num instructions consuming a value
system.cpu.iew.wb_rate 1.461208 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.576282 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 23083392 # The number of squashed insts skipped by commit
2013-01-08 14:54:16 +01:00
system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards
2015-11-06 09:26:50 +01:00
system.cpu.commit.branchMispredicts 1611406 # The number of times a branch was mispredicted
2016-02-10 10:08:27 +01:00
system.cpu.commit.committed_per_cycle::samples 228378913 # Number of insts commited each cycle
2015-11-06 09:26:50 +01:00
system.cpu.commit.committed_per_cycle::mean 1.435387 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.036441 # Number of insts commited each cycle
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2016-02-10 10:08:27 +01:00
system.cpu.commit.committed_per_cycle::0 94653047 41.45% 41.45% # Number of insts commited each cycle
2015-11-06 09:26:50 +01:00
system.cpu.commit.committed_per_cycle::1 70419351 30.83% 72.28% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 20855772 9.13% 81.41% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 13391170 5.86% 87.28% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 8734239 3.82% 91.10% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 4529616 1.98% 93.08% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 3006865 1.32% 94.40% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 2429241 1.06% 95.46% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 10359612 4.54% 100.00% # Number of insts commited each cycle
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2016-02-10 10:08:27 +01:00
system.cpu.commit.committed_per_cycle::total 228378913 # Number of insts commited each cycle
2015-04-30 21:17:43 +02:00
system.cpu.commit.committedInsts 273037832 # Number of instructions committed
system.cpu.commit.committedOps 327812214 # Number of ops (including micro ops) committed
2011-05-23 17:59:13 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
2014-09-20 23:18:53 +02:00
system.cpu.commit.refs 168107892 # Number of memory references committed
system.cpu.commit.loads 85732275 # Number of loads committed
2011-05-23 17:59:13 +02:00
system.cpu.commit.membars 11033 # Number of memory barriers committed
2015-04-30 21:17:43 +02:00
system.cpu.commit.branches 30563526 # Number of branches committed
2011-05-23 17:59:13 +02:00
system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions.
2014-09-20 23:18:53 +02:00
system.cpu.commit.int_insts 258331704 # Number of committed integer instructions.
system.cpu.commit.function_calls 6225114 # Number of function calls committed.
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2015-04-30 21:17:43 +02:00
system.cpu.commit.op_class_0::IntAlu 104312487 31.82% 31.82% # Class of committed instruction
2014-09-20 23:18:53 +02:00
system.cpu.commit.op_class_0::IntMult 2145917 0.65% 32.48% # Class of committed instruction
2014-09-03 13:42:59 +02:00
system.cpu.commit.op_class_0::IntDiv 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 6594343 2.01% 34.49% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 34.49% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 7943502 2.42% 36.91% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 3118180 0.95% 37.86% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 1563217 0.48% 38.34% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 19652356 6.00% 44.33% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 7136937 2.18% 46.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction
2014-09-20 23:18:53 +02:00
system.cpu.commit.op_class_0::MemRead 85732275 26.15% 74.87% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Class of committed instruction
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2015-04-30 21:17:43 +02:00
system.cpu.commit.op_class_0::total 327812214 # Class of committed instruction
2015-11-06 09:26:50 +01:00
system.cpu.commit.bw_lim_events 10359612 # number cycles where commit BW limit reached
2016-02-10 10:08:27 +01:00
system.cpu.rob.rob_reads 568912384 # The number of ROB reads
2015-11-06 09:26:50 +01:00
system.cpu.rob.rob_writes 705520379 # The number of ROB writes
system.cpu.timesIdled 58444 # Number of times that the entire CPU went into an idle state and unscheduled itself
2016-02-10 10:08:27 +01:00
system.cpu.idleCycles 1048856 # Total number of cycles that the CPU has spent unscheduled due to idling
2015-04-30 21:17:43 +02:00
system.cpu.committedInsts 273037220 # Number of Instructions Simulated
system.cpu.committedOps 327811602 # Number of Ops (including micro ops) Simulated
2015-11-06 09:26:50 +01:00
system.cpu.cpi 0.853924 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.853924 # CPI: Total CPI of All Threads
system.cpu.ipc 1.171065 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.171065 # IPC: Total IPC of All Threads
2016-03-17 18:25:11 +01:00
system.cpu.int_regfile_reads 331328732 # number of integer regfile reads
2015-11-06 09:26:50 +01:00
system.cpu.int_regfile_writes 136938455 # number of integer regfile writes
system.cpu.fp_regfile_reads 187108865 # number of floating regfile reads
system.cpu.fp_regfile_writes 132177694 # number of floating regfile writes
system.cpu.cc_regfile_reads 1297131127 # number of cc regfile reads
system.cpu.cc_regfile_writes 80243114 # number of cc regfile writes
system.cpu.misc_regfile_reads 1183136277 # number of misc regfile reads
2013-01-08 14:54:16 +01:00
system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.replacements 1533838 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.844582 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 163641356 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1534350 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 106.651909 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 84508000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.844582 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999696 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999696 # Average percentage of cache occupancy
2014-09-20 23:18:53 +02:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 91 # Occupied blocks per task id
2014-09-20 23:18:53 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.tag_accesses 336640002 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 336640002 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 82608606 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 82608606 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 80940468 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 80940468 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 70474 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 70474 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 10911 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 10911 # number of LoadLockedReq hits
2013-01-08 14:54:16 +01:00
system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
2015-11-06 09:26:50 +01:00
system.cpu.dcache.demand_hits::cpu.data 163549074 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 163549074 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 163619548 # number of overall hits
system.cpu.dcache.overall_hits::total 163619548 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 2799218 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 2799218 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1112231 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1112231 # number of WriteReq misses
2015-03-02 11:04:20 +01:00
system.cpu.dcache.SoftPFReq_misses::cpu.data 18 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 18 # number of SoftPFReq misses
2014-09-20 23:18:53 +02:00
system.cpu.dcache.LoadLockedReq_misses::cpu.data 5 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 5 # number of LoadLockedReq misses
2015-11-06 09:26:50 +01:00
system.cpu.dcache.demand_misses::cpu.data 3911449 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 3911449 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 3911467 # number of overall misses
system.cpu.dcache.overall_misses::total 3911467 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 31000710000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 31000710000 # number of ReadReq miss cycles
2016-02-10 10:08:27 +01:00
system.cpu.dcache.WriteReq_miss_latency::cpu.data 8973513996 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 8973513996 # number of WriteReq miss cycles
2015-07-03 16:15:03 +02:00
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 189000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 189000 # number of LoadLockedReq miss cycles
2016-02-10 10:08:27 +01:00
system.cpu.dcache.demand_miss_latency::cpu.data 39974223996 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 39974223996 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 39974223996 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 39974223996 # number of overall miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.dcache.ReadReq_accesses::cpu.data 85407824 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 85407824 # number of ReadReq accesses(hits+misses)
2014-09-20 23:18:53 +02:00
system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses)
2015-11-06 09:26:50 +01:00
system.cpu.dcache.SoftPFReq_accesses::cpu.data 70492 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 70492 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10916 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 10916 # number of LoadLockedReq accesses(hits+misses)
2013-01-08 14:54:16 +01:00
system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
2015-11-06 09:26:50 +01:00
system.cpu.dcache.demand_accesses::cpu.data 167460523 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 167460523 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 167531015 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 167531015 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032775 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.032775 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013555 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.013555 # miss rate for WriteReq accesses
2015-03-02 11:04:20 +01:00
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000255 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.000255 # miss rate for SoftPFReq accesses
2014-09-20 23:18:53 +02:00
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000458 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000458 # miss rate for LoadLockedReq accesses
2015-11-06 09:26:50 +01:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.023357 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.023357 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.023348 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.023348 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11074.775169 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 11074.775169 # average ReadReq miss latency
2016-02-10 10:08:27 +01:00
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8068.030828 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 8068.030828 # average WriteReq miss latency
2015-07-03 16:15:03 +02:00
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37800 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37800 # average LoadLockedReq miss latency
2016-02-10 10:08:27 +01:00
system.cpu.dcache.demand_avg_miss_latency::cpu.data 10219.799362 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 10219.799362 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 10219.752332 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 10219.752332 # average overall miss latency
2014-12-23 15:31:20 +01:00
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.cpu.dcache.blocked_cycles::no_targets 1061203 # number of cycles access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.cpu.dcache.blocked::no_targets 134969 # number of cycles access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2015-11-06 09:26:50 +01:00
system.cpu.dcache.avg_blocked_cycles::no_targets 7.862568 # average number of cycles each access was blocked
2013-01-07 19:05:54 +01:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
2015-11-06 09:26:50 +01:00
system.cpu.dcache.writebacks::writebacks 1533838 # number of writebacks
system.cpu.dcache.writebacks::total 1533838 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1485532 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 1485532 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 891576 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 891576 # number of WriteReq MSHR hits
2014-09-20 23:18:53 +02:00
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 5 # number of LoadLockedReq MSHR hits
2015-11-06 09:26:50 +01:00
system.cpu.dcache.demand_mshr_hits::cpu.data 2377108 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 2377108 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 2377108 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 2377108 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313686 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1313686 # number of ReadReq MSHR misses
2015-07-03 16:15:03 +02:00
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220655 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 220655 # number of WriteReq MSHR misses
2014-09-20 23:18:53 +02:00
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 11 # number of SoftPFReq MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.dcache.demand_mshr_misses::cpu.data 1534341 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1534341 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1534352 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1534352 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15231288500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 15231288500 # number of ReadReq MSHR miss cycles
2016-02-10 10:08:27 +01:00
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1828348773 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1828348773 # number of WriteReq MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 681500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 681500 # number of SoftPFReq MSHR miss cycles
2016-02-10 10:08:27 +01:00
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17059637273 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 17059637273 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17060318773 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 17060318773 # number of overall MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015381 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015381 # mshr miss rate for ReadReq accesses
2015-03-02 11:04:20 +01:00
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002689 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002689 # mshr miss rate for WriteReq accesses
2014-09-20 23:18:53 +02:00
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000156 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000156 # mshr miss rate for SoftPFReq accesses
2015-11-06 09:26:50 +01:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009162 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.009162 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009159 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.009159 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11594.314395 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11594.314395 # average ReadReq mshr miss latency
2016-02-10 10:08:27 +01:00
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8286.006540 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8286.006540 # average WriteReq mshr miss latency
2015-11-06 09:26:50 +01:00
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61954.545455 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61954.545455 # average SoftPFReq mshr miss latency
2016-02-10 10:08:27 +01:00
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11118.543579 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11118.543579 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11118.908030 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11118.908030 # average overall mshr miss latency
2013-01-07 19:05:54 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-11-06 09:26:50 +01:00
system.cpu.icache.tags.replacements 715978 # number of replacements
system.cpu.icache.tags.tagsinuse 511.829667 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 88375700 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 716490 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 123.345336 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 330590500 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 511.829667 # Average occupied blocks per requestor
2015-07-30 09:42:27 +02:00
system.cpu.icache.tags.occ_percent::cpu.inst 0.999667 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.999667 # Average percentage of cache occupancy
2014-12-23 15:31:20 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2015-07-03 16:15:03 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 246 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id
2015-03-02 11:04:20 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::4 69 # Occupied blocks per task id
2014-12-23 15:31:20 +01:00
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2015-11-06 09:26:50 +01:00
system.cpu.icache.tags.tag_accesses 178912379 # Number of tag accesses
system.cpu.icache.tags.data_accesses 178912379 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 88375700 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 88375700 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 88375700 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 88375700 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 88375700 # number of overall hits
system.cpu.icache.overall_hits::total 88375700 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 722244 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 722244 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 722244 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 722244 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 722244 # number of overall misses
system.cpu.icache.overall_misses::total 722244 # number of overall misses
2016-02-10 10:08:27 +01:00
system.cpu.icache.ReadReq_miss_latency::cpu.inst 6486047445 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 6486047445 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 6486047445 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 6486047445 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 6486047445 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 6486047445 # number of overall miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.icache.ReadReq_accesses::cpu.inst 89097944 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 89097944 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 89097944 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 89097944 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 89097944 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 89097944 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008106 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.008106 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.008106 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.008106 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.008106 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.008106 # miss rate for overall accesses
2016-02-10 10:08:27 +01:00
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8980.410284 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 8980.410284 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 8980.410284 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 8980.410284 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 8980.410284 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 8980.410284 # average overall miss latency
2015-11-06 09:26:50 +01:00
system.cpu.icache.blocked_cycles::no_mshrs 66919 # number of cycles access was blocked
2015-07-03 16:15:03 +02:00
system.cpu.icache.blocked_cycles::no_targets 94 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.cpu.icache.blocked::no_mshrs 2190 # number of cycles access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 30.556621 # average number of cycles each access was blocked
2015-07-03 16:15:03 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets 31.333333 # average number of cycles each access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
2015-11-06 09:26:50 +01:00
system.cpu.icache.writebacks::writebacks 715978 # number of writebacks
system.cpu.icache.writebacks::total 715978 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 5753 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 5753 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 5753 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 5753 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 5753 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 5753 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 716491 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 716491 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 716491 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 716491 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 716491 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 716491 # number of overall MSHR misses
2016-02-10 10:08:27 +01:00
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6035135455 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 6035135455 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6035135455 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 6035135455 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6035135455 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 6035135455 # number of overall MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008042 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008042 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008042 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.008042 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008042 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.008042 # mshr miss rate for overall accesses
2016-02-10 10:08:27 +01:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8423.183899 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8423.183899 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8423.183899 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 8423.183899 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8423.183899 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 8423.183899 # average overall mshr miss latency
2014-12-23 15:31:20 +01:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.prefetcher.num_hwpf_issued 404830 # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified 404871 # number of prefetch candidates identified
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.prefetcher.pfBufferHit 38 # number of redundant prefetches already in prefetch queue
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.prefetcher.pfSpanPage 28177 # number of prefetches not generated due to page crossing
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.tags.replacements 0 # number of replacements
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.tags.tagsinuse 5610.545509 # Cycle average of tags in use
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.total_refs 3011470 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 6745 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 446.474426 # Average number of references to valid blocks.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.tags.occ_blocks::writebacks 5502.326450 # Average occupied blocks per requestor
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 108.219059 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.335835 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.006605 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.342441 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022 498 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 6247 # Occupied blocks per task id
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1022::0 16 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1 22 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::2 344 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1022::3 2 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::4 114 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 906 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 71 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 5055 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022 0.030396 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.381287 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 68984443 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 68984443 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 965413 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 965413 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 1035068 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 1035068 # number of WritebackClean hits
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadExReq_hits::cpu.data 219881 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 219881 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 706254 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 706254 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1242123 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 1242123 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 706254 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 1462004 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2168258 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 706254 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 1462004 # number of overall hits
system.cpu.l2cache.overall_hits::total 2168258 # number of overall hits
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 772 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 772 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 9709 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 9709 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 71574 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 71574 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 9709 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 72346 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 82055 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 9709 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 72346 # number of overall misses
system.cpu.l2cache.overall_misses::total 82055 # number of overall misses
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 19500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 19500 # number of UpgradeReq miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 55912000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 55912000 # number of ReadExReq miss cycles
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 697540000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 697540000 # number of ReadCleanReq miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5069165500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 5069165500 # number of ReadSharedReq miss cycles
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.demand_miss_latency::cpu.inst 697540000 # number of demand (read+write) miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_miss_latency::cpu.data 5125077500 # number of demand (read+write) miss cycles
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.demand_miss_latency::total 5822617500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 697540000 # number of overall miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_miss_latency::cpu.data 5125077500 # number of overall miss cycles
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.overall_miss_latency::total 5822617500 # number of overall miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.WritebackDirty_accesses::writebacks 965413 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 965413 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 1035068 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 1035068 # number of WritebackClean accesses(hits+misses)
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses)
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 220653 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 220653 # number of ReadExReq accesses(hits+misses)
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 715963 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 715963 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1313697 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 1313697 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 715963 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1534350 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2250313 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 715963 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1534350 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2250313 # number of overall (read+write) accesses
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.500000 # miss rate for UpgradeReq accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003499 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.003499 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.013561 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.013561 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.054483 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.054483 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.013561 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.047151 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.036464 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.013561 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.047151 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.036464 # miss rate for overall accesses
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 19500 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 19500 # average UpgradeReq miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72424.870466 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72424.870466 # average ReadExReq miss latency
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 71844.680194 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 71844.680194 # average ReadCleanReq miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 70824.119094 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 70824.119094 # average ReadSharedReq miss latency
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71844.680194 # average overall miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70841.200619 # average overall miss latency
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.demand_avg_miss_latency::total 70959.935409 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71844.680194 # average overall miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70841.200619 # average overall miss latency
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.overall_avg_miss_latency::total 70959.935409 # average overall miss latency
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 44 # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total 44 # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 12 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 12 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 33 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 33 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 77 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 89 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 77 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 89 # number of overall MSHR hits
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 51610 # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total 51610 # number of HardPFReq MSHR misses
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 728 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 728 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 9697 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 9697 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 71541 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 71541 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 9697 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 72269 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 81966 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 9697 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 72269 # number of overall MSHR misses
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 51610 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 133576 # number of overall MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 180856312 # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 180856312 # number of HardPFReq MSHR miss cycles
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 13500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 13500 # number of UpgradeReq MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 50141500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 50141500 # number of ReadExReq MSHR miss cycles
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 638754500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 638754500 # number of ReadCleanReq MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4638052000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4638052000 # number of ReadSharedReq MSHR miss cycles
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 638754500 # number of demand (read+write) MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4688193500 # number of demand (read+write) MSHR miss cycles
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.demand_mshr_miss_latency::total 5326948000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 638754500 # number of overall MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4688193500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 180856312 # number of overall MSHR miss cycles
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.overall_mshr_miss_latency::total 5507804312 # number of overall MSHR miss cycles
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003299 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003299 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.013544 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.013544 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.054458 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.054458 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.013544 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.047101 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.036424 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.013544 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.047101 # mshr miss rate for overall accesses
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::total 0.059359 # mshr miss rate for overall accesses
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3504.288161 # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3504.288161 # average HardPFReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13500 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13500 # average UpgradeReq mshr miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68875.686813 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68875.686813 # average ReadExReq mshr miss latency
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65871.351965 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65871.351965 # average ReadCleanReq mshr miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64830.684503 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64830.684503 # average ReadSharedReq mshr miss latency
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65871.351965 # average overall mshr miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64871.431734 # average overall mshr miss latency
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64989.727448 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65871.351965 # average overall mshr miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64871.431734 # average overall mshr miss latency
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3504.288161 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41233.487393 # average overall mshr miss latency
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoop_filter.tot_requests 4500659 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2249836 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 249343 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-02-10 10:08:27 +01:00
system.cpu.toL2Bus.snoop_filter.tot_snoops 130206 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 52860 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 77346 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 2030188 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 965413 # Transaction distribution
2016-02-10 10:08:27 +01:00
system.cpu.toL2Bus.trans_dist::WritebackClean 1284403 # Transaction distribution
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.trans_dist::CleanEvict 81238 # Transaction distribution
2016-02-10 10:08:27 +01:00
system.cpu.toL2Bus.trans_dist::HardPFReq 52998 # Transaction distribution
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.trans_dist::ReadExReq 220653 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 220653 # Transaction distribution
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.trans_dist::ReadCleanReq 716491 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1313697 # Transaction distribution
2016-02-10 10:08:27 +01:00
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2148432 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4602542 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 6750974 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 91644224 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 196364032 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 288008256 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 134764 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 2385079 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.191572 # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoop_fanout::stdev 0.468754 # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoop_fanout::0 2005511 84.09% 84.09% # Request fanout histogram
2016-02-10 10:08:27 +01:00
system.cpu.toL2Bus.snoop_fanout::1 302222 12.67% 96.76% # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoop_fanout::2 77346 3.24% 100.00% # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2016-02-10 10:08:27 +01:00
system.cpu.toL2Bus.snoop_fanout::total 2385079 # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.reqLayer0.occupancy 4500145500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 3.9 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1075017936 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 2302043463 # Layer occupancy (ticks)
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.membus.trans_dist::ReadResp 83880 # Transaction distribution
2014-12-23 15:31:20 +01:00
system.membus.trans_dist::UpgradeReq 1 # Transaction distribution
2015-11-06 09:26:50 +01:00
system.membus.trans_dist::ReadExReq 728 # Transaction distribution
system.membus.trans_dist::ReadExResp 728 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 83880 # Transaction distribution
2016-02-10 10:08:27 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 169217 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 169217 # Packet count per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 5414912 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 5414912 # Cumulative packet size per connected master and slave (bytes)
2014-12-23 15:31:20 +01:00
system.membus.snoops 0 # Total snoops (count)
2015-11-06 09:26:50 +01:00
system.membus.snoop_fanout::samples 84609 # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.membus.snoop_fanout::0 84609 100.00% 100.00% # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.membus.snoop_fanout::total 84609 # Request fanout histogram
system.membus.reqLayer0.occupancy 103435410 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
2016-02-10 10:08:27 +01:00
system.membus.respLayer1.occupancy 446648668 # Layer occupancy (ticks)
2015-11-06 09:26:50 +01:00
system.membus.respLayer1.utilization 0.4 # Layer utilization (%)
2011-01-18 23:30:06 +01:00
---------- End Simulation Statistics ----------
