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gem5/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt

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ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
---------- Begin Simulation Statistics ----------
stats: arm: updates
2015-04-30 21:17:43 +02:00
sim_seconds 0.112557 # Number of seconds simulated
sim_ticks 112556618500 # Number of ticks simulated
final_tick 112556618500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
host_inst_rate 125639 # Simulator instruction rate (inst/s)
host_op_rate 150843 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 51793233 # Simulator tick rate (ticks/s)
host_mem_usage 327772 # Number of bytes of host memory used
host_seconds 2173.19 # Real time elapsed on the host
stats: arm: updates
2015-04-30 21:17:43 +02:00
sim_insts 273037220 # Number of instructions simulated
sim_ops 327811602 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.physmem.bytes_read::cpu.inst 187072 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 117696 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher 162752 # Number of bytes read from this memory
system.physmem.bytes_read::total 467520 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 187072 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 187072 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 2923 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1839 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher 2543 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7305 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1662026 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1045660 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher 1445957 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 4153643 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1662026 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1662026 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1662026 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1045660 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher 1445957 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 4153643 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 7305 # Number of read requests accepted
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writeReqs 0 # Number of write requests accepted
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.physmem.readBursts 7305 # Number of DRAM read bursts, including those serviced by the write queue
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.physmem.bytesReadDRAM 467520 # Total number of bytes read from DRAM
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.physmem.bytesReadSys 467520 # Total read bytes from the system interface side
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.neitherReadNorWriteReqs 1 # Number of requests that are neither read nor write
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.perBankRdBursts::0 589 # Per bank write bursts
system.physmem.perBankRdBursts::1 789 # Per bank write bursts
system.physmem.perBankRdBursts::2 601 # Per bank write bursts
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.perBankRdBursts::3 520 # Per bank write bursts
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.perBankRdBursts::4 444 # Per bank write bursts
system.physmem.perBankRdBursts::5 346 # Per bank write bursts
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.physmem.perBankRdBursts::6 146 # Per bank write bursts
system.physmem.perBankRdBursts::7 247 # Per bank write bursts
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.perBankRdBursts::8 219 # Per bank write bursts
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.perBankRdBursts::9 290 # Per bank write bursts
system.physmem.perBankRdBursts::10 315 # Per bank write bursts
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.perBankRdBursts::11 411 # Per bank write bursts
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.physmem.perBankRdBursts::12 540 # Per bank write bursts
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.perBankRdBursts::13 678 # Per bank write bursts
system.physmem.perBankRdBursts::14 615 # Per bank write bursts
system.physmem.perBankRdBursts::15 555 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.physmem.totGap 112556460000 # Total gap between requests
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.physmem.readPktSize::6 7305 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.physmem.rdQLenPdf::0 4013 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 1460 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 489 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 289 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 237 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 191 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 168 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 137 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 186 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 52 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 20 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 17 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 16 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.physmem.bytesPerActivate::samples 1395 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 333.121147 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 192.861490 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 347.787983 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 501 35.91% 35.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 324 23.23% 59.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 138 9.89% 69.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 72 5.16% 74.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 60 4.30% 78.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 40 2.87% 81.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 25 1.79% 83.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 33 2.37% 85.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 202 14.48% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1395 # Bytes accessed per row activation
system.physmem.totQLat 103629565 # Total ticks spent queuing
system.physmem.totMemAccLat 240598315 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 36525000 # Total ticks spent in databus transfers
system.physmem.avgQLat 14186.11 # Average queueing delay per DRAM burst
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.physmem.avgMemAccLat 32936.11 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 4.15 # Average DRAM read bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.physmem.avgRdBWSys 4.15 # Average system read bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.physmem.avgRdQLen 1.37 # Average read queue length when enqueuing
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.physmem.readRowHits 5900 # Number of row buffer hits during reads
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.physmem.readRowHitRate 80.77 # Row buffer hit rate for reads
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.physmem.avgGap 15408139.63 # Average gap between requests
system.physmem.pageHitRate 80.77 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 4800600 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 2619375 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 28509000 # Energy for read commands per rank (pJ)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem_0.refreshEnergy 7351234800 # Energy for refresh commands per rank (pJ)
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.physmem_0.actBackEnergy 3210095790 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 64714428750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 75311688315 # Total energy per rank (pJ)
system.physmem_0.averagePower 669.136839 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 107655127862 # Time in different power states
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem_0.memoryStateTime::REF 3758300000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.physmem_0.memoryStateTime::ACT 1137230638 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.physmem_1.actEnergy 5692680 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 3106125 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 28033200 # Energy for read commands per rank (pJ)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem_1.refreshEnergy 7351234800 # Energy for refresh commands per rank (pJ)
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.physmem_1.actBackEnergy 3321763065 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 64616466750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 75326296620 # Total energy per rank (pJ)
system.physmem_1.averagePower 669.266714 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 107490739638 # Time in different power states
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem_1.memoryStateTime::REF 3758300000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.physmem_1.memoryStateTime::ACT 1301464112 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.branchPred.lookups 37745745 # Number of BP lookups
system.cpu.branchPred.condPredicted 20165036 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1746193 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 18664433 # Number of BTB lookups
system.cpu.branchPred.BTBHits 17299757 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.branchPred.BTBHitPct 92.688361 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 7225644 # Number of times the RAS was used to get a target.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.branchPred.RASInCorrect 3815 # Number of incorrect RAS predictions.
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 191 # Number of system calls
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.numCycles 225113238 # number of cpu cycles simulated
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.fetch.icacheStallCycles 12251417 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 334051298 # Number of instructions fetch has processed
system.cpu.fetch.Branches 37745745 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 24525401 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 210778013 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 3510671 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 1214 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.IcacheWaitRetryStallCycles 2374 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 89095174 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 21831 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 224788353 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.802613 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.228565 # Number of instructions fetched each cycle (Total)
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.fetch.rateDist::0 51103569 22.73% 22.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 42898008 19.08% 41.82% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 30051948 13.37% 55.19% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 100734828 44.81% 100.00% # Number of instructions fetched each cycle (Total)
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.fetch.rateDist::total 224788353 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.167674 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.483926 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 27670582 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 63851253 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 108576447 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 23069494 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1620577 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 6880022 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 135197 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 363530011 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 6168132 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 1620577 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 44985380 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 17900890 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 342489 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 113387887 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 46551130 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 355747905 # Number of instructions processed by rename
system.cpu.rename.SquashedInsts 2899336 # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents 6599141 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 195125 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 7751977 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 21225499 # Number of times rename has blocked due to SQ full
system.cpu.rename.FullRegisterEvents 2892433 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 403402217 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 2533894130 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 350207887 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 194891394 # Number of floating rename lookups
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.rename.CommittedMaps 372230051 # Number of HB maps that are committed
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.rename.UndoneMaps 31172166 # Number of HB maps that are undone due to squashing
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.rename.serializingInsts 17015 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 17024 # count of temporary serializing insts renamed
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.rename.skidInsts 55319848 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 92416628 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 88482470 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1658909 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 1843123 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 353235356 # Number of instructions added to the IQ (excludes non-spec)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iq.iqNonSpecInstsAdded 28024 # Number of non-speculative instructions added to the IQ
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.iq.iqInstsIssued 346405014 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 2300418 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 25451778 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 73600174 # Number of squashed operands that are examined and possibly removed from graph
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iq.iqSquashedNonSpecRemoved 5904 # Number of squashed non-spec instructions that were removed
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.iq.issued_per_cycle::samples 224788353 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.541027 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.099686 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.iq.issued_per_cycle::0 40435382 17.99% 17.99% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 78271933 34.82% 52.81% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 61035531 27.15% 79.96% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 34789384 15.48% 95.44% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 9595504 4.27% 99.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 651863 0.29% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 8756 0.00% 100.00% # Number of insts issued each cycle
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.iq.issued_per_cycle::total 224788353 # Number of insts issued each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.iq.fu_full::IntAlu 9471637 7.62% 7.62% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 7328 0.01% 7.63% # attempts to use FU when none available
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iq.fu_full::IntDiv 0 0.00% 7.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 7.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 7.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 7.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.63% # attempts to use FU when none available
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.iq.fu_full::SimdFloatAdd 257062 0.21% 7.83% # attempts to use FU when none available
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.83% # attempts to use FU when none available
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.iq.fu_full::SimdFloatCmp 126985 0.10% 7.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 92941 0.07% 8.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 68002 0.05% 8.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 719490 0.58% 8.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 316341 0.25% 8.90% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 682827 0.55% 9.45% # attempts to use FU when none available
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.45% # attempts to use FU when none available
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.iq.fu_full::MemRead 53603507 43.13% 52.57% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 58947270 47.43% 100.00% # attempts to use FU when none available
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.iq.FU_type_0::IntAlu 110656004 31.94% 31.94% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 2148356 0.62% 32.56% # Type of FU issued
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.56% # Type of FU issued
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.iq.FU_type_0::SimdFloatAdd 6798499 1.96% 34.53% # Type of FU issued
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.53% # Type of FU issued
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.iq.FU_type_0::SimdFloatCmp 8668326 2.50% 37.03% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 3332485 0.96% 37.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 1592467 0.46% 38.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 20930113 6.04% 44.49% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 7182308 2.07% 46.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 7148959 2.06% 48.63% # Type of FU issued
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 48.68% # Type of FU issued
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.iq.FU_type_0::MemRead 91886991 26.53% 75.21% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 85885220 24.79% 100.00% # Type of FU issued
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.iq.FU_type_0::total 346405014 # Type of FU issued
system.cpu.iq.rate 1.538803 # Inst issue rate
system.cpu.iq.fu_busy_cnt 124293390 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.358809 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 756692141 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 251708637 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 223263072 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 287500048 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 127016707 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 117424886 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 303165485 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 167532919 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 5066153 # Number of loads that had data forwarded from stores
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 6684353 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 13689 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 10190 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 6106853 # Number of stores squashed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.iew.lsq.thread0.rescheduledLoads 154467 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 567717 # Number of times an access to memory failed due to the cache being blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.iew.iewSquashCycles 1620577 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 2121612 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 331103 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 353264247 # Number of instructions dispatched to IQ
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.iew.iewDispLoadInsts 92416628 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 88482470 # Number of dispatched store instructions
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iew.iewDispNonSpecInsts 16991 # Number of dispatched non-speculative instructions
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.iew.iewIQFullEvents 8045 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 337585 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 10190 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 1220609 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 439082 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1659691 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 342414524 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 90667106 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 3990490 # Number of squashed instructions skipped in execute
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iew.exec_nop 867 # number of nop insts executed
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.iew.exec_refs 175256113 # number of memory reference insts executed
system.cpu.iew.exec_branches 31752933 # Number of branches executed
system.cpu.iew.exec_stores 84589007 # Number of stores executed
system.cpu.iew.exec_rate 1.521077 # Inst execution rate
system.cpu.iew.wb_sent 340946411 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 340687958 # cumulative count of insts written-back
system.cpu.iew.wb_producers 153730891 # num instructions producing a value
system.cpu.iew.wb_consumers 266895127 # num instructions consuming a value
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.iew.wb_rate 1.513407 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.575997 # average fanout of values written-back
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.commit.commitSquashedInsts 23077429 # The number of squashed insts skipped by commit
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.commit.branchMispredicts 1611435 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 221063225 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.482889 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.052142 # Number of insts commited each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.commit.committed_per_cycle::0 87359166 39.52% 39.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 70369846 31.83% 71.35% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 20804571 9.41% 80.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 13442893 6.08% 86.84% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 8809424 3.99% 90.83% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 4514904 2.04% 92.87% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 2991184 1.35% 94.22% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 2424669 1.10% 95.32% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 10346568 4.68% 100.00% # Number of insts commited each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.commit.committed_per_cycle::total 221063225 # Number of insts commited each cycle
system.cpu.commit.committedInsts 273037832 # Number of instructions committed
system.cpu.commit.committedOps 327812214 # Number of ops (including micro ops) committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.commit.refs 168107892 # Number of memory references committed
system.cpu.commit.loads 85732275 # Number of loads committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.membars 11033 # Number of memory barriers committed
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.commit.branches 30563526 # Number of branches committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions.
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.commit.int_insts 258331704 # Number of committed integer instructions.
system.cpu.commit.function_calls 6225114 # Number of function calls committed.
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.commit.op_class_0::IntAlu 104312487 31.82% 31.82% # Class of committed instruction
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.commit.op_class_0::IntMult 2145917 0.65% 32.48% # Class of committed instruction
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.commit.op_class_0::IntDiv 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 6594343 2.01% 34.49% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 34.49% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 7943502 2.42% 36.91% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 3118180 0.95% 37.86% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 1563217 0.48% 38.34% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 19652356 6.00% 44.33% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 7136937 2.18% 46.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.commit.op_class_0::MemRead 85732275 26.15% 74.87% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Class of committed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.commit.op_class_0::total 327812214 # Class of committed instruction
system.cpu.commit.bw_lim_events 10346568 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 561603777 # The number of ROB reads
system.cpu.rob.rob_writes 705508335 # The number of ROB writes
system.cpu.timesIdled 50687 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 324885 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 273037220 # Number of Instructions Simulated
system.cpu.committedOps 327811602 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 0.824478 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.824478 # CPI: Total CPI of All Threads
system.cpu.ipc 1.212888 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.212888 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 331301011 # number of integer regfile reads
system.cpu.int_regfile_writes 136940115 # number of integer regfile writes
system.cpu.fp_regfile_reads 187107432 # number of floating regfile reads
system.cpu.fp_regfile_writes 132177980 # number of floating regfile writes
system.cpu.cc_regfile_reads 1297030870 # number of cc regfile reads
system.cpu.cc_regfile_writes 80242369 # number of cc regfile writes
system.cpu.misc_regfile_reads 1182848919 # number of misc regfile reads
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.tags.replacements 1533856 # number of replacements
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.dcache.tags.tagsinuse 511.842901 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 163689178 # Total number of references to valid blocks.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.tags.sampled_refs 1534368 # Sample count of references to valid blocks.
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.dcache.tags.avg_refs 106.681825 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 84489000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.842901 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999693 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999693 # Average percentage of cache occupancy
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 312 # Occupied blocks per task id
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.dcache.tags.tag_accesses 336633512 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 336633512 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 82631334 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 82631334 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 80965560 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 80965560 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 70478 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 70478 # number of SoftPFReq hits
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.LoadLockedReq_hits::cpu.data 10909 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 10909 # number of LoadLockedReq hits
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.dcache.demand_hits::cpu.data 163596894 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 163596894 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 163667372 # number of overall hits
system.cpu.dcache.overall_hits::total 163667372 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 2773234 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 2773234 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1087139 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1087139 # number of WriteReq misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.SoftPFReq_misses::cpu.data 18 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 18 # number of SoftPFReq misses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.dcache.LoadLockedReq_misses::cpu.data 5 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 5 # number of LoadLockedReq misses
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.dcache.demand_misses::cpu.data 3860373 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 3860373 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 3860391 # number of overall misses
system.cpu.dcache.overall_misses::total 3860391 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 22353219965 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 22353219965 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 8921439031 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 8921439031 # number of WriteReq miss cycles
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 189750 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 189750 # number of LoadLockedReq miss cycles
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.dcache.demand_miss_latency::cpu.data 31274658996 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 31274658996 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 31274658996 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 31274658996 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 85404568 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 85404568 # number of ReadReq accesses(hits+misses)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses)
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.dcache.SoftPFReq_accesses::cpu.data 70496 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 70496 # number of SoftPFReq accesses(hits+misses)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10914 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 10914 # number of LoadLockedReq accesses(hits+misses)
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.dcache.demand_accesses::cpu.data 167457267 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 167457267 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 167527763 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 167527763 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032472 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.032472 # miss rate for ReadReq accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013249 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.013249 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000255 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.000255 # miss rate for SoftPFReq accesses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000458 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000458 # miss rate for LoadLockedReq accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.023053 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.023053 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.023043 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.023043 # miss rate for overall accesses
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 8060.343976 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 8060.343976 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8206.346227 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 8206.346227 # average WriteReq miss latency
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37950 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37950 # average LoadLockedReq miss latency
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.dcache.demand_avg_miss_latency::cpu.data 8101.460402 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 8101.460402 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 8101.422627 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 8101.422627 # average overall miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.dcache.blocked_cycles::no_targets 920181 # number of cycles access was blocked
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.dcache.blocked::no_targets 117395 # number of cycles access was blocked
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.dcache.avg_blocked_cycles::no_targets 7.838332 # average number of cycles each access was blocked
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.writebacks::writebacks 966341 # number of writebacks
system.cpu.dcache.writebacks::total 966341 # number of writebacks
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1459520 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 1459520 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 866494 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 866494 # number of WriteReq MSHR hits
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 5 # number of LoadLockedReq MSHR hits
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.dcache.demand_mshr_hits::cpu.data 2326014 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 2326014 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 2326014 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 2326014 # number of overall MSHR hits
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313714 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1313714 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220645 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 220645 # number of WriteReq MSHR misses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 11 # number of SoftPFReq MSHR misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.demand_mshr_misses::cpu.data 1534359 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1534359 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1534370 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1534370 # number of overall MSHR misses
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9970454284 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9970454284 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1720952041 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1720952041 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 709000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 709000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11691406325 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 11691406325 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11692115325 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 11692115325 # number of overall MSHR miss cycles
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015382 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015382 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002689 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002689 # mshr miss rate for WriteReq accesses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000156 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000156 # mshr miss rate for SoftPFReq accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009163 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.009163 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009159 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.009159 # mshr miss rate for overall accesses
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7589.516656 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7589.516656 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7799.642145 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7799.642145 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 64454.545455 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 64454.545455 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7619.733273 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 7619.733273 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7620.140726 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 7620.140726 # average overall mshr miss latency
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.icache.tags.replacements 715712 # number of replacements
system.cpu.icache.tags.tagsinuse 511.827844 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 88374047 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 716224 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 123.388838 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 326692250 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 511.827844 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.999664 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.999664 # Average percentage of cache occupancy
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 245 # Occupied blocks per task id
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 69 # Occupied blocks per task id
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.icache.tags.tag_accesses 178906541 # Number of tag accesses
system.cpu.icache.tags.data_accesses 178906541 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 88374047 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 88374047 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 88374047 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 88374047 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 88374047 # number of overall hits
system.cpu.icache.overall_hits::total 88374047 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 721111 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 721111 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 721111 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 721111 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 721111 # number of overall misses
system.cpu.icache.overall_misses::total 721111 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 5974650710 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 5974650710 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 5974650710 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 5974650710 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 5974650710 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 5974650710 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 89095158 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 89095158 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 89095158 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 89095158 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 89095158 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 89095158 # number of overall (read+write) accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008094 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.008094 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.008094 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.008094 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.008094 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.008094 # miss rate for overall accesses
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8285.341244 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 8285.341244 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 8285.341244 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 8285.341244 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 8285.341244 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 8285.341244 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 59670 # number of cycles access was blocked
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.blocked_cycles::no_targets 95 # number of cycles access was blocked
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.icache.blocked::no_mshrs 2032 # number of cycles access was blocked
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 29.365157 # average number of cycles each access was blocked
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.avg_blocked_cycles::no_targets 31.666667 # average number of cycles each access was blocked
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4886 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 4886 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 4886 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 4886 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 4886 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 4886 # number of overall MSHR hits
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 716225 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 716225 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 716225 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 716225 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 716225 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 716225 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 5193352944 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 5193352944 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 5193352944 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 5193352944 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5193352944 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 5193352944 # number of overall MSHR miss cycles
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008039 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008039 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008039 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.008039 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008039 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.008039 # mshr miss rate for overall accesses
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7251.007636 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7251.007636 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7251.007636 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 7251.007636 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7251.007636 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 7251.007636 # average overall mshr miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.l2cache.prefetcher.num_hwpf_issued 405309 # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified 405577 # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit 209 # number of redundant prefetches already in prefetch queue
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.l2cache.prefetcher.pfSpanPage 27975 # number of prefetches not generated due to page crossing
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.tags.replacements 0 # number of replacements
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.l2cache.tags.tagsinuse 5974.758413 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 2806551 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 7279 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 385.568210 # Average number of references to valid blocks.
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.l2cache.tags.occ_blocks::writebacks 2575.130596 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2680.592596 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 609.586326 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 109.448896 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.157173 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.163610 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.037206 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.006680 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.364670 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022 497 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 6782 # Occupied blocks per task id
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1022::0 16 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1 22 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::2 344 # Occupied blocks per task id
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.l2cache.tags.age_task_id_blocks_1022::4 115 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 773 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 127 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 5741 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022 0.030334 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.413940 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 51684404 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 51684404 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 712384 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 1312658 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2025042 # number of ReadReq hits
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.Writeback_hits::writebacks 966341 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 966341 # number of Writeback hits
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.l2cache.ReadExReq_hits::cpu.data 219788 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 219788 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 712384 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 1532446 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2244830 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 712384 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 1532446 # number of overall hits
system.cpu.l2cache.overall_hits::total 2244830 # number of overall hits
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.ReadReq_misses::cpu.inst 2935 # number of ReadReq misses
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.l2cache.ReadReq_misses::cpu.data 1067 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 4002 # number of ReadReq misses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 855 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 855 # number of ReadExReq misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.demand_misses::cpu.inst 2935 # number of demand (read+write) misses
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.l2cache.demand_misses::cpu.data 1922 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 4857 # number of demand (read+write) misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.overall_misses::cpu.inst 2935 # number of overall misses
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.l2cache.overall_misses::cpu.data 1922 # number of overall misses
system.cpu.l2cache.overall_misses::total 4857 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 201263959 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 77652750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 278916709 # number of ReadReq miss cycles
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23499 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 23499 # number of UpgradeReq miss cycles
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 61582748 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 61582748 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 201263959 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 139235498 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 340499457 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 201263959 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 139235498 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 340499457 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 715319 # number of ReadReq accesses(hits+misses)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.ReadReq_accesses::cpu.data 1313725 # number of ReadReq accesses(hits+misses)
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.l2cache.ReadReq_accesses::total 2029044 # number of ReadReq accesses(hits+misses)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.Writeback_accesses::writebacks 966341 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 966341 # number of Writeback accesses(hits+misses)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 220643 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 220643 # number of ReadExReq accesses(hits+misses)
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.l2cache.demand_accesses::cpu.inst 715319 # number of demand (read+write) accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.demand_accesses::cpu.data 1534368 # number of demand (read+write) accesses
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.l2cache.demand_accesses::total 2249687 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 715319 # number of overall (read+write) accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.overall_accesses::cpu.data 1534368 # number of overall (read+write) accesses
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.l2cache.overall_accesses::total 2249687 # number of overall (read+write) accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.004103 # miss rate for ReadReq accesses
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000812 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.001972 # miss rate for ReadReq accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.500000 # miss rate for UpgradeReq accesses
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003875 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.003875 # miss rate for ReadExReq accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004103 # miss rate for demand accesses
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.l2cache.demand_miss_rate::cpu.data 0.001253 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.002159 # miss rate for demand accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004103 # miss rate for overall accesses
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.l2cache.overall_miss_rate::cpu.data 0.001253 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.002159 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68573.750937 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72776.710403 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 69694.330085 # average ReadReq miss latency
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 23499 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 23499 # average UpgradeReq miss latency
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72026.605848 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72026.605848 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68573.750937 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72443.027055 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 70104.891291 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68573.750937 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72443.027055 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 70104.891291 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 704 # number of cycles access was blocked
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.l2cache.blocked::no_mshrs 2 # number of cycles access was blocked
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 352 # average number of cycles each access was blocked
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 33 # number of ReadReq MSHR hits
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 50 # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total 50 # number of ReadExReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 83 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 95 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 83 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 95 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2923 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1034 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 3957 # number of ReadReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 30254 # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total 30254 # number of HardPFReq MSHR misses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 805 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 805 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2923 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 1839 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 4762 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2923 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 1839 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 30254 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 35016 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 175790791 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 67094500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 242885291 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 178618011 # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 178618011 # number of HardPFReq MSHR miss cycles
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14001 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14001 # number of UpgradeReq MSHR miss cycles
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 52729252 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 52729252 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 175790791 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 119823752 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 295614543 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 175790791 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 119823752 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 178618011 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 474232554 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.004086 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000787 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001950 # mshr miss rate for ReadReq accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003648 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003648 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004086 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.001199 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.002117 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004086 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.001199 # mshr miss rate for overall accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.l2cache.overall_mshr_miss_rate::total 0.015565 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60140.537462 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64888.297872 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61381.170331 # average ReadReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 5903.946949 # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 5903.946949 # average HardPFReq mshr miss latency
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14001 # average UpgradeReq mshr miss latency
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65502.176398 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65502.176398 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60140.537462 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65157.015769 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62077.812474 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60140.537462 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65157.015769 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 5903.946949 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 13543.310315 # average overall mshr miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.toL2Bus.trans_dist::ReadReq 2029950 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 2029950 # Transaction distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.toL2Bus.trans_dist::Writeback 966341 # Transaction distribution
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.toL2Bus.trans_dist::HardPFReq 31609 # Transaction distribution
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.toL2Bus.trans_dist::ReadExReq 220643 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 220643 # Transaction distribution
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1431544 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4035081 # Packet count per connected master and slave (bytes)
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.toL2Bus.pkt_count::total 5466625 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45780416 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 160045376 # Cumulative packet size per connected master and slave (bytes)
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.toL2Bus.pkt_size::total 205825792 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 32515 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 3248545 # Request fanout histogram
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.toL2Bus.snoop_fanout::mean 1.009730 # Request fanout histogram
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.toL2Bus.snoop_fanout::stdev 0.098161 # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.toL2Bus.snoop_fanout::1 3216936 99.03% 99.03% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 31609 0.97% 100.00% # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.toL2Bus.snoop_fanout::total 3248545 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 2574809000 # Layer occupancy (ticks)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%)
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.toL2Bus.respLayer0.occupancy 1075177011 # Layer occupancy (ticks)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%)
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.toL2Bus.respLayer1.occupancy 2301798469 # Layer occupancy (ticks)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%)
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.membus.trans_dist::ReadReq 6500 # Transaction distribution
system.membus.trans_dist::ReadResp 6500 # Transaction distribution
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.trans_dist::UpgradeReq 1 # Transaction distribution
system.membus.trans_dist::UpgradeResp 1 # Transaction distribution
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.membus.trans_dist::ReadExReq 805 # Transaction distribution
system.membus.trans_dist::ReadExResp 805 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14612 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 14612 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 467520 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 467520 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.snoops 0 # Total snoops (count)
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.membus.snoop_fanout::samples 7306 # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.membus.snoop_fanout::0 7306 100.00% 100.00% # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.membus.snoop_fanout::total 7306 # Request fanout histogram
system.membus.reqLayer0.occupancy 9226230 # Layer occupancy (ticks)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.membus.respLayer1.occupancy 38266679 # Layer occupancy (ticks)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink