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gem5/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt

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ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
---------- Begin Simulation Statistics ----------
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
sim_seconds 0.058843 # Number of seconds simulated
sim_ticks 58842982000 # Number of ticks simulated
final_tick 58842982000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
host_inst_rate 157851 # Simulator instruction rate (inst/s)
host_op_rate 189517 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 34018873 # Simulator tick rate (ticks/s)
host_mem_usage 327492 # Number of bytes of host memory used
host_seconds 1729.72 # Real time elapsed on the host
sim_insts 273036656 # Number of instructions simulated
sim_ops 327810999 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.bytes_read::cpu.inst 189376 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 272128 # Number of bytes read from this memory
system.physmem.bytes_read::total 461504 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 189376 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 189376 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 2959 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 4252 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7211 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 3218328 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 4624647 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 7842974 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 3218328 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 3218328 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 3218328 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4624647 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 7842974 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 7211 # Number of read requests accepted
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writeReqs 0 # Number of write requests accepted
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.readBursts 7211 # Number of DRAM read bursts, including those serviced by the write queue
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.bytesReadDRAM 461504 # Total number of bytes read from DRAM
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.bytesReadSys 461504 # Total read bytes from the system interface side
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.neitherReadNorWriteReqs 11 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 592 # Per bank write bursts
system.physmem.perBankRdBursts::1 792 # Per bank write bursts
system.physmem.perBankRdBursts::2 603 # Per bank write bursts
system.physmem.perBankRdBursts::3 519 # Per bank write bursts
system.physmem.perBankRdBursts::4 437 # Per bank write bursts
system.physmem.perBankRdBursts::5 342 # Per bank write bursts
system.physmem.perBankRdBursts::6 159 # Per bank write bursts
system.physmem.perBankRdBursts::7 228 # Per bank write bursts
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.perBankRdBursts::8 208 # Per bank write bursts
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.perBankRdBursts::9 292 # Per bank write bursts
system.physmem.perBankRdBursts::10 317 # Per bank write bursts
system.physmem.perBankRdBursts::11 409 # Per bank write bursts
system.physmem.perBankRdBursts::12 526 # Per bank write bursts
system.physmem.perBankRdBursts::13 671 # Per bank write bursts
system.physmem.perBankRdBursts::14 612 # Per bank write bursts
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.perBankRdBursts::15 504 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.totGap 58842848000 # Total gap between requests
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.readPktSize::6 7211 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.rdQLenPdf::0 4240 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 2012 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 646 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 244 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 68 # What read queue length does an incoming req see
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.bytesPerActivate::samples 1405 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 327.288256 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 191.332764 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 342.731237 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 492 35.02% 35.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 350 24.91% 59.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 132 9.40% 69.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 82 5.84% 75.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 53 3.77% 78.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 47 3.35% 82.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 27 1.92% 84.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 22 1.57% 85.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 200 14.23% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1405 # Bytes accessed per row activation
system.physmem.totQLat 59614750 # Total ticks spent queuing
system.physmem.totMemAccLat 194821000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 36055000 # Total ticks spent in databus transfers
system.physmem.avgQLat 8267.20 # Average queueing delay per DRAM burst
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.avgMemAccLat 27017.20 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 7.84 # Average DRAM read bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.avgRdBWSys 7.84 # Average system read bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.busUtil 0.06 # Data bus utilization in percentage
system.physmem.busUtilRead 0.06 # Data bus utilization in percentage for reads
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.avgRdQLen 1.12 # Average read queue length when enqueuing
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.readRowHits 5798 # Number of row buffer hits during reads
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.readRowHitRate 80.40 # Row buffer hit rate for reads
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.avgGap 8160150.88 # Average gap between requests
system.physmem.pageHitRate 80.40 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 55121576750 # Time in different power states
system.physmem.memoryStateTime::REF 1964820000 # Time in different power states
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.memoryStateTime::ACT 1754568250 # Time in different power states
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.membus.throughput 7842974 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 4381 # Transaction distribution
system.membus.trans_dist::ReadResp 4381 # Transaction distribution
system.membus.trans_dist::UpgradeReq 11 # Transaction distribution
system.membus.trans_dist::UpgradeResp 11 # Transaction distribution
system.membus.trans_dist::ReadExReq 2830 # Transaction distribution
system.membus.trans_dist::ReadExResp 2830 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14444 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 14444 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 461504 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 461504 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 461504 # Total data (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.membus.reqLayer0.occupancy 8714000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.membus.respLayer1.occupancy 67059990 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.branchPred.lookups 36678579 # Number of BP lookups
system.cpu.branchPred.condPredicted 19369962 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1628976 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 19217639 # Number of BTB lookups
system.cpu.branchPred.BTBHits 17291098 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.branchPred.BTBHitPct 89.975142 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 7036393 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 5252 # Number of incorrect RAS predictions.
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 191 # Number of system calls
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.numCycles 117685965 # number of cpu cycles simulated
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.fetch.icacheStallCycles 40172132 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 329927106 # Number of instructions fetch has processed
system.cpu.fetch.Branches 36678579 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 24327491 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 75600101 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 3327960 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 175 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 2800 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 41 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 38768855 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 530996 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 117439229 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 3.389931 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.437439 # Number of instructions fetched each cycle (Total)
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.fetch.rateDist::0 46731814 39.79% 39.79% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 7329854 6.24% 46.03% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 6574514 5.60% 51.63% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 6398088 5.45% 57.08% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 4252484 3.62% 60.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 5520861 4.70% 65.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 3987559 3.40% 68.80% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 3254311 2.77% 71.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 33389744 28.43% 100.00% # Number of instructions fetched each cycle (Total)
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.fetch.rateDist::total 117439229 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.311665 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.803453 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 34271331 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 16148849 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 61039844 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 4384832 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1594373 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 7530126 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 70364 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 389722126 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 437543 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 1594373 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 37031203 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 5569218 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 387986 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 62601924 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 10254525 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 382340457 # Number of instructions processed by rename
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.rename.ROBFullEvents 36 # Number of times rename has blocked due to ROB full
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.rename.IQFullEvents 4583661 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 2043172 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 2989050 # Number of times rename has blocked due to SQ full
system.cpu.rename.FullRegisterEvents 65700 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 432935056 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 2729953830 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 376601971 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 209126886 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 372229219 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 60705837 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 14453 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 15060 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 19856485 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 96101144 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 93882304 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 9920575 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 10878783 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 370378331 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 25182 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 358744041 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 1234352 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 42331510 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 132428138 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 3062 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 117439229 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 3.054721 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 2.223263 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.iq.issued_per_cycle::0 21274018 18.11% 18.11% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 14280801 12.16% 30.28% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 14869023 12.66% 42.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 13830819 11.78% 54.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 20620243 17.56% 72.27% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 15076681 12.84% 85.11% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 10030176 8.54% 93.65% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 4472440 3.81% 97.46% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 2985028 2.54% 100.00% # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.iq.issued_per_cycle::total 117439229 # Number of insts issued each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.iq.fu_full::IntAlu 30566 0.13% 0.13% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 5035 0.02% 0.15% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.15% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.15% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.15% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.15% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 0.15% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.15% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.15% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.15% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.15% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.15% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.15% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.15% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.15% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 0.15% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.15% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 0.15% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.15% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.15% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 218902 0.91% 1.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 207576 0.86% 1.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 15328 0.06% 1.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 1824 0.01% 1.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 338916 1.41% 3.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 30886 0.13% 3.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 130712 0.54% 4.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.07% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 13684069 56.78% 60.84% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 9438097 39.16% 100.00% # attempts to use FU when none available
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.iq.FU_type_0::IntAlu 114997382 32.06% 32.06% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 2177572 0.61% 32.66% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.66% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.66% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.66% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.66% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.66% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.66% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 6789188 1.89% 34.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 8562613 2.39% 36.94% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 3491505 0.97% 37.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 1605361 0.45% 38.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 21185799 5.91% 44.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 7196318 2.01% 46.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 7147739 1.99% 48.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 183217 0.05% 48.32% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 95472748 26.61% 74.93% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 89934599 25.07% 100.00% # Type of FU issued
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.iq.FU_type_0::total 358744041 # Type of FU issued
system.cpu.iq.rate 3.048316 # Inst issue rate
system.cpu.iq.fu_busy_cnt 24101911 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.067184 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 600140343 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 274631052 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 231134438 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 260123231 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 138160310 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 119811956 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 246702850 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 136143102 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 13691987 # Number of loads that had data forwarded from stores
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 10368919 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 114059 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 68397 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 11506726 # Number of stores squashed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.iew.lsq.thread0.rescheduledLoads 1395971 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 850 # Number of times an access to memory failed due to the cache being blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.iew.iewSquashCycles 1594373 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 4558099 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 129859 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 370404619 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 1080086 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 96101144 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 93882304 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 14149 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 21825 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 109033 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 68397 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 1241378 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 435662 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1677040 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 354745077 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 94263609 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 3998964 # Number of squashed instructions skipped in execute
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.iew.exec_nop 1106 # number of nop insts executed
system.cpu.iew.exec_refs 182843438 # number of memory reference insts executed
system.cpu.iew.exec_branches 32405794 # Number of branches executed
system.cpu.iew.exec_stores 88579829 # Number of stores executed
system.cpu.iew.exec_rate 3.014336 # Inst execution rate
system.cpu.iew.wb_sent 352024494 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 350946394 # cumulative count of insts written-back
system.cpu.iew.wb_producers 175212964 # num instructions producing a value
system.cpu.iew.wb_consumers 355804607 # num instructions consuming a value
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.iew.wb_rate 2.982058 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.492442 # average fanout of values written-back
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.commit.commitSquashedInsts 42598489 # The number of squashed insts skipped by commit
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.commit.branchMispredicts 1559369 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 111323846 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 2.944667 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.904010 # Number of insts commited each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.commit.committed_per_cycle::0 29334492 26.35% 26.35% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 21002495 18.87% 45.22% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 12438899 11.17% 56.39% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 8843852 7.94% 64.33% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 8943359 8.03% 72.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 5286497 4.75% 77.12% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 3580965 3.22% 80.33% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 3438245 3.09% 83.42% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 18455042 16.58% 100.00% # Number of insts commited each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.commit.committed_per_cycle::total 111323846 # Number of insts commited each cycle
system.cpu.commit.committedInsts 273037268 # Number of instructions committed
system.cpu.commit.committedOps 327811611 # Number of ops (including micro ops) committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.commit.refs 168107803 # Number of memory references committed
system.cpu.commit.loads 85732225 # Number of loads committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.membars 11033 # Number of memory barriers committed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.commit.branches 30563485 # Number of branches committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions.
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.commit.int_insts 258331174 # Number of committed integer instructions.
ARM: Update stats for CBNZ fix.
2012-03-09 21:33:07 +01:00
system.cpu.commit.function_calls 6225112 # Number of function calls committed.
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.commit.op_class_0::IntAlu 104312045 31.82% 31.82% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 2145845 0.65% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 6594343 2.01% 34.49% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 34.49% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 7943502 2.42% 36.91% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 3118180 0.95% 37.86% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 1563217 0.48% 38.34% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 19652356 6.00% 44.33% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 7136937 2.18% 46.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 85732225 26.15% 74.87% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 82375578 25.13% 100.00% # Class of committed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.commit.op_class_0::total 327811611 # Class of committed instruction
system.cpu.commit.bw_lim_events 18455042 # number cycles where commit BW limit reached
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.rob.rob_reads 463276381 # The number of ROB reads
system.cpu.rob.rob_writes 746948197 # The number of ROB writes
system.cpu.timesIdled 5570 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 246736 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 273036656 # Number of Instructions Simulated
system.cpu.committedOps 327810999 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 0.431026 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.431026 # CPI: Total CPI of All Threads
system.cpu.ipc 2.320044 # IPC: Instructions Per Cycle
system.cpu.ipc_total 2.320044 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 344698387 # number of integer regfile reads
system.cpu.int_regfile_writes 141985623 # number of integer regfile writes
system.cpu.fp_regfile_reads 189510679 # number of floating regfile reads
system.cpu.fp_regfile_writes 134618624 # number of floating regfile writes
system.cpu.cc_regfile_reads 1340695625 # number of cc regfile reads
system.cpu.cc_regfile_writes 80827327 # number of cc regfile writes
system.cpu.misc_regfile_reads 1216328122 # number of misc regfile reads
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.toL2Bus.throughput 23209157 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 17471 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 17471 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 1022 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 12 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 12 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 2846 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 2846 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31432 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10234 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 41666 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1005376 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 359424 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total 1364800 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 1364800 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 896 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 11697999 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.toL2Bus.respLayer0.occupancy 24104992 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.toL2Bus.respLayer1.occupancy 7380470 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.tags.replacements 13841 # number of replacements
system.cpu.icache.tags.tagsinuse 1830.861112 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 38751311 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 15711 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 2466.508243 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.tags.occ_blocks::cpu.inst 1830.861112 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.893975 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.893975 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1870 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::2 194 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1522 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.913086 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 77553427 # Number of tag accesses
system.cpu.icache.tags.data_accesses 77553427 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 38751328 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 38751328 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 38751328 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 38751328 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 38751328 # number of overall hits
system.cpu.icache.overall_hits::total 38751328 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 17524 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 17524 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 17524 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 17524 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 17524 # number of overall misses
system.cpu.icache.overall_misses::total 17524 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 439561740 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 439561740 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 439561740 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 439561740 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 439561740 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 439561740 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 38768852 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 38768852 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 38768852 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 38768852 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 38768852 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 38768852 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000452 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000452 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000452 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000452 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000452 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000452 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25083.413604 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 25083.413604 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 25083.413604 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 25083.413604 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 25083.413604 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 25083.413604 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 684 # number of cycles access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 57 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1801 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 1801 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 1801 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 1801 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 1801 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 1801 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15723 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 15723 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 15723 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 15723 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 15723 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 15723 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 350218008 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 350218008 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 350218008 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 350218008 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 350218008 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 350218008 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000406 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000406 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000406 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000406 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000406 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000406 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22274.248426 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22274.248426 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22274.248426 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 22274.248426 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22274.248426 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 22274.248426 # average overall mshr miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.replacements 0 # number of replacements
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.tags.tagsinuse 3837.051468 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 13121 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 5294 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 2.478466 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.tags.occ_blocks::writebacks 357.151307 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2707.112582 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 772.787579 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.010899 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.082615 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.023584 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.117098 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 5294 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1246 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3911 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.161560 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 178837 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 178837 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 12742 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 286 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 13028 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 1022 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 1022 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 12742 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 302 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 13044 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 12742 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 302 # number of overall hits
system.cpu.l2cache.overall_hits::total 13044 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 2967 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 1462 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 4429 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 11 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 11 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 2830 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 2830 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 2967 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 4292 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 7259 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 2967 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 4292 # number of overall misses
system.cpu.l2cache.overall_misses::total 7259 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 207032250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 106837750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 313870000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 202417250 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 202417250 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 207032250 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 309255000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 516287250 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 207032250 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 309255000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 516287250 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 15709 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1748 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 17457 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 1022 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 1022 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 12 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 12 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 2846 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 2846 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 15709 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 4594 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 20303 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 15709 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 4594 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 20303 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.188873 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.836384 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.253709 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.916667 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.916667 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994378 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.994378 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.188873 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.934262 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.357533 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.188873 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.934262 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.357533 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69778.311426 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73076.436389 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 70867.012870 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71525.530035 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71525.530035 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69778.311426 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72053.821062 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 71123.742940 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69778.311426 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72053.821062 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 71123.742940 # average overall miss latency
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 40 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 48 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 40 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 48 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2959 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1422 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 4381 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 11 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 11 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2830 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 2830 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2959 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 4252 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 7211 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2959 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 4252 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 7211 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 169394250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 86707000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 256101250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 112009 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 112009 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 167488250 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 167488250 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 169394250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 254195250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 423589500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 169394250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 254195250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 423589500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.188363 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.813501 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.250960 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.916667 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.916667 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994378 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994378 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.188363 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.925555 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.355169 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.188363 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.925555 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.355169 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57247.127408 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60975.386779 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58457.258617 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10182.636364 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10182.636364 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59183.127208 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59183.127208 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57247.127408 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59782.514111 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58742.130079 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57247.127408 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59782.514111 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58742.130079 # average overall mshr miss latency
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.tags.replacements 1384 # number of replacements
system.cpu.dcache.tags.tagsinuse 3114.575432 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 161730326 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 4594 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 35204.685677 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.tags.occ_blocks::cpu.data 3114.575432 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.760394 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.760394 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 3210 # Occupied blocks per task id
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 686 # Occupied blocks per task id
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::4 2462 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.783691 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 323517792 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 323517792 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 79590771 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 79590771 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 82030417 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 82030417 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 87045 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 87045 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 11127 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 11127 # number of LoadLockedReq hits
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.demand_hits::cpu.data 161621188 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 161621188 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 161708233 # number of overall hits
system.cpu.dcache.overall_hits::total 161708233 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 4059 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 4059 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 22243 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 22243 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 40 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 40 # number of SoftPFReq misses
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.demand_misses::cpu.data 26302 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 26302 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 26342 # number of overall misses
system.cpu.dcache.overall_misses::total 26342 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 234715222 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 234715222 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1291834537 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 1291834537 # number of WriteReq miss cycles
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 170250 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 170250 # number of LoadLockedReq miss cycles
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.demand_miss_latency::cpu.data 1526549759 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 1526549759 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 1526549759 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 1526549759 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 79594830 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 79594830 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 82052660 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 82052660 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 87085 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 87085 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11129 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 11129 # number of LoadLockedReq accesses(hits+misses)
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.demand_accesses::cpu.data 161647490 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 161647490 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 161734575 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 161734575 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000051 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000051 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000271 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000271 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000459 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.000459 # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000180 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000180 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000163 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000163 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000163 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000163 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 57825.873861 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 57825.873861 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58078.251000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 58078.251000 # average WriteReq miss latency
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85125 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85125 # average LoadLockedReq miss latency
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.demand_avg_miss_latency::cpu.data 58039.303437 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 58039.303437 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 57951.171475 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 57951.171475 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 32404 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 1444 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 548 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 59.131387 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 103.142857 # average number of cycles each access was blocked
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.writebacks::writebacks 1022 # number of writebacks
system.cpu.dcache.writebacks::total 1022 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2332 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 2332 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19388 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 19388 # number of WriteReq MSHR hits
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.demand_mshr_hits::cpu.data 21720 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 21720 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 21720 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 21720 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1727 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2855 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 2855 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 24 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 24 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 4582 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 4582 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 4606 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 4606 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109924790 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 109924790 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 205574740 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 205574740 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1745000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1745000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 315499530 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 315499530 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 317244530 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 317244530 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000276 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000276 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000028 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000028 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63650.718008 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63650.718008 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72005.162872 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72005.162872 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 72708.333333 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 72708.333333 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68856.292012 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 68856.292012 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68876.363439 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 68876.363439 # average overall mshr miss latency
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink