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gem5/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt

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ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
---------- Begin Simulation Statistics ----------
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
sim_seconds 0.506591 # Number of seconds simulated
sim_ticks 506591420000 # Number of ticks simulated
final_tick 506591420000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
host_inst_rate 188296 # Simulator instruction rate (inst/s)
host_op_rate 202861 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 61758141 # Simulator tick rate (ticks/s)
host_mem_usage 254008 # Number of bytes of host memory used
host_seconds 8202.83 # Real time elapsed on the host
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
sim_insts 1544563023 # Number of instructions simulated
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
sim_ops 1664032415 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.bytes_read::cpu.inst 46336 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 143772736 # Number of bytes read from this memory
system.physmem.bytes_read::total 143819072 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 46336 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 46336 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 70460288 # Number of bytes written to this memory
system.physmem.bytes_written::total 70460288 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 724 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2246449 # Number of read requests responded to by this memory
system.physmem.num_reads::total 2247173 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1100942 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1100942 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 91466 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 283804128 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 283895594 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 91466 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 91466 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 139087014 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 139087014 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 139087014 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 91466 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 283804128 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 422982608 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 2247174 # Number of read requests accepted
system.physmem.writeReqs 1100942 # Number of write requests accepted
system.physmem.readBursts 2247174 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 1100942 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 143725504 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 93632 # Total number of bytes read from write queue
system.physmem.bytesWritten 70458432 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 143819136 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 70460288 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 1463 # Number of DRAM read bursts serviced by the write queue
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.perBankRdBursts::0 139870 # Per bank write bursts
system.physmem.perBankRdBursts::1 136313 # Per bank write bursts
system.physmem.perBankRdBursts::2 133717 # Per bank write bursts
system.physmem.perBankRdBursts::3 136218 # Per bank write bursts
system.physmem.perBankRdBursts::4 134833 # Per bank write bursts
system.physmem.perBankRdBursts::5 135331 # Per bank write bursts
system.physmem.perBankRdBursts::6 136159 # Per bank write bursts
system.physmem.perBankRdBursts::7 136113 # Per bank write bursts
system.physmem.perBankRdBursts::8 143820 # Per bank write bursts
system.physmem.perBankRdBursts::9 146459 # Per bank write bursts
system.physmem.perBankRdBursts::10 144333 # Per bank write bursts
system.physmem.perBankRdBursts::11 146068 # Per bank write bursts
system.physmem.perBankRdBursts::12 145787 # Per bank write bursts
system.physmem.perBankRdBursts::13 145950 # Per bank write bursts
system.physmem.perBankRdBursts::14 142167 # Per bank write bursts
system.physmem.perBankRdBursts::15 142573 # Per bank write bursts
system.physmem.perBankWrBursts::0 69256 # Per bank write bursts
system.physmem.perBankWrBursts::1 67490 # Per bank write bursts
system.physmem.perBankWrBursts::2 65701 # Per bank write bursts
system.physmem.perBankWrBursts::3 66292 # Per bank write bursts
system.physmem.perBankWrBursts::4 66182 # Per bank write bursts
system.physmem.perBankWrBursts::5 66456 # Per bank write bursts
system.physmem.perBankWrBursts::6 67905 # Per bank write bursts
system.physmem.perBankWrBursts::7 68814 # Per bank write bursts
system.physmem.perBankWrBursts::8 70409 # Per bank write bursts
system.physmem.perBankWrBursts::9 70980 # Per bank write bursts
system.physmem.perBankWrBursts::10 70565 # Per bank write bursts
system.physmem.perBankWrBursts::11 70894 # Per bank write bursts
system.physmem.perBankWrBursts::12 70329 # Per bank write bursts
system.physmem.perBankWrBursts::13 70807 # Per bank write bursts
system.physmem.perBankWrBursts::14 69706 # Per bank write bursts
system.physmem.perBankWrBursts::15 69127 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.totGap 506591366500 # Total gap between requests
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.readPktSize::6 2247174 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.writePktSize::6 1100942 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 1574104 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 476401 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 148213 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 46974 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.wrQLenPdf::15 22580 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 24088 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 48460 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 60043 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 65003 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 66811 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 67201 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 67231 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 67460 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 67663 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 67777 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 68170 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 69182 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 70669 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 67984 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 68233 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 66514 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 65455 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 246 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 63 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 18 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.bytesPerActivate::samples 2025013 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 105.768407 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 82.613194 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 129.925028 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 1567130 77.39% 77.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 318117 15.71% 93.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 66732 3.30% 96.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 23886 1.18% 97.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 14001 0.69% 98.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 6496 0.32% 98.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 4833 0.24% 98.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 3896 0.19% 99.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 19922 0.98% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 2025013 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 65320 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 34.335441 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 154.678788 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 65282 99.94% 99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 11 0.02% 99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-3071 14 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.99% # Reads before turning the bus around for writes
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.rdPerTurnAround::total 65320 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 65320 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 16.854149 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.813582 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 1.224401 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-17 41990 64.28% 64.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18-19 22168 33.94% 98.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-21 1073 1.64% 99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22-23 57 0.09% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-25 8 0.01% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26-27 3 0.00% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-29 2 0.00% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30-31 14 0.02% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-33 2 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::34-35 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-45 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-85 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 65320 # Writes before turning the bus around for reads
system.physmem.totQLat 50678676000 # Total ticks spent queuing
system.physmem.totMemAccLat 92785757250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 11228555000 # Total ticks spent in databus transfers
system.physmem.avgQLat 22566.87 # Average queueing delay per DRAM burst
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.avgMemAccLat 41316.87 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 283.71 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 139.08 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 283.90 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 139.09 # Average system write bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.busUtil 3.30 # Data bus utilization in percentage
system.physmem.busUtilRead 2.22 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 1.09 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.19 # Average read queue length when enqueuing
system.physmem.avgWrQLen 25.41 # Average write queue length when enqueuing
system.physmem.readRowHits 906473 # Number of row buffer hits during reads
system.physmem.writeRowHits 415128 # Number of row buffer hits during writes
system.physmem.readRowHitRate 40.36 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 37.71 # Row buffer hit rate for writes
system.physmem.avgGap 151306.40 # Average gap between requests
system.physmem.pageHitRate 39.49 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 89126966500 # Time in different power states
system.physmem.memoryStateTime::REF 16916120000 # Time in different power states
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.memoryStateTime::ACT 400546526000 # Time in different power states
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.membus.throughput 422982608 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 1419539 # Transaction distribution
system.membus.trans_dist::ReadResp 1419538 # Transaction distribution
system.membus.trans_dist::Writeback 1100942 # Transaction distribution
system.membus.trans_dist::ReadExReq 827635 # Transaction distribution
system.membus.trans_dist::ReadExResp 827635 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5595289 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 5595289 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 214279360 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 214279360 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 214279360 # Total data (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.membus.reqLayer0.occupancy 12858312000 # Layer occupancy (ticks)
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.membus.reqLayer0.utilization 2.5 # Layer utilization (%)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.membus.respLayer1.occupancy 21011522750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 4.1 # Layer utilization (%)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.branchPred.lookups 322479068 # Number of BP lookups
system.cpu.branchPred.condPredicted 251697336 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 15342173 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 182789015 # Number of BTB lookups
system.cpu.branchPred.BTBHits 169211218 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.branchPred.BTBHitPct 92.571875 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 19180311 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 62 # Number of incorrect RAS predictions.
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.numCycles 1013182841 # number of cpu cycles simulated
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.fetch.icacheStallCycles 309137299 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 2319640214 # Number of instructions fetch has processed
system.cpu.fetch.Branches 322479068 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 188391529 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 688452374 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 31084694 # Number of cycles fetch has spent squashing
system.cpu.fetch.CacheLines 300792002 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 5498702 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 1013132020 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.455758 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.154346 # Number of instructions fetched each cycle (Total)
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.fetch.rateDist::0 555222202 54.80% 54.80% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 28050197 2.77% 57.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 43308558 4.27% 61.85% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 56959165 5.62% 67.47% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 42292761 4.17% 71.64% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 51207543 5.05% 76.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 41019007 4.05% 80.75% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 29441196 2.91% 83.65% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 165631391 16.35% 100.00% # Number of instructions fetched each cycle (Total)
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.fetch.rateDist::total 1013132020 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.318283 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.289459 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 248682792 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 345622952 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 359459924 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 43824601 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 15541751 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 49856372 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 610 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 2395697302 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 2189 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 15541751 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 269479595 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 192381996 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 17471 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 380094168 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 155617039 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 2338847400 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 939227 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 43524152 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 85831703 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 28336004 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 2341659219 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 10827293229 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 2896191361 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 924 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 666760274 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 297 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 295 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 177584133 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 623787680 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 234474986 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 103326529 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 119861826 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 2235979798 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 279 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 2042453270 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 1123672 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 568282292 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 1410742018 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 109 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1013132020 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.015979 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 2.060962 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.iq.issued_per_cycle::0 369509753 36.47% 36.47% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 122144381 12.06% 48.53% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 148105848 14.62% 63.15% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 116397380 11.49% 74.64% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 120158766 11.86% 86.50% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 67734855 6.69% 93.18% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 38716090 3.82% 97.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 19620402 1.94% 98.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 10744545 1.06% 100.00% # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.iq.issued_per_cycle::total 1013132020 # Number of insts issued each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.iq.fu_full::IntAlu 3650692 18.70% 18.70% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 890 0.00% 18.71% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 18.71% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.71% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.71% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.71% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 18.71% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.71% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 18.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 18.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.71% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 15434151 79.07% 97.77% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 434530 2.23% 100.00% # attempts to use FU when none available
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.iq.FU_type_0::IntAlu 1227555044 60.10% 60.10% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 999501 0.05% 60.15% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.15% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.15% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.15% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.15% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.15% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.15% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 75 0.00% 60.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 3 0.00% 60.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 36 0.00% 60.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 18 0.00% 60.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.15% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 618802083 30.30% 90.45% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 195096510 9.55% 100.00% # Type of FU issued
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.iq.FU_type_0::total 2042453270 # Type of FU issued
system.cpu.iq.rate 2.015878 # Inst issue rate
system.cpu.iq.fu_busy_cnt 19520263 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.009557 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 5118681932 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 2804481694 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1937195401 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 563 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 772 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 222 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 2061973250 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 283 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 29620868 # Number of loads that had data forwarded from stores
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 165481346 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 152761 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 223174 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 59627941 # Number of stores squashed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.iew.lsq.thread0.rescheduledLoads 27365932 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 20554693 # Number of times an access to memory failed due to the cache being blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.iew.iewSquashCycles 15541751 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 99594513 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 79709192 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 2235980127 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 3715851 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 623787680 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 234474986 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 217 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 887425 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 78519079 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 223174 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 8257753 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 10408115 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 18665868 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 2014561503 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 604829298 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 27891767 # Number of squashed instructions skipped in execute
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.iew.exec_nop 50 # number of nop insts executed
system.cpu.iew.exec_refs 796810326 # number of memory reference insts executed
system.cpu.iew.exec_branches 245407289 # Number of branches executed
system.cpu.iew.exec_stores 191981028 # Number of stores executed
system.cpu.iew.exec_rate 1.988349 # Inst execution rate
system.cpu.iew.wb_sent 1947397166 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1937195623 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1312629106 # num instructions producing a value
system.cpu.iew.wb_consumers 2061058840 # num instructions consuming a value
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.iew.wb_rate 1.911990 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.636871 # average fanout of values written-back
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.commit.commitSquashedInsts 572342091 # The number of squashed insts skipped by commit
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.commit.branchMispredicts 15341577 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 933174586 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.783195 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.675212 # Number of insts commited each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.commit.committed_per_cycle::0 468896979 50.25% 50.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 178641910 19.14% 69.39% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 68227019 7.31% 76.70% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 32102473 3.44% 80.14% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 24397966 2.61% 82.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 27603302 2.96% 85.71% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 17322198 1.86% 87.57% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 14774408 1.58% 89.15% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 101208331 10.85% 100.00% # Number of insts commited each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.commit.committed_per_cycle::total 933174586 # Number of insts commited each cycle
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.commit.committedInsts 1544563041 # Number of instructions committed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.commit.committedOps 1664032433 # Number of ops (including micro ops) committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.commit.refs 633153379 # Number of memory references committed
system.cpu.commit.loads 458306334 # Number of loads committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.membars 62 # Number of memory barriers committed
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.commit.branches 213462426 # Number of branches committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.commit.int_insts 1477900421 # Number of committed integer instructions.
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.function_calls 13665177 # Number of function calls committed.
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.commit.op_class_0::IntAlu 1030178729 61.91% 61.91% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 458306334 27.54% 89.49% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Class of committed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.commit.op_class_0::total 1664032433 # Class of committed instruction
system.cpu.commit.bw_lim_events 101208331 # number cycles where commit BW limit reached
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.rob.rob_reads 3068340180 # The number of ROB reads
system.cpu.rob.rob_writes 4552875899 # The number of ROB writes
system.cpu.timesIdled 556 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 50821 # Total number of cycles that the CPU has spent unscheduled due to idling
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.committedInsts 1544563023 # Number of Instructions Simulated
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.committedOps 1664032415 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 0.655967 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.655967 # CPI: Total CPI of All Threads
system.cpu.ipc 1.524466 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.524466 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 2376547647 # number of integer regfile reads
system.cpu.int_regfile_writes 1366493054 # number of integer regfile writes
system.cpu.fp_regfile_reads 209 # number of floating regfile reads
system.cpu.fp_regfile_writes 233 # number of floating regfile writes
system.cpu.cc_regfile_reads 7643535318 # number of cc regfile reads
system.cpu.cc_regfile_writes 583887345 # number of cc regfile writes
system.cpu.misc_regfile_reads 725285725 # number of misc regfile reads
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.misc_regfile_writes 124 # number of misc regfile writes
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.toL2Bus.throughput 1691907313 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 7714547 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 7714546 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 3783532 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1894199 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1894199 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1502 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22999521 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 23001023 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 48064 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 857057664 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total 857105728 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 857105728 # Total data (bytes)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.toL2Bus.reqLayer0.occupancy 10479902270 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1252249 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.toL2Bus.respLayer1.occupancy 14758141993 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 2.9 # Layer utilization (%)
system.cpu.icache.tags.replacements 15 # number of replacements
system.cpu.icache.tags.tagsinuse 614.894819 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 300790815 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 751 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 400520.392810 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.tags.occ_blocks::cpu.inst 614.894819 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.300242 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.300242 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 736 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 709 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.359375 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 601584755 # Number of tag accesses
system.cpu.icache.tags.data_accesses 601584755 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 300790815 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 300790815 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 300790815 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 300790815 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 300790815 # number of overall hits
system.cpu.icache.overall_hits::total 300790815 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1187 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1187 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1187 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1187 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1187 # number of overall misses
system.cpu.icache.overall_misses::total 1187 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 83295499 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 83295499 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 83295499 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 83295499 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 83295499 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 83295499 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 300792002 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 300792002 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 300792002 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 300792002 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 300792002 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 300792002 # number of overall (read+write) accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70173.124684 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 70173.124684 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 70173.124684 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 70173.124684 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 70173.124684 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 70173.124684 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 65 # number of cycles access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 65 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 436 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 436 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 436 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 436 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 436 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 436 # number of overall MSHR hits
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 751 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 751 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 751 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 751 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 751 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 751 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54758751 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 54758751 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54758751 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 54758751 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54758751 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 54758751 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72914.448735 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72914.448735 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72914.448735 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 72914.448735 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72914.448735 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 72914.448735 # average overall mshr miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.tags.replacements 2214491 # number of replacements
system.cpu.l2cache.tags.tagsinuse 31511.693387 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 9253081 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 2244265 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 4.122989 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 21056926750 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 14239.275305 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 20.394558 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 17252.023525 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.434548 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000622 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.526490 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.961661 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29774 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 81 # Occupied blocks per task id
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1811 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 23310 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4479 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908630 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 111276688 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 111276688 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 26 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 6294974 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 6295000 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 3783532 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 3783532 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 1066564 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 1066564 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 26 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 7361538 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 7361564 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 26 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 7361538 # number of overall hits
system.cpu.l2cache.overall_hits::total 7361564 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 725 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 1418822 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 1419547 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 827635 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 827635 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 725 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 2246457 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 2247182 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 725 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 2246457 # number of overall misses
system.cpu.l2cache.overall_misses::total 2247182 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 53741250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 119467300250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 119521041500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 71195256250 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 71195256250 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 53741250 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 190662556500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 190716297750 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 53741250 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 190662556500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 190716297750 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 751 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 7713796 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 7714547 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 3783532 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 3783532 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1894199 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1894199 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 751 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 9607995 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 9608746 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 751 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 9607995 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 9608746 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.965379 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.183933 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.184009 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436931 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.436931 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965379 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.233811 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.233868 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965379 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.233811 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.233868 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74125.862069 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84201.753462 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 84196.607439 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 86022.529557 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 86022.529557 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74125.862069 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84872.559991 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 84869.092824 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74125.862069 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84872.559991 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 84869.092824 # average overall miss latency
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.writebacks::writebacks 1100942 # number of writebacks
system.cpu.l2cache.writebacks::total 1100942 # number of writebacks
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.demand_mshr_hits::cpu.data 7 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 724 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1418815 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 1419539 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 827635 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 827635 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 724 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 2246450 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 2247174 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 724 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2246450 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 2247174 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 44565250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 101708549750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 101753115000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60858432750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60858432750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44565250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 162566982500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 162611547750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44565250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 162566982500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 162611547750 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964048 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.183932 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184008 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436931 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436931 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964048 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233810 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.233868 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964048 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233810 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.233868 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61554.212707 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71685.561366 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71680.394128 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73532.937527 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73532.937527 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61554.212707 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72366.169957 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72362.686534 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61554.212707 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72366.169957 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72362.686534 # average overall mshr miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.tags.replacements 9603898 # number of replacements
system.cpu.dcache.tags.tagsinuse 4087.677378 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 678741158 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 9607994 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 70.643379 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 3511642250 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4087.677378 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.997968 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.997968 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 657 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 2421 # Occupied blocks per task id
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::2 1017 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.tags.tag_accesses 1403558154 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1403558154 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 511838800 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 511838800 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 166902232 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 166902232 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 2 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 2 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 63 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 63 # number of LoadLockedReq hits
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.demand_hits::cpu.data 678741032 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 678741032 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 678741034 # number of overall hits
system.cpu.dcache.overall_hits::total 678741034 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 12550102 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 12550102 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 5683815 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 5683815 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.demand_misses::cpu.data 18233917 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 18233917 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 18233919 # number of overall misses
system.cpu.dcache.overall_misses::total 18233919 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 378927155489 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 378927155489 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 307221007401 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 307221007401 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 228000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 686148162890 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 686148162890 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 686148162890 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 686148162890 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 524388902 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 524388902 # number of ReadReq accesses(hits+misses)
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.SoftPFReq_accesses::cpu.data 4 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 4 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 66 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 66 # number of LoadLockedReq accesses(hits+misses)
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.demand_accesses::cpu.data 696974949 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 696974949 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 696974953 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 696974953 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023933 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.023933 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032933 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.032933 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.500000 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.500000 # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045455 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045455 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.026162 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.026162 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.026162 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.026162 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30193.153449 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 30193.153449 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54051.901302 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 54051.901302 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 76000 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 76000 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 37630.321718 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 37630.321718 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 37630.317591 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 37630.317591 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 28822616 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 4626055 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 1847693 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 65151 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.599245 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 71.005127 # average number of cycles each access was blocked
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.writebacks::writebacks 3783532 # number of writebacks
system.cpu.dcache.writebacks::total 3783532 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4836306 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 4836306 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3789617 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 3789617 # number of WriteReq MSHR hits
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.demand_mshr_hits::cpu.data 8625923 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 8625923 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 8625923 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 8625923 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7713796 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 7713796 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1894198 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1894198 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 9607994 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 9607994 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 9607995 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 9607995 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 192253948507 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 192253948507 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84881076130 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 84881076130 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 69500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 69500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 277135024637 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 277135024637 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 277135094137 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 277135094137 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.014710 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.014710 # mshr miss rate for ReadReq accesses
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010975 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010975 # mshr miss rate for WriteReq accesses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.013785 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.013785 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.013785 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.013785 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24923.390314 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24923.390314 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44811.089511 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44811.089511 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 69500 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 69500 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28844.212917 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 28844.212917 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28844.217148 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 28844.217148 # average overall mshr miss latency
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink