2010-07-27 07:03:44 +02:00
---------- Begin Simulation Statistics ----------
2016-03-17 18:30:58 +01:00
sim_seconds 0.517287 # Number of seconds simulated
sim_ticks 517287152500 # Number of ticks simulated
final_tick 517287152500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2012-01-25 18:19:50 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
2016-03-17 18:30:58 +01:00
host_inst_rate 131506 # Simulator instruction rate (inst/s)
host_op_rate 157879 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 249419657 # Simulator tick rate (ticks/s)
host_mem_usage 307088 # Number of bytes of host memory used
host_seconds 2073.96 # Real time elapsed on the host
sim_insts 272737951 # Number of instructions simulated
sim_ops 327435116 # Number of ops (including micro ops) simulated
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2016-03-17 18:30:58 +01:00
system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 269696 # Number of bytes read from this memory
system.physmem.bytes_read::total 436672 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 166976 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 166976 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 2609 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 4214 # Number of read requests responded to by this memory
system.physmem.num_reads::total 6823 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 322792 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 521366 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 844158 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 322792 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 322792 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 322792 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 521366 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 844158 # Total bandwidth to/from this memory (bytes/s)
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2014-12-23 15:31:20 +01:00
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2010-11-08 20:59:35 +01:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
2010-07-27 07:03:44 +02:00
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
2012-01-25 18:19:50 +01:00
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2012-01-25 18:19:50 +01:00
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 191 # Number of system calls
2016-03-17 18:30:58 +01:00
system.cpu.numCycles 1034574305 # number of cpu cycles simulated
2012-01-25 18:19:50 +01:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
2016-03-17 18:30:58 +01:00
system.cpu.committedInsts 272737951 # Number of instructions committed
system.cpu.committedOps 327435116 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 258332236 # Number of integer alu accesses
2012-01-25 18:19:50 +01:00
system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses
2016-03-17 18:30:58 +01:00
system.cpu.num_func_calls 12449970 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 15800021 # number of instructions that are conditional controls
system.cpu.num_int_insts 258332236 # number of integer instructions
2012-01-25 18:19:50 +01:00
system.cpu.num_fp_insts 114216705 # number of float instructions
2016-03-17 18:30:58 +01:00
system.cpu.num_int_register_reads 1215886434 # number of times the integer registers were read
system.cpu.num_int_register_writes 162499715 # number of times the integer registers were written
2012-01-25 18:19:50 +01:00
system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read
system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written
2016-03-17 18:30:58 +01:00
system.cpu.num_cc_register_reads 1242911540 # number of times the CC registers were read
system.cpu.num_cc_register_writes 76355719 # number of times the CC registers were written
system.cpu.num_mem_refs 168105830 # number of memory refs
system.cpu.num_load_insts 85730232 # Number of load instructions
system.cpu.num_store_insts 82375598 # Number of store instructions
2014-10-20 23:48:19 +02:00
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
2016-03-17 18:30:58 +01:00
system.cpu.num_busy_cycles 1034574304.998000 # Number of busy cycles
2014-10-20 23:48:19 +02:00
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
2016-03-17 18:30:58 +01:00
system.cpu.Branches 30566209 # Number of branches fetched
2014-05-10 00:58:50 +02:00
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
2016-03-17 18:30:58 +01:00
system.cpu.op_class::IntAlu 104315933 31.82% 31.82% # Class of executed instruction
2014-09-03 13:42:59 +02:00
system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 6594343 2.01% 34.49% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 34.49% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34% # Class of executed instruction
2016-03-17 18:30:58 +01:00
system.cpu.op_class::SimdFloatMisc 19652356 5.99% 44.33% # Class of executed instruction
2014-09-03 13:42:59 +02:00
system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction
2016-03-17 18:30:58 +01:00
system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.67% # Class of executed instruction
2014-09-03 13:42:59 +02:00
system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction
2016-03-17 18:30:58 +01:00
system.cpu.op_class::MemRead 85730232 26.15% 74.87% # Class of executed instruction
system.cpu.op_class::MemWrite 82375598 25.13% 100.00% # Class of executed instruction
2014-05-10 00:58:50 +02:00
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
2016-03-17 18:30:58 +01:00
system.cpu.op_class::total 327813586 # Class of executed instruction
system.cpu.dcache.tags.replacements 1326 # number of replacements
system.cpu.dcache.tags.tagsinuse 3078.339297 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 168357609 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 4469 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 37672.322443 # Average number of references to valid blocks.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-03-17 18:30:58 +01:00
system.cpu.dcache.tags.occ_blocks::cpu.data 3078.339297 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.751548 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.751548 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 3143 # Occupied blocks per task id
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
2016-03-17 18:30:58 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 678 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 2434 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.767334 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 336728627 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 336728627 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 86231946 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 86231946 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 82049814 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 82049814 # number of WriteReq hits
2014-12-23 15:31:20 +01:00
system.cpu.dcache.SoftPFReq_hits::cpu.data 54059 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 54059 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
2016-03-17 18:30:58 +01:00
system.cpu.dcache.demand_hits::cpu.data 168281760 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 168281760 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 168335819 # number of overall hits
system.cpu.dcache.overall_hits::total 168335819 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1605 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1605 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 2862 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2862 # number of WriteReq misses
2014-12-23 15:31:20 +01:00
system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses
2016-03-17 18:30:58 +01:00
system.cpu.dcache.demand_misses::cpu.data 4467 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 4467 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 4470 # number of overall misses
system.cpu.dcache.overall_misses::total 4470 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 88066000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 88066000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 176802500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 176802500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 264868500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 264868500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 264868500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 264868500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 86233551 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 86233551 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 82052676 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 82052676 # number of WriteReq accesses(hits+misses)
2014-12-23 15:31:20 +01:00
system.cpu.dcache.SoftPFReq_accesses::cpu.data 54062 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 54062 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
2016-03-17 18:30:58 +01:00
system.cpu.dcache.demand_accesses::cpu.data 168286227 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 168286227 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 168340289 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 168340289 # number of overall (read+write) accesses
2014-12-23 15:31:20 +01:00
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000035 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000055 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.000055 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000027 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses
2016-03-17 18:30:58 +01:00
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54869.781931 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 54869.781931 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61775.856045 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 61775.856045 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 59294.492948 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 59294.492948 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 59254.697987 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 59254.697987 # average overall miss latency
2014-12-23 15:31:20 +01:00
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
2016-03-17 18:30:58 +01:00
system.cpu.dcache.writebacks::writebacks 997 # number of writebacks
system.cpu.dcache.writebacks::total 997 # number of writebacks
2014-12-23 15:31:20 +01:00
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits
2016-03-17 18:30:58 +01:00
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1604 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1604 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2862 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 2862 # number of WriteReq MSHR misses
2014-12-23 15:31:20 +01:00
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses
2016-03-17 18:30:58 +01:00
system.cpu.dcache.demand_mshr_misses::cpu.data 4466 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 4466 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 4469 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 4469 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86415000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 86415000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 173940500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 173940500 # number of WriteReq MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 183000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 183000 # number of SoftPFReq MSHR miss cycles
2016-03-17 18:30:58 +01:00
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260355500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 260355500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 260538500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 260538500 # number of overall MSHR miss cycles
2014-12-23 15:31:20 +01:00
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000055 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000055 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
2016-03-17 18:30:58 +01:00
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53874.688279 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53874.688279 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60775.856045 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60775.856045 # average WriteReq mshr miss latency
2015-11-06 09:26:50 +01:00
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency
2016-03-17 18:30:58 +01:00
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58297.245858 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 58297.245858 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58299.060192 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 58299.060192 # average overall mshr miss latency
2014-12-23 15:31:20 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2016-03-17 18:30:58 +01:00
system.cpu.icache.tags.replacements 13798 # number of replacements
system.cpu.icache.tags.tagsinuse 1765.947853 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 348643415 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 15605 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 22341.776033 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-03-17 18:30:58 +01:00
system.cpu.icache.tags.occ_blocks::cpu.inst 1765.947853 # Average occupied blocks per requestor
2015-11-06 09:26:50 +01:00
system.cpu.icache.tags.occ_percent::cpu.inst 0.862279 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.862279 # Average percentage of cache occupancy
2014-01-24 22:29:33 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
2016-03-17 18:30:58 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::3 163 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1522 # Occupied blocks per task id
2014-01-24 22:29:33 +01:00
system.cpu.icache.tags.occ_task_id_percent::1024 0.882324 # Percentage of cache occupancy per task id
2016-03-17 18:30:58 +01:00
system.cpu.icache.tags.tag_accesses 697333645 # Number of tag accesses
system.cpu.icache.tags.data_accesses 697333645 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 348643415 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 348643415 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 348643415 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 348643415 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 348643415 # number of overall hits
system.cpu.icache.overall_hits::total 348643415 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 15605 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 15605 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 15605 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 15605 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 15605 # number of overall misses
system.cpu.icache.overall_misses::total 15605 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 338522000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 338522000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 338522000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 338522000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 338522000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 338522000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 348659020 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 348659020 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 348659020 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 348659020 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 348659020 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 348659020 # number of overall (read+write) accesses
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses
2012-06-05 07:23:16 +02:00
system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses
2012-02-12 23:07:43 +01:00
system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses
2012-06-05 07:23:16 +02:00
system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses
2012-02-12 23:07:43 +01:00
system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses
2012-06-05 07:23:16 +02:00
system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses
2016-03-17 18:30:58 +01:00
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21693.175264 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 21693.175264 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 21693.175264 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 21693.175264 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 21693.175264 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 21693.175264 # average overall miss latency
2010-07-27 07:03:44 +02:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2012-01-25 18:19:50 +01:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
2010-07-27 07:03:44 +02:00
system.cpu.icache.cache_copies 0 # number of cache copies performed
2016-03-17 18:30:58 +01:00
system.cpu.icache.writebacks::writebacks 13798 # number of writebacks
system.cpu.icache.writebacks::total 13798 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15605 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 15605 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 15605 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 15605 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 15605 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 15605 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 322917000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 322917000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 322917000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 322917000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 322917000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 322917000 # number of overall MSHR miss cycles
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses
2012-06-05 07:23:16 +02:00
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses
2012-02-12 23:07:43 +01:00
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses
2012-06-05 07:23:16 +02:00
system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses
2012-02-12 23:07:43 +01:00
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses
2012-06-05 07:23:16 +02:00
system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses
2016-03-17 18:30:58 +01:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20693.175264 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20693.175264 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20693.175264 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 20693.175264 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20693.175264 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 20693.175264 # average overall mshr miss latency
2012-01-25 18:19:50 +01:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.replacements 0 # number of replacements
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.tags.tagsinuse 3487.616981 # Cycle average of tags in use
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.tags.total_refs 19775 # Total number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.tags.avg_refs 4.050594 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.tags.occ_blocks::writebacks 341.600605 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.332701 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 738.683674 # Average occupied blocks per requestor
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073466 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.022543 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.106434 # Average percentage of cache occupancy
2014-01-24 22:29:33 +01:00
system.cpu.l2cache.tags.occ_task_id_blocks::1024 4882 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1233 # Occupied blocks per task id
2014-01-24 22:29:33 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3543 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148987 # Percentage of cache occupancy per task id
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.tags.tag_accesses 228016 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 228016 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 997 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 997 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 6213 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 6213 # number of WritebackClean hits
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12996 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 12996 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 239 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 239 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 12996 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 255 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 13251 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 12996 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 255 # number of overall hits
system.cpu.l2cache.overall_hits::total 13251 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 2846 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 2846 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2609 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 2609 # number of ReadCleanReq misses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1368 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 1368 # number of ReadSharedReq misses
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.demand_misses::cpu.inst 2609 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 4214 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 6823 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 2609 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 4214 # number of overall misses
system.cpu.l2cache.overall_misses::total 6823 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 169475500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 169475500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 155351500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 155351500 # number of ReadCleanReq miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 81591000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 81591000 # number of ReadSharedReq miss cycles
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.demand_miss_latency::cpu.inst 155351500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 251066500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 406418000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 155351500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 251066500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 406418000 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 997 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 997 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 6213 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 6213 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 2862 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 2862 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15605 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 15605 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1607 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 1607 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 15605 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 4469 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 20074 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 15605 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 4469 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 20074 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994410 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.994410 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.167190 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.167190 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.851276 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.851276 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167190 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.942940 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.339892 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167190 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.942940 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.339892 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59548.664793 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59548.664793 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59544.461479 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59544.461479 # average ReadCleanReq miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59642.543860 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59642.543860 # average ReadSharedReq miss latency
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59544.461479 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59579.140959 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 59565.880111 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59544.461479 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59579.140959 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 59565.880111 # average overall miss latency
2010-07-27 07:03:44 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2012-05-09 20:52:14 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2012-01-25 18:19:50 +01:00
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
2010-07-27 07:03:44 +02:00
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2846 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 2846 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2609 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2609 # number of ReadCleanReq MSHR misses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1368 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1368 # number of ReadSharedReq MSHR misses
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2609 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 4214 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 6823 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2609 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 4214 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 6823 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 141015500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 141015500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 129261500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 129261500 # number of ReadCleanReq MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 67911000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 67911000 # number of ReadSharedReq MSHR miss cycles
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129261500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 208926500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 338188000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129261500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 208926500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 338188000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994410 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994410 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.167190 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.167190 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.851276 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.851276 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167190 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.942940 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.339892 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167190 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.942940 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.339892 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49548.664793 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49548.664793 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49544.461479 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49544.461479 # average ReadCleanReq mshr miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49642.543860 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49642.543860 # average ReadSharedReq mshr miss latency
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49544.461479 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49579.140959 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49565.880111 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49544.461479 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49579.140959 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49565.880111 # average overall mshr miss latency
2012-01-25 18:19:50 +01:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2016-03-17 18:30:58 +01:00
system.cpu.toL2Bus.snoop_filter.tot_requests 35198 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 15220 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7664 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-03-17 18:30:58 +01:00
system.cpu.toL2Bus.trans_dist::ReadResp 17212 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 997 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 13798 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 329 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 2862 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 2862 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 15605 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1607 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45008 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10264 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 55272 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1881792 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 349824 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 2231616 # Cumulative packet size per connected master and slave (bytes)
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
2016-03-17 18:30:58 +01:00
system.cpu.toL2Bus.snoop_fanout::samples 20074 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.386570 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.486976 # Request fanout histogram
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-03-17 18:30:58 +01:00
system.cpu.toL2Bus.snoop_fanout::0 12314 61.34% 61.34% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 7760 38.66% 100.00% # Request fanout histogram
2015-05-05 09:22:39 +02:00
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2015-05-05 09:22:39 +02:00
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
2016-03-17 18:30:58 +01:00
system.cpu.toL2Bus.snoop_fanout::total 20074 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 32394000 # Layer occupancy (ticks)
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
2016-03-17 18:30:58 +01:00
system.cpu.toL2Bus.respLayer0.occupancy 23407500 # Layer occupancy (ticks)
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2016-03-17 18:30:58 +01:00
system.cpu.toL2Bus.respLayer1.occupancy 6703500 # Layer occupancy (ticks)
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2016-03-17 18:30:58 +01:00
system.membus.trans_dist::ReadResp 3977 # Transaction distribution
system.membus.trans_dist::ReadExReq 2846 # Transaction distribution
system.membus.trans_dist::ReadExResp 2846 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 3977 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13646 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 13646 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 436672 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 436672 # Cumulative packet size per connected master and slave (bytes)
2014-12-23 15:31:20 +01:00
system.membus.snoops 0 # Total snoops (count)
2016-03-17 18:30:58 +01:00
system.membus.snoop_fanout::samples 6824 # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-03-17 18:30:58 +01:00
system.membus.snoop_fanout::0 6824 100.00% 100.00% # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
2016-03-17 18:30:58 +01:00
system.membus.snoop_fanout::total 6824 # Request fanout histogram
system.membus.reqLayer0.occupancy 7272500 # Layer occupancy (ticks)
2014-12-23 15:31:20 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2016-03-17 18:30:58 +01:00
system.membus.respLayer1.occupancy 34115000 # Layer occupancy (ticks)
2014-12-23 15:31:20 +01:00
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
2010-07-27 07:03:44 +02:00
---------- End Simulation Statistics ----------
