sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity
gem5/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt

490 lines
55 KiB
Text
Raw Normal View History

More regression updates. Get rid of caches in simple-timing config for now. tests/SConscript: another line for diff to ignore tests/configs/simple-timing.py: turn off caches for now tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt: tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout: tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt: tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout: update for inst/tick rate (old one was debug?) tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout: works now (no caches) --HG-- extra : convert_revision : 472030f63297346976db6274a78235c93d4eef8e
2006-08-17 00:48:15 +02:00
---------- Begin Simulation Statistics ----------
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
sim_seconds 0.000017 # Number of seconds simulated
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
sim_ticks 16524500 # Number of ticks simulated
final_tick 16524500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
host_inst_rate 396950 # Simulator instruction rate (inst/s)
host_op_rate 396157 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2535599202 # Simulator tick rate (ticks/s)
host_mem_usage 290048 # Number of bytes of host memory used
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
host_seconds 0.01 # Real time elapsed on the host
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
sim_insts 2577 # Number of instructions simulated
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
sim_ops 2577 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.physmem.bytes_read::cpu.inst 10432 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 5248 # Number of bytes read from this memory
system.physmem.bytes_read::total 15680 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 10432 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 10432 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 163 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 82 # Number of read requests responded to by this memory
system.physmem.num_reads::total 245 # Number of read requests responded to by this memory
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.bw_read::cpu.inst 631305032 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 317589034 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 948894066 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 631305032 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 631305032 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 631305032 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 317589034 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 948894066 # Total bandwidth to/from this memory (bytes/s)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
tests: update tests for TLB unification
2009-04-09 07:21:30 +02:00
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
Stats: Update the stats. --HG-- extra : convert_revision : 888b6e3bcd432a9318d4b8741a8b274c6f37f1a8
2007-08-27 05:27:53 +02:00
system.cpu.dtb.read_hits 415 # DTB read hits
system.cpu.dtb.read_misses 4 # DTB read misses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 419 # DTB read accesses
Stats: Update the stats. --HG-- extra : convert_revision : 888b6e3bcd432a9318d4b8741a8b274c6f37f1a8
2007-08-27 05:27:53 +02:00
system.cpu.dtb.write_hits 294 # DTB write hits
system.cpu.dtb.write_misses 4 # DTB write misses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 298 # DTB write accesses
system.cpu.dtb.data_hits 709 # DTB hits
system.cpu.dtb.data_misses 8 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 717 # DTB accesses
system.cpu.itb.fetch_hits 2586 # ITB hits
system.cpu.itb.fetch_misses 11 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 2597 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4 # Number of system calls
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.numCycles 33049 # number of cpu cycles simulated
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.committedInsts 2577 # Number of instructions committed
system.cpu.committedOps 2577 # Number of ops (including micro ops) committed
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
system.cpu.num_func_calls 140 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
system.cpu.num_int_insts 2375 # number of integer instructions
system.cpu.num_fp_insts 6 # number of float instructions
system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 717 # number of memory refs
system.cpu.num_load_insts 419 # Number of load instructions
system.cpu.num_store_insts 298 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.num_busy_cycles 33049 # Number of busy cycles
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
stats: updates due to branch predictor warming
2014-02-16 18:40:34 +01:00
system.cpu.Branches 396 # Number of branches fetched
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction
system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction
system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction
system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction
system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 2585 # Class of executed instruction
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 47.433873 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 627 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 82 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 7.646341 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 47.433873 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.011581 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.011581 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 82 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.020020 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1500 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1500 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 360 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 360 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 267 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 267 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 627 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 627 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 627 # number of overall hits
system.cpu.dcache.overall_hits::total 627 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 27 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 27 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 82 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 82 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 82 # number of overall misses
system.cpu.dcache.overall_misses::total 82 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1485000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 1485000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 4510000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 4510000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 4510000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 4510000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 415 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 415 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 709 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 709 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 709 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 709 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.132530 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.132530 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.091837 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.091837 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.115656 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.115656 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.115656 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.115656 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 27 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 27 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 82 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 82 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 82 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2942500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2942500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1444500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1444500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4387000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 4387000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4387000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 4387000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.132530 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.132530 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.091837 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.115656 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.115656 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.replacements 0 # number of replacements
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.tags.tagsinuse 80.042941 # Cycle average of tags in use
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.total_refs 2423 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 163 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 14.865031 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.tags.occ_blocks::cpu.inst 80.042941 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.039083 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.039083 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 163 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 61 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.079590 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 5335 # Number of tag accesses
system.cpu.icache.tags.data_accesses 5335 # Number of data accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_hits::cpu.inst 2423 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 2423 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 2423 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 2423 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 2423 # number of overall hits
system.cpu.icache.overall_hits::total 2423 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 163 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 163 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 163 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 163 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 163 # number of overall misses
system.cpu.icache.overall_misses::total 163 # number of overall misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.ReadReq_miss_latency::cpu.inst 8965500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 8965500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 8965500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 8965500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 8965500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 8965500 # number of overall miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_accesses::cpu.inst 2586 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 2586 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 2586 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 2586 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 2586 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 2586 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.063032 # miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.ReadReq_miss_rate::total 0.063032 # miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.demand_miss_rate::cpu.inst 0.063032 # miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.demand_miss_rate::total 0.063032 # miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.overall_miss_rate::cpu.inst 0.063032 # miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.overall_miss_rate::total 0.063032 # miss rate for overall accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55003.067485 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 55003.067485 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55003.067485 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 55003.067485 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55003.067485 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 55003.067485 # average overall miss latency
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
Update reference outputs --HG-- extra : convert_revision : 110a6c51cc1c562d115492b7360bfdbbded8eefd
2006-08-18 06:17:21 +02:00
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 163 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 163 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 163 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 163 # number of overall MSHR misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 8721000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 8721000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 8721000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 8721000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 8721000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 8721000 # number of overall MSHR miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.063032 # mshr miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.demand_mshr_miss_rate::total 0.063032 # mshr miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.overall_mshr_miss_rate::total 0.063032 # mshr miss rate for overall accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53503.067485 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53503.067485 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53503.067485 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 53503.067485 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53503.067485 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53503.067485 # average overall mshr miss latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.replacements 0 # number of replacements
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.tags.tagsinuse 107.153052 # Cycle average of tags in use
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 218 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.tags.occ_blocks::cpu.inst 80.161341 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 26.991711 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002446 # Average percentage of cache occupancy
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000824 # Average percentage of cache occupancy
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.occ_percent::total 0.003270 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.l2cache.tags.occ_task_id_blocks::1024 218 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 82 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.006653 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 2205 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 2205 # Number of data accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_misses::cpu.inst 163 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 218 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 27 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 27 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 163 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 82 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 245 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 163 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 82 # number of overall misses
system.cpu.l2cache.overall_misses::total 245 # number of overall misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 8558000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2887500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 11445500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1417500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1417500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 8558000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 4305000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 12863000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 8558000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 4305000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 12863000 # number of overall miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_accesses::cpu.inst 163 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 218 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 27 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 27 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 163 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 82 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 245 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 163 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 82 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 245 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52503.067485 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52502.293578 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52503.067485 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52502.040816 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52503.067485 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52502.040816 # average overall miss latency
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
Update reference outputs --HG-- extra : convert_revision : 110a6c51cc1c562d115492b7360bfdbbded8eefd
2006-08-18 06:17:21 +02:00
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 163 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 218 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 27 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 27 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 163 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 82 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 245 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 245 # number of overall MSHR misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6601500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2227500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8829000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1093500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1093500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6601500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3321000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 9922500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6601500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3321000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 9922500 # number of overall MSHR miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.trans_dist::ReadReq 218 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 218 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 326 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 164 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 490 # Packet count per connected master and slave (bytes)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10432 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5248 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 15680 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 245 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 245 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 245 # Request fanout histogram
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.reqLayer0.occupancy 122500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 244500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 123000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.trans_dist::ReadReq 218 # Transaction distribution
system.membus.trans_dist::ReadResp 218 # Transaction distribution
system.membus.trans_dist::ReadExReq 27 # Transaction distribution
system.membus.trans_dist::ReadExResp 27 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 490 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 490 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15680 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 15680 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 245 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 245 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 245 # Request fanout histogram
system.membus.reqLayer0.occupancy 245500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.5 # Layer utilization (%)
system.membus.respLayer1.occupancy 1225500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 7.4 # Layer utilization (%)
More regression updates. Get rid of caches in simple-timing config for now. tests/SConscript: another line for diff to ignore tests/configs/simple-timing.py: turn off caches for now tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt: tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout: tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt: tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout: update for inst/tick rate (old one was debug?) tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout: works now (no caches) --HG-- extra : convert_revision : 472030f63297346976db6274a78235c93d4eef8e
2006-08-17 00:48:15 +02:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink