Andreas Hansson 8909843a76 stats: Update stats to reflect cache and interconnect changes ... This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.		2015-03-02 05:04:20 -05:00
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minor-timing	stats: Update stats to reflect cache and interconnect changes	2015-03-02 05:04:20 -05:00
o3-timing	stats: Update stats to reflect cache and interconnect changes	2015-03-02 05:04:20 -05:00
simple-atomic	stats: updates due to changes to x86, stale configs.	2014-10-11 16:18:51 -05:00
simple-timing	stats: Update stats to reflect cache and interconnect changes	2015-03-02 05:04:20 -05:00
simple-timing-ruby	stats: Bump stats for decoder, TLB, prefetcher and DRAM changes	2014-12-23 09:31:20 -05:00
simple-timing-ruby-MESI_Two_Level	stats: Bump stats for decoder, TLB, prefetcher and DRAM changes	2014-12-23 09:31:20 -05:00
simple-timing-ruby-MOESI_CMP_directory	stats: Bump stats for decoder, TLB, prefetcher and DRAM changes	2014-12-23 09:31:20 -05:00
simple-timing-ruby-MOESI_CMP_token	stats: Bump stats for decoder, TLB, prefetcher and DRAM changes	2014-12-23 09:31:20 -05:00
simple-timing-ruby-MOESI_hammer	stats: Bump stats for decoder, TLB, prefetcher and DRAM changes	2014-12-23 09:31:20 -05:00