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gem5/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt

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Create reference outputs for this regression. --HG-- extra : convert_revision : 91e0144fef3f66d413417ad0318f43f752494e3c
2007-02-01 00:47:23 +01:00
---------- Begin Simulation Statistics ----------
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
sim_seconds 0.069793 # Number of seconds simulated
sim_ticks 69793219500 # Number of ticks simulated
final_tick 69793219500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
Create reference outputs for this regression. --HG-- extra : convert_revision : 91e0144fef3f66d413417ad0318f43f752494e3c
2007-02-01 00:47:23 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
host_inst_rate 248568 # Simulator instruction rate (inst/s)
host_op_rate 248568 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 46191499 # Simulator tick rate (ticks/s)
host_mem_usage 302704 # Number of bytes of host memory used
host_seconds 1510.95 # Real time elapsed on the host
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
sim_insts 375574808 # Number of instructions simulated
sim_ops 375574808 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.bytes_read::cpu.inst 221440 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 255808 # Number of bytes read from this memory
system.physmem.bytes_read::total 477248 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 221440 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 221440 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 3460 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 3997 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7457 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 3172801 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3665227 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 6838028 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 3172801 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 3172801 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 3172801 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3665227 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 6838028 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 7457 # Number of read requests accepted
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writeReqs 0 # Number of write requests accepted
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.readBursts 7457 # Number of DRAM read bursts, including those serviced by the write queue
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.bytesReadDRAM 477248 # Total number of bytes read from DRAM
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.bytesReadSys 477248 # Total read bytes from the system interface side
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.perBankRdBursts::0 527 # Per bank write bursts
system.physmem.perBankRdBursts::1 657 # Per bank write bursts
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.perBankRdBursts::2 455 # Per bank write bursts
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.perBankRdBursts::3 602 # Per bank write bursts
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.perBankRdBursts::4 446 # Per bank write bursts
system.physmem.perBankRdBursts::5 454 # Per bank write bursts
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.perBankRdBursts::6 515 # Per bank write bursts
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.perBankRdBursts::7 522 # Per bank write bursts
system.physmem.perBankRdBursts::8 438 # Per bank write bursts
system.physmem.perBankRdBursts::9 407 # Per bank write bursts
system.physmem.perBankRdBursts::10 339 # Per bank write bursts
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.perBankRdBursts::11 305 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.perBankRdBursts::12 414 # Per bank write bursts
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.perBankRdBursts::13 542 # Per bank write bursts
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.perBankRdBursts::14 455 # Per bank write bursts
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.perBankRdBursts::15 379 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.totGap 69793123000 # Total gap between requests
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.readPktSize::6 7457 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.rdQLenPdf::0 4245 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 1915 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 898 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 340 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.bytesPerActivate::samples 1360 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 348.047059 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 208.039838 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 346.646558 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 428 31.47% 31.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 327 24.04% 55.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 157 11.54% 67.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 92 6.76% 73.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 56 4.12% 77.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 39 2.87% 80.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 33 2.43% 83.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 25 1.84% 85.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 203 14.93% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1360 # Bytes accessed per row activation
system.physmem.totQLat 67335750 # Total ticks spent queuing
system.physmem.totMemAccLat 207154500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 37285000 # Total ticks spent in databus transfers
system.physmem.avgQLat 9029.87 # Average queueing delay per DRAM burst
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.avgMemAccLat 27779.87 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 6.84 # Average DRAM read bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.avgRdBWSys 6.84 # Average system read bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.busUtil 0.05 # Data bus utilization in percentage
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.readRowHits 6086 # Number of row buffer hits during reads
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.readRowHitRate 81.61 # Row buffer hit rate for reads
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.avgGap 9359410.35 # Average gap between requests
system.physmem.pageHitRate 81.61 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 5828760 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 3180375 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 32377800 # Energy for read commands per rank (pJ)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem_0.refreshEnergy 4558223280 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 2111779035 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 40020613500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 46732002750 # Total energy per rank (pJ)
system.physmem_0.averagePower 669.624038 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 66577889000 # Time in different power states
system.physmem_0.memoryStateTime::REF 2330380000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem_0.memoryStateTime::ACT 882777000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem_1.actEnergy 4430160 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 2417250 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 25272000 # Energy for read commands per rank (pJ)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem_1.refreshEnergy 4558223280 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 2013356565 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 40106949000 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 46710648255 # Total energy per rank (pJ)
system.physmem_1.averagePower 669.318049 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 66719394750 # Time in different power states
system.physmem_1.memoryStateTime::REF 2330380000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem_1.memoryStateTime::ACT 738657750 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.branchPred.lookups 51259743 # Number of BP lookups
system.cpu.branchPred.condPredicted 29683169 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1233682 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 26552604 # Number of BTB lookups
system.cpu.branchPred.BTBHits 23664767 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.branchPred.BTBHitPct 89.124091 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 9366329 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 317 # Number of incorrect RAS predictions.
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dtb.read_hits 103795078 # DTB read hits
system.cpu.dtb.read_misses 91880 # DTB read misses
system.cpu.dtb.read_acv 49322 # DTB read access violations
system.cpu.dtb.read_accesses 103886958 # DTB read accesses
system.cpu.dtb.write_hits 79431295 # DTB write hits
system.cpu.dtb.write_misses 1540 # DTB write misses
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.dtb.write_acv 2 # DTB write access violations
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dtb.write_accesses 79432835 # DTB write accesses
system.cpu.dtb.data_hits 183226373 # DTB hits
system.cpu.dtb.data_misses 93420 # DTB misses
system.cpu.dtb.data_acv 49324 # DTB access violations
system.cpu.dtb.data_accesses 183319793 # DTB accesses
system.cpu.itb.fetch_hits 51424924 # ITB hits
system.cpu.itb.fetch_misses 367 # ITB misses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.itb.fetch_acv 0 # ITB acv
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.itb.fetch_accesses 51425291 # ITB accesses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 215 # Number of system calls
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.numCycles 139586442 # number of cpu cycles simulated
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.fetch.icacheStallCycles 52218190 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 457878359 # Number of instructions fetch has processed
system.cpu.fetch.Branches 51259743 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 33031096 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 85762697 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 2573496 # Number of cycles fetch has spent squashing
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.fetch.TlbCycles 4 # Number of cycles fetch has spent waiting for tlb
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.fetch.MiscStallCycles 172 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 13442 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 10 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 51424924 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 558112 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 139281263 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 3.287437 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.344389 # Number of instructions fetched each cycle (Total)
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.fetch.rateDist::0 58400466 41.93% 41.93% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 4519538 3.24% 45.17% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 7300185 5.24% 50.42% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 5568881 4.00% 54.41% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 11993718 8.61% 63.03% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 8035210 5.77% 68.79% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 5954127 4.27% 73.07% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1896980 1.36% 74.43% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 35612158 25.57% 100.00% # Number of instructions fetched each cycle (Total)
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.fetch.rateDist::total 139281263 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.367226 # Number of branch fetches per cycle
system.cpu.fetch.rate 3.280250 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 45296559 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 16238717 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 71951122 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 4512320 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1282545 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 9579038 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 4257 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 452073358 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 14179 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 1282545 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 47196926 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 5664651 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 519192 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 74460720 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 10157229 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 448418638 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 439172 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 2532304 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 2861217 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 3565763 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 292805975 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 590541853 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 420605547 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 169936305 # Number of floating rename lookups
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.rename.UndoneMaps 33273646 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 37923 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 320 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 15988914 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 106425467 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 81691000 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 12462225 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 9670397 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 415046688 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 308 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 407272286 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 487219 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 39326693 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 18379010 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 93 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 139281263 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.924100 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 2.223091 # Number of insts issued each cycle
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iq.issued_per_cycle::0 24058662 17.27% 17.27% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 19633951 14.10% 31.37% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 22674806 16.28% 47.65% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 18925755 13.59% 61.24% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 19544360 14.03% 75.27% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 14234748 10.22% 85.49% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 9653364 6.93% 92.42% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 6204842 4.45% 96.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 4350775 3.12% 100.00% # Number of insts issued each cycle
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iq.issued_per_cycle::total 139281263 # Number of insts issued each cycle
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iq.fu_full::IntAlu 264805 1.33% 1.33% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 1.33% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 1.33% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 148480 0.74% 2.07% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 91560 0.46% 2.53% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 2226 0.01% 2.54% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 3500111 17.53% 20.07% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 1672568 8.38% 28.44% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 28.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 28.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.44% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 9323721 46.69% 75.13% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 4965817 24.87% 100.00% # attempts to use FU when none available
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iq.FU_type_0::IntAlu 153389569 37.66% 37.67% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 2128191 0.52% 38.19% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 38.19% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 37431648 9.19% 47.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 7537641 1.85% 49.24% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 2804878 0.69% 49.92% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 16758896 4.11% 54.04% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 1606846 0.39% 54.43% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.43% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 105464958 25.90% 80.33% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 80116078 19.67% 100.00% # Type of FU issued
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iq.FU_type_0::total 407272286 # Type of FU issued
system.cpu.iq.rate 2.917707 # Inst issue rate
system.cpu.iq.fu_busy_cnt 19969288 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.049032 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 626696170 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 266696972 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 237458259 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 347586172 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 187752417 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 163387975 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 246426590 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 180781403 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 19964423 # Number of loads that had data forwarded from stores
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iew.lsq.thread0.squashedLoads 11670980 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 165408 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 76048 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 8170271 # Number of stores squashed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iew.lsq.thread0.rescheduledLoads 382447 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 3767 # Number of times an access to memory failed due to the cache being blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iew.iewSquashCycles 1282545 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 4525606 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 90420 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 440059104 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 152527 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 106425467 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 81691000 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 308 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 7009 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 82356 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 76048 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 1000879 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 421168 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1422047 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 403473304 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 103936308 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 3798982 # Number of squashed instructions skipped in execute
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iew.exec_nop 25012108 # number of nop insts executed
system.cpu.iew.exec_refs 183369178 # number of memory reference insts executed
system.cpu.iew.exec_branches 46997600 # Number of branches executed
system.cpu.iew.exec_stores 79432870 # Number of stores executed
system.cpu.iew.exec_rate 2.890491 # Inst execution rate
system.cpu.iew.wb_sent 401684713 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 400846234 # cumulative count of insts written-back
system.cpu.iew.wb_producers 198095133 # num instructions producing a value
system.cpu.iew.wb_consumers 284050882 # num instructions consuming a value
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iew.wb_rate 2.871670 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.697393 # average fanout of values written-back
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.commit.commitSquashedInsts 41395670 # The number of squashed insts skipped by commit
Create reference outputs for this regression. --HG-- extra : convert_revision : 91e0144fef3f66d413417ad0318f43f752494e3c
2007-02-01 00:47:23 +01:00
system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.commit.branchMispredicts 1229479 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 133482933 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 2.986633 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 3.212859 # Number of insts commited each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.commit.committed_per_cycle::0 48683097 36.47% 36.47% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 18109981 13.57% 50.04% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 9618460 7.21% 57.24% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 8715508 6.53% 63.77% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 6449297 4.83% 68.61% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 4412968 3.31% 71.91% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 5003390 3.75% 75.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 2633066 1.97% 77.63% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 29857166 22.37% 100.00% # Number of insts commited each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.commit.committed_per_cycle::total 133482933 # Number of insts commited each cycle
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.commit.committedInsts 398664583 # Number of instructions committed
system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.commit.refs 168275216 # Number of memory references committed
system.cpu.commit.loads 94754487 # Number of loads committed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.commit.membars 0 # Number of memory barriers committed
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.commit.branches 44587533 # Number of branches committed
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions.
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.commit.int_insts 316365839 # Number of committed integer instructions.
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.commit.function_calls 8007752 # Number of function calls committed.
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::No_OpClass 23123356 5.80% 5.80% # Class of committed instruction
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.commit.op_class_0::IntAlu 141652545 35.53% 41.33% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 2124322 0.53% 41.86% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 41.86% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 35620060 8.93% 50.80% # Class of committed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::FloatCmp 7072549 1.77% 52.57% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 2735231 0.69% 53.26% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 16498021 4.14% 57.40% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 1563283 0.39% 57.79% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 57.79% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 57.79% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 57.79% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 57.79% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 57.79% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 57.79% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 57.79% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 57.79% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 57.79% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 57.79% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 57.79% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 57.79% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 57.79% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 57.79% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 57.79% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 57.79% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 57.79% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 57.79% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 57.79% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 57.79% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 57.79% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 94754487 23.77% 81.56% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 73520729 18.44% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 398664583 # Class of committed instruction
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.commit.bw_lim_events 29857166 # number cycles where commit BW limit reached
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.rob.rob_reads 543683043 # The number of ROB reads
system.cpu.rob.rob_writes 885930772 # The number of ROB writes
system.cpu.timesIdled 3165 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 305179 # Total number of cycles that the CPU has spent unscheduled due to idling
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.committedInsts 375574808 # Number of Instructions Simulated
system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.cpi 0.371661 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.371661 # CPI: Total CPI of All Threads
system.cpu.ipc 2.690625 # IPC: Instructions Per Cycle
system.cpu.ipc_total 2.690625 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 403591803 # number of integer regfile reads
system.cpu.int_regfile_writes 172078772 # number of integer regfile writes
system.cpu.fp_regfile_reads 157997982 # number of floating regfile reads
system.cpu.fp_regfile_writes 105636085 # number of floating regfile writes
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.misc_regfile_reads 350572 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.tags.replacements 806 # number of replacements
system.cpu.dcache.tags.tagsinuse 3297.136243 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 156944357 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 4209 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 37287.801616 # Average number of references to valid blocks.
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.tags.occ_blocks::cpu.data 3297.136243 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.804965 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.804965 # Average percentage of cache occupancy
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 3403 # Occupied blocks per task id
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::4 3119 # Occupied blocks per task id
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 0.830811 # Percentage of cache occupancy per task id
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.tags.tag_accesses 313935887 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 313935887 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 83443297 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 83443297 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 73501051 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 73501051 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits
system.cpu.dcache.demand_hits::cpu.data 156944348 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 156944348 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 156944348 # number of overall hits
system.cpu.dcache.overall_hits::total 156944348 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1804 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1804 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 19678 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 19678 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 21482 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 21482 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 21482 # number of overall misses
system.cpu.dcache.overall_misses::total 21482 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 122640500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 122640500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1228413709 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 1228413709 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 1351054209 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 1351054209 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 1351054209 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 1351054209 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 83445101 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 83445101 # number of ReadReq accesses(hits+misses)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 9 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 9 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 156965830 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 156965830 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 156965830 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 156965830 # number of overall (read+write) accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000022 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000268 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000268 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000137 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000137 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000137 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000137 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67982.538803 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 67982.538803 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62425.739862 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 62425.739862 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 62892.384741 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 62892.384741 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 62892.384741 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 62892.384741 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 51314 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 108 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 737 # number of cycles access was blocked
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 69.625509 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 108 # average number of cycles each access was blocked
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.writebacks::writebacks 682 # number of writebacks
system.cpu.dcache.writebacks::total 682 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 803 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 803 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16470 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 16470 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 17273 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 17273 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 17273 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 17273 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1001 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1001 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3208 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 3208 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 4209 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 4209 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 4209 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 4209 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 72824500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 72824500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 253362750 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 253362750 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 326187250 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 326187250 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 326187250 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 326187250 # number of overall MSHR miss cycles
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000012 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72751.748252 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72751.748252 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78978.413342 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78978.413342 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77497.564742 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 77497.564742 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77497.564742 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 77497.564742 # average overall mshr miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.tags.replacements 2160 # number of replacements
system.cpu.icache.tags.tagsinuse 1831.206745 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 51419247 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 4087 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 12581.171275 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.tags.occ_blocks::cpu.inst 1831.206745 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.894144 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.894144 # Average percentage of cache occupancy
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.tags.occ_task_id_blocks::1024 1927 # Occupied blocks per task id
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 168 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 289 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1348 # Occupied blocks per task id
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.tags.occ_task_id_percent::1024 0.940918 # Percentage of cache occupancy per task id
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.tags.tag_accesses 102853935 # Number of tag accesses
system.cpu.icache.tags.data_accesses 102853935 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 51419247 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 51419247 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 51419247 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 51419247 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 51419247 # number of overall hits
system.cpu.icache.overall_hits::total 51419247 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 5677 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 5677 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 5677 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 5677 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 5677 # number of overall misses
system.cpu.icache.overall_misses::total 5677 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 373029250 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 373029250 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 373029250 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 373029250 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 373029250 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 373029250 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 51424924 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 51424924 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 51424924 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 51424924 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 51424924 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 51424924 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000110 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000110 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000110 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000110 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000110 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000110 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65708.869121 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 65708.869121 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 65708.869121 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 65708.869121 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 65708.869121 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 65708.869121 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 290 # number of cycles access was blocked
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 58 # average number of cycles each access was blocked
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1590 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 1590 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 1590 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 1590 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 1590 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 1590 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4087 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 4087 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 4087 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 4087 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 4087 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 4087 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 274156250 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 274156250 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 274156250 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 274156250 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 274156250 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 274156250 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000079 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000079 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000079 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67080.070957 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67080.070957 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67080.070957 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 67080.070957 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67080.070957 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 67080.070957 # average overall mshr miss latency
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.replacements 0 # number of replacements
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.tags.tagsinuse 4023.366871 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 875 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 4863 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.179930 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.tags.occ_blocks::writebacks 372.059378 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2982.142231 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 669.165262 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.011354 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.091008 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.020421 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.122783 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 4863 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 148 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 135 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 529 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4051 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148407 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 79895 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 79895 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 627 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 134 # number of ReadReq hits
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.ReadReq_hits::total 761 # number of ReadReq hits
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.Writeback_hits::writebacks 682 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 682 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 78 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 78 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 627 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 212 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 839 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 627 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 212 # number of overall hits
system.cpu.l2cache.overall_hits::total 839 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 3460 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 867 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 4327 # number of ReadReq misses
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 3130 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 3130 # number of ReadExReq misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.demand_misses::cpu.inst 3460 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 3997 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 7457 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 3460 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 3997 # number of overall misses
system.cpu.l2cache.overall_misses::total 7457 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 263476500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 70328000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 333804500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 249238250 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 249238250 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 263476500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 319566250 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 583042750 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 263476500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 319566250 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 583042750 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 4087 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1001 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 5088 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 682 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 682 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 3208 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 3208 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 4087 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 4209 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 8296 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 4087 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 4209 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 8296 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.846587 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.866134 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.850432 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.975686 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.975686 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.846587 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.949632 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.898867 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.846587 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.949632 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.898867 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76149.277457 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81116.493656 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 77144.557430 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79628.833866 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79628.833866 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76149.277457 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79951.526145 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 78187.307228 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76149.277457 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79951.526145 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 78187.307228 # average overall miss latency
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3460 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 867 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 4327 # number of ReadReq MSHR misses
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3130 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 3130 # number of ReadExReq MSHR misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3460 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 3997 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 7457 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3460 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 3997 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 7457 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 220205500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 59518000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 279723500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 210540750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 210540750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 220205500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 270058750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 490264250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 220205500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 270058750 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 490264250 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.846587 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.866134 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.850432 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.975686 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.975686 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.846587 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.949632 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.898867 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.846587 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.949632 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.898867 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63643.208092 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68648.212226 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64646.059626 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67265.415335 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67265.415335 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63643.208092 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67565.361521 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65745.507577 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63643.208092 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67565.361521 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65745.507577 # average overall mshr miss latency
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.toL2Bus.trans_dist::ReadReq 5088 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 5088 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 682 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 3208 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 3208 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8174 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9100 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 17274 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 261568 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 313024 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 574592 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.toL2Bus.snoop_fanout::samples 8978 # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.toL2Bus.snoop_fanout::1 8978 100.00% 100.00% # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.toL2Bus.snoop_fanout::total 8978 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 5171000 # Layer occupancy (ticks)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.toL2Bus.respLayer0.occupancy 6830250 # Layer occupancy (ticks)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.toL2Bus.respLayer1.occupancy 6882750 # Layer occupancy (ticks)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.trans_dist::ReadReq 4327 # Transaction distribution
system.membus.trans_dist::ReadResp 4327 # Transaction distribution
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.trans_dist::ReadExReq 3130 # Transaction distribution
system.membus.trans_dist::ReadExResp 3130 # Transaction distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14914 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 14914 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 477248 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 477248 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.snoops 0 # Total snoops (count)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.snoop_fanout::samples 7457 # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.snoop_fanout::0 7457 100.00% 100.00% # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.snoop_fanout::total 7457 # Request fanout histogram
system.membus.reqLayer0.occupancy 9341500 # Layer occupancy (ticks)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.respLayer1.occupancy 39310250 # Layer occupancy (ticks)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
Create reference outputs for this regression. --HG-- extra : convert_revision : 91e0144fef3f66d413417ad0318f43f752494e3c
2007-02-01 00:47:23 +01:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink