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gem5/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt

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x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
---------- Begin Simulation Statistics ----------
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
sim_seconds 5.134221 # Number of seconds simulated
sim_ticks 5134220888000 # Number of ticks simulated
final_tick 5134220888000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
host_inst_rate 274165 # Simulator instruction rate (inst/s)
host_op_rate 545049 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 5772363280 # Simulator tick rate (ticks/s)
host_mem_usage 1013712 # Number of bytes of host memory used
host_seconds 889.45 # Real time elapsed on the host
sim_insts 243855553 # Number of instructions simulated
sim_ops 484792888 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 442496 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 5387840 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 144896 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 1908224 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker 2688 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst 377856 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 3143424 # Number of bytes read from this memory
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.bytes_read::total 11436096 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 442496 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 144896 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 377856 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 965248 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 9176704 # Number of bytes written to this memory
system.physmem.bytes_written::total 9176704 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 6914 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 84185 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 2264 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 29816 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker 42 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst 5904 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 49116 # Number of read requests responded to by this memory
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.num_reads::total 178689 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 143386 # Number of write requests responded to by this memory
system.physmem.num_writes::total 143386 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 86186 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 1049398 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 28222 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 371668 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker 524 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst 73596 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data 612249 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::pc.south_bridge.ide 5522 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2227426 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 86186 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 28222 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst 73596 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 188003 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1787361 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1787361 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1787361 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 86186 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 1049398 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 28222 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 371668 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker 524 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst 73596 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data 612249 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide 5522 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 4014786 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 87585 # Number of read requests accepted
system.physmem.writeReqs 96690 # Number of write requests accepted
system.physmem.readBursts 87585 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 96690 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 5601728 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 3712 # Total number of bytes read from write queue
system.physmem.bytesWritten 5458112 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 5605440 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 6188160 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 58 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 11390 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 914 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 5700 # Per bank write bursts
system.physmem.perBankRdBursts::1 5150 # Per bank write bursts
system.physmem.perBankRdBursts::2 4887 # Per bank write bursts
system.physmem.perBankRdBursts::3 5253 # Per bank write bursts
system.physmem.perBankRdBursts::4 5094 # Per bank write bursts
system.physmem.perBankRdBursts::5 4483 # Per bank write bursts
system.physmem.perBankRdBursts::6 5146 # Per bank write bursts
system.physmem.perBankRdBursts::7 4650 # Per bank write bursts
system.physmem.perBankRdBursts::8 5914 # Per bank write bursts
system.physmem.perBankRdBursts::9 5792 # Per bank write bursts
system.physmem.perBankRdBursts::10 5352 # Per bank write bursts
system.physmem.perBankRdBursts::11 5127 # Per bank write bursts
system.physmem.perBankRdBursts::12 5714 # Per bank write bursts
system.physmem.perBankRdBursts::13 6636 # Per bank write bursts
system.physmem.perBankRdBursts::14 6391 # Per bank write bursts
system.physmem.perBankRdBursts::15 6238 # Per bank write bursts
system.physmem.perBankWrBursts::0 5924 # Per bank write bursts
system.physmem.perBankWrBursts::1 5309 # Per bank write bursts
system.physmem.perBankWrBursts::2 4960 # Per bank write bursts
system.physmem.perBankWrBursts::3 5064 # Per bank write bursts
system.physmem.perBankWrBursts::4 5666 # Per bank write bursts
system.physmem.perBankWrBursts::5 4857 # Per bank write bursts
system.physmem.perBankWrBursts::6 5361 # Per bank write bursts
system.physmem.perBankWrBursts::7 4594 # Per bank write bursts
system.physmem.perBankWrBursts::8 5275 # Per bank write bursts
system.physmem.perBankWrBursts::9 5755 # Per bank write bursts
system.physmem.perBankWrBursts::10 5195 # Per bank write bursts
system.physmem.perBankWrBursts::11 4824 # Per bank write bursts
system.physmem.perBankWrBursts::12 5173 # Per bank write bursts
system.physmem.perBankWrBursts::13 6061 # Per bank write bursts
system.physmem.perBankWrBursts::14 5642 # Per bank write bursts
system.physmem.perBankWrBursts::15 5623 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.numWrRetry 29 # Number of times write queue was full causing retry
system.physmem.totGap 5133220754000 # Total gap between requests
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.readPktSize::6 87585 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.writePktSize::6 96690 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 81722 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 4619 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 680 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 175 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 44 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 32 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 35 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 30 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 33 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see
stats: changes due to recent changesets.
2015-01-11 01:06:43 +01:00
system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.rdQLenPdf::12 26 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 26 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see
stats: changes due to recent changesets.
2015-01-11 01:06:43 +01:00
system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.wrQLenPdf::0 127 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 65 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 62 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 60 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 56 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 54 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 53 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 53 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 53 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 53 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 53 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 53 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 53 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 54 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 52 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 1039 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 1172 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 3310 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 3495 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 3809 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 3692 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 3643 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 3794 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 4270 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 3928 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 3935 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 4892 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 4319 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 3751 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 5765 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 4380 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 4127 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 4040 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 759 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 534 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 685 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 1249 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 1282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 1191 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 1037 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 1374 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 1067 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 1059 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 1078 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 1047 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 775 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 681 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 674 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 568 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 373 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 186 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 159 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 198 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 198 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 135 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 116 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 118 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 113 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 84 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 57 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 55 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 69 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 50 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 67 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 38708 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 285.721608 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 170.408148 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 310.834116 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 15365 39.69% 39.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 9282 23.98% 63.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 4036 10.43% 74.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 2303 5.95% 80.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 1514 3.91% 83.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1118 2.89% 86.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 653 1.69% 88.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 582 1.50% 90.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 3855 9.96% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 38708 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 3628 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 24.124587 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 196.006736 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511 3625 99.92% 99.92% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-1535 1 0.03% 99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6144-6655 1 0.03% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::9728-10239 1 0.03% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 3628 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 3628 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 23.506891 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 17.576033 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 38.070070 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-15 79 2.18% 2.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-31 3330 91.79% 93.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-47 63 1.74% 95.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-63 14 0.39% 96.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-79 6 0.17% 96.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-95 13 0.36% 96.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-111 6 0.17% 96.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-127 13 0.36% 97.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-143 16 0.44% 97.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-159 18 0.50% 98.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-175 3 0.08% 98.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-191 8 0.22% 98.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-207 33 0.91% 99.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-223 3 0.08% 99.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-239 1 0.03% 99.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-255 2 0.06% 99.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::304-319 2 0.06% 99.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::320-335 3 0.08% 99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::336-351 1 0.03% 99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::352-367 7 0.19% 99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::368-383 3 0.08% 99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::384-399 1 0.03% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::560-575 2 0.06% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::576-591 1 0.03% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 3628 # Writes before turning the bus around for reads
system.physmem.totQLat 973946232 # Total ticks spent queuing
system.physmem.totMemAccLat 2615077482 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 437635000 # Total ticks spent in databus transfers
system.physmem.avgQLat 11127.38 # Average queueing delay per DRAM burst
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.avgMemAccLat 29877.38 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1.09 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.06 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1.09 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.21 # Average system write bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.physmem.busUtil 0.02 # Data bus utilization in percentage
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.avgWrQLen 10.98 # Average write queue length when enqueuing
system.physmem.readRowHits 70024 # Number of row buffer hits during reads
system.physmem.writeRowHits 64077 # Number of row buffer hits during writes
system.physmem.readRowHitRate 80.00 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 75.12 # Row buffer hit rate for writes
system.physmem.avgGap 27856305.81 # Average gap between requests
system.physmem.pageHitRate 77.59 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 138605040 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 75351375 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 314831400 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 270442800 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 250017758640 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 94326783165 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 2239415376750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 2584559149170 # Total energy per rank (pJ)
system.physmem_0.averagePower 667.799253 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 3683386249962 # Time in different power states
system.physmem_0.memoryStateTime::REF 127820940000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem_0.memoryStateTime::ACT 17097201288 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem_1.actEnergy 154027440 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 83877750 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 367863600 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 282191040 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 250017758640 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 95207179230 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 2235926942250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 2582039839950 # Total energy per rank (pJ)
system.physmem_1.averagePower 667.929569 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 3682087997664 # Time in different power states
system.physmem_1.memoryStateTime::REF 127820940000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem_1.memoryStateTime::ACT 18395204336 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.numCycles 861071319 # number of cpu cycles simulated
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.committedInsts 71289400 # Number of instructions committed
system.cpu0.committedOps 145467698 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 133359316 # Number of integer alu accesses
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.num_func_calls 922812 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 14140303 # number of instructions that are conditional controls
system.cpu0.num_int_insts 133359316 # number of integer instructions
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu0.num_fp_insts 0 # number of float instructions
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.num_int_register_reads 244470794 # number of times the integer registers were read
system.cpu0.num_int_register_writes 114705006 # number of times the integer registers were written
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.num_cc_register_reads 82965986 # number of times the CC registers were read
system.cpu0.num_cc_register_writes 55469495 # number of times the CC registers were written
system.cpu0.num_mem_refs 13497529 # number of memory refs
system.cpu0.num_load_insts 10019587 # Number of load instructions
system.cpu0.num_store_insts 3477942 # Number of store instructions
system.cpu0.num_idle_cycles 817633663.650796 # Number of idle cycles
system.cpu0.num_busy_cycles 43437655.349204 # Number of busy cycles
system.cpu0.not_idle_fraction 0.050446 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.949554 # Percentage of idle cycles
system.cpu0.Branches 15408320 # Number of branches fetched
system.cpu0.op_class::No_OpClass 89223 0.06% 0.06% # Class of executed instruction
system.cpu0.op_class::IntAlu 131776877 90.59% 90.65% # Class of executed instruction
system.cpu0.op_class::IntMult 58105 0.04% 90.69% # Class of executed instruction
system.cpu0.op_class::IntDiv 48148 0.03% 90.72% # Class of executed instruction
system.cpu0.op_class::FloatAdd 0 0.00% 90.72% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 90.72% # Class of executed instruction
system.cpu0.op_class::FloatCvt 0 0.00% 90.72% # Class of executed instruction
system.cpu0.op_class::FloatMult 0 0.00% 90.72% # Class of executed instruction
system.cpu0.op_class::FloatDiv 0 0.00% 90.72% # Class of executed instruction
system.cpu0.op_class::FloatSqrt 0 0.00% 90.72% # Class of executed instruction
system.cpu0.op_class::SimdAdd 0 0.00% 90.72% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc 0 0.00% 90.72% # Class of executed instruction
system.cpu0.op_class::SimdAlu 0 0.00% 90.72% # Class of executed instruction
system.cpu0.op_class::SimdCmp 0 0.00% 90.72% # Class of executed instruction
system.cpu0.op_class::SimdCvt 0 0.00% 90.72% # Class of executed instruction
system.cpu0.op_class::SimdMisc 0 0.00% 90.72% # Class of executed instruction
system.cpu0.op_class::SimdMult 0 0.00% 90.72% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc 0 0.00% 90.72% # Class of executed instruction
system.cpu0.op_class::SimdShift 0 0.00% 90.72% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.72% # Class of executed instruction
system.cpu0.op_class::SimdSqrt 0 0.00% 90.72% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.72% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.72% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.72% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.72% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.72% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.72% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 90.72% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.72% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.72% # Class of executed instruction
system.cpu0.op_class::MemRead 10017918 6.89% 97.61% # Class of executed instruction
system.cpu0.op_class::MemWrite 3477942 2.39% 100.00% # Class of executed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.op_class::total 145468213 # Class of executed instruction
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.dcache.tags.replacements 1637783 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.999406 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 19710876 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 1638295 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 12.031335 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.dcache.tags.occ_blocks::cpu0.data 144.289579 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 344.626695 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data 23.083132 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.281816 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.673099 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data 0.045084 # Average percentage of cache occupancy
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 219 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 270 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.dcache.tags.tag_accesses 88682212 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 88682212 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 4830179 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 2466757 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data 4264396 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 11561332 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 3346491 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 1735459 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data 3006073 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 8088023 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 19837 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data 10092 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu2.data 29821 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 59750 # number of SoftPFReq hits
system.cpu0.dcache.demand_hits::cpu0.data 8176670 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 4202216 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data 7270469 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 19649355 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 8196507 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 4212308 # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data 7300290 # number of overall hits
system.cpu0.dcache.overall_hits::total 19709105 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 348359 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 159608 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data 811619 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 1319586 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 127641 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 64125 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data 133967 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 325733 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 145510 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data 64697 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu2.data 196344 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 406551 # number of SoftPFReq misses
system.cpu0.dcache.demand_misses::cpu0.data 476000 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 223733 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data 945586 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 1645319 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 621510 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 288430 # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data 1141930 # number of overall misses
system.cpu0.dcache.overall_misses::total 2051870 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2193925000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 11673600356 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 13867525356 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2608735779 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 4432412697 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 7041148476 # number of WriteReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 4802660779 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data 16106013053 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 20908673832 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 4802660779 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data 16106013053 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 20908673832 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 5178538 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 2626365 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data 5076015 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 12880918 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 3474132 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 1799584 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data 3140040 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 8413756 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 165347 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 74789 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 226165 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 466301 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 8652670 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 4425949 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data 8216055 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 21294674 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 8818017 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 4500738 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data 8442220 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 21760975 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.067270 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.060771 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.159893 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.102445 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.036740 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.035633 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.042664 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.038714 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.880028 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.865060 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.868145 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.871864 # miss rate for SoftPFReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.055012 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.050550 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data 0.115090 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.077264 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.070482 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.064085 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data 0.135264 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.094291 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13745.708235 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14383.103841 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 10508.997031 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 40682.039439 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 33085.854703 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 21616.319120 # average WriteReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21466.036655 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17032.837894 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 12707.975676 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16651.044548 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 14104.203456 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 10190.057768 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 161116 # number of cycles access was blocked
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.dcache.blocked::no_mshrs 19020 # number of cycles access was blocked
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8.470873 # average number of cycles each access was blocked
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.dcache.writebacks::writebacks 1546722 # number of writebacks
system.cpu0.dcache.writebacks::total 1546722 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 49 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 374785 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 374834 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1569 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 32139 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 33708 # number of WriteReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data 1618 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data 406924 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 408542 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data 1618 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data 406924 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 408542 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 159559 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 436834 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 596393 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 62556 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 101828 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 164384 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 64697 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 192960 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 257657 # number of SoftPFReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 222115 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data 538662 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 760777 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 286812 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data 731622 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 1018434 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1953809500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 5644023259 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7597832759 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2418621221 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3692192265 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6110813486 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 904952750 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 2733042751 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 3637995501 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4372430721 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 9336215524 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 13708646245 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 5277383471 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 12069258275 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 17346641746 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30408890000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33050179000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63459069000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 531811000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 800665000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1332476000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 30940701000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33850844000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 64791545000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.060753 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086058 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.046301 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034761 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.032429 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019538 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.865060 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.853182 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.552555 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.050185 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.065562 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.035726 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.063726 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.086662 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.046801 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12245.059821 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12920.292969 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12739.641074 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38663.297222 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 36259.106189 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37174.016242 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13987.553519 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14163.778768 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14119.529068 # average SoftPFReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 19685.436468 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17332.233430 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18019.270095 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18400.148777 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16496.576477 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17032.661661 # average overall mshr miss latency
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.icache.tags.replacements 877463 # number of replacements
system.cpu0.icache.tags.tagsinuse 510.822061 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 128690361 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 877975 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 146.576339 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 150549344000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 275.387940 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 146.288168 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst 89.145952 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.537867 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.285719 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst 0.174113 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.997699 # Average percentage of cache occupancy
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.icache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 138 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.icache.tags.tag_accesses 130472306 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 130472306 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 86685680 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 38800184 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst 3204497 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 128690361 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 86685680 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 38800184 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst 3204497 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 128690361 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 86685680 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 38800184 # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst 3204497 # number of overall hits
system.cpu0.icache.overall_hits::total 128690361 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 302042 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 162655 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst 439255 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 903952 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 302042 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 162655 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst 439255 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 903952 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 302042 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 162655 # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst 439255 # number of overall misses
system.cpu0.icache.overall_misses::total 903952 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2276697249 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 6082026148 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 8358723397 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 2276697249 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst 6082026148 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 8358723397 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 2276697249 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst 6082026148 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 8358723397 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 86987722 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 38962839 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst 3643752 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 129594313 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 86987722 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 38962839 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst 3643752 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 129594313 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 86987722 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 38962839 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst 3643752 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 129594313 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003472 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004175 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.120550 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.006975 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003472 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004175 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst 0.120550 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.006975 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003472 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004175 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst 0.120550 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.006975 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13997.093535 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13846.230886 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 9246.866423 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13997.093535 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13846.230886 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 9246.866423 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13997.093535 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13846.230886 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 9246.866423 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 5936 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 21 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 289 # number of cycles access was blocked
stats: changes due to recent changesets.
2015-01-11 01:06:43 +01:00
system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.icache.avg_blocked_cycles::no_mshrs 20.539792 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets 21 # average number of cycles each access was blocked
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 25959 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 25959 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu2.inst 25959 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 25959 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu2.inst 25959 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 25959 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 162655 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 413296 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 575951 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 162655 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst 413296 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 575951 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 162655 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst 413296 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 575951 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2031893251 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 5207377551 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 7239270802 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2031893251 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 5207377551 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 7239270802 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2031893251 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 5207377551 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 7239270802 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004175 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.113426 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004444 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004175 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.113426 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.004444 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004175 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.113426 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.004444 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12492.042981 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12599.632106 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12569.247735 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12492.042981 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12599.632106 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12569.247735 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12492.042981 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12599.632106 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12569.247735 # average overall mshr miss latency
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.numCycles 2606018109 # number of cpu cycles simulated
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.committedInsts 35373738 # Number of instructions committed
system.cpu1.committedOps 68746890 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 63819737 # Number of integer alu accesses
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.num_func_calls 481772 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 6496386 # number of instructions that are conditional controls
system.cpu1.num_int_insts 63819737 # number of integer instructions
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu1.num_fp_insts 0 # number of float instructions
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.num_int_register_reads 118130559 # number of times the integer registers were read
system.cpu1.num_int_register_writes 54973369 # number of times the integer registers were written
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.num_cc_register_reads 36098608 # number of times the CC registers were read
system.cpu1.num_cc_register_writes 26881383 # number of times the CC registers were written
system.cpu1.num_mem_refs 4684980 # number of memory refs
system.cpu1.num_load_insts 2884758 # Number of load instructions
system.cpu1.num_store_insts 1800222 # Number of store instructions
system.cpu1.num_idle_cycles 2483538175.555252 # Number of idle cycles
system.cpu1.num_busy_cycles 122479933.444748 # Number of busy cycles
system.cpu1.not_idle_fraction 0.046999 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.953001 # Percentage of idle cycles
system.cpu1.Branches 7152522 # Number of branches fetched
system.cpu1.op_class::No_OpClass 34380 0.05% 0.05% # Class of executed instruction
system.cpu1.op_class::IntAlu 63978277 93.06% 93.11% # Class of executed instruction
system.cpu1.op_class::IntMult 29063 0.04% 93.16% # Class of executed instruction
system.cpu1.op_class::IntDiv 22112 0.03% 93.19% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 93.19% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 93.19% # Class of executed instruction
system.cpu1.op_class::FloatCvt 0 0.00% 93.19% # Class of executed instruction
system.cpu1.op_class::FloatMult 0 0.00% 93.19% # Class of executed instruction
system.cpu1.op_class::FloatDiv 0 0.00% 93.19% # Class of executed instruction
system.cpu1.op_class::FloatSqrt 0 0.00% 93.19% # Class of executed instruction
system.cpu1.op_class::SimdAdd 0 0.00% 93.19% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc 0 0.00% 93.19% # Class of executed instruction
system.cpu1.op_class::SimdAlu 0 0.00% 93.19% # Class of executed instruction
system.cpu1.op_class::SimdCmp 0 0.00% 93.19% # Class of executed instruction
system.cpu1.op_class::SimdCvt 0 0.00% 93.19% # Class of executed instruction
system.cpu1.op_class::SimdMisc 0 0.00% 93.19% # Class of executed instruction
system.cpu1.op_class::SimdMult 0 0.00% 93.19% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc 0 0.00% 93.19% # Class of executed instruction
system.cpu1.op_class::SimdShift 0 0.00% 93.19% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.19% # Class of executed instruction
system.cpu1.op_class::SimdSqrt 0 0.00% 93.19% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.19% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.19% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.19% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.19% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.19% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.19% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 93.19% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.19% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.19% # Class of executed instruction
system.cpu1.op_class::MemRead 2883100 4.19% 97.38% # Class of executed instruction
system.cpu1.op_class::MemWrite 1800222 2.62% 100.00% # Class of executed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.op_class::total 68747154 # Class of executed instruction
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu2.branchPred.lookups 29503892 # Number of BP lookups
system.cpu2.branchPred.condPredicted 29503892 # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect 342810 # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups 26694805 # Number of BTB lookups
system.cpu2.branchPred.BTBHits 25976378 # Number of BTB hits
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu2.branchPred.BTBHitPct 97.308739 # BTB Hit Percentage
system.cpu2.branchPred.usedRAS 611666 # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect 68809 # Number of incorrect RAS predictions.
system.cpu2.numCycles 155682865 # number of cpu cycles simulated
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu2.fetch.icacheStallCycles 11322292 # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts 145393707 # Number of instructions fetch has processed
system.cpu2.fetch.Branches 29503892 # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches 26588044 # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles 142785185 # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles 717310 # Number of cycles fetch has spent squashing
system.cpu2.fetch.TlbCycles 102884 # Number of cycles fetch has spent waiting for tlb
system.cpu2.fetch.MiscStallCycles 9783 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.PendingDrainCycles 8624 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu2.fetch.PendingTrapStallCycles 60469 # Number of stall cycles due to pending traps
system.cpu2.fetch.PendingQuiesceStallCycles 14 # Number of stall cycles due to pending quiesce instructions
system.cpu2.fetch.IcacheWaitRetryStallCycles 854 # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines 3643758 # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes 177822 # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.ItlbSquashes 3817 # Number of outstanding ITLB misses that were squashed
system.cpu2.fetch.rateDist::samples 154648109 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean 1.849994 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev 3.031354 # Number of instructions fetched each cycle (Total)
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu2.fetch.rateDist::0 98977108 64.00% 64.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1 881864 0.57% 64.57% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2 23689941 15.32% 79.89% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3 607646 0.39% 80.28% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4 853753 0.55% 80.84% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5 859687 0.56% 81.39% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6 584791 0.38% 81.77% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7 755278 0.49% 82.26% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8 27438041 17.74% 100.00% # Number of instructions fetched each cycle (Total)
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu2.fetch.rateDist::total 154648109 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate 0.189513 # Number of branch fetches per cycle
system.cpu2.fetch.rate 0.933910 # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles 10277895 # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles 94004330 # Number of cycles decode is blocked
system.cpu2.decode.RunCycles 21519674 # Number of cycles decode is running
system.cpu2.decode.UnblockCycles 4891128 # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles 359306 # Number of cycles decode is squashing
system.cpu2.decode.DecodedInsts 283040141 # Number of instructions handled by decode
system.cpu2.rename.SquashCycles 359306 # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles 12341484 # Number of cycles rename is idle
system.cpu2.rename.BlockCycles 77022094 # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles 4867618 # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles 24062417 # Number of cycles rename is running
system.cpu2.rename.UnblockCycles 12399480 # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts 281740718 # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents 206678 # Number of times rename has blocked due to ROB full
system.cpu2.rename.IQFullEvents 5855345 # Number of times rename has blocked due to IQ full
system.cpu2.rename.LQFullEvents 68061 # Number of times rename has blocked due to LQ full
system.cpu2.rename.SQFullEvents 4394741 # Number of times rename has blocked due to SQ full
system.cpu2.rename.RenamedOperands 336544944 # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups 615400877 # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups 377780143 # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups 207 # Number of floating rename lookups
system.cpu2.rename.CommittedMaps 323636169 # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps 12908773 # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts 167322 # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts 168903 # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts 23920372 # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads 6854331 # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores 3831116 # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads 436605 # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores 369940 # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded 279698877 # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded 432383 # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued 277466645 # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued 109952 # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined 9178493 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined 14257252 # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved 68980 # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples 154648109 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean 1.794181 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev 2.395462 # Number of insts issued each cycle
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu2.iq.issued_per_cycle::0 91599661 59.23% 59.23% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1 5400101 3.49% 62.72% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2 3869243 2.50% 65.22% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3 3752650 2.43% 67.65% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4 22658386 14.65% 82.30% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5 2693281 1.74% 84.04% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6 23975807 15.50% 99.55% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7 476523 0.31% 99.86% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8 222457 0.14% 100.00% # Number of insts issued each cycle
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu2.iq.issued_per_cycle::total 154648109 # Number of insts issued each cycle
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu2.iq.fu_full::IntAlu 1665704 85.56% 85.56% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult 0 0.00% 85.56% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv 0 0.00% 85.56% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd 0 0.00% 85.56% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp 0 0.00% 85.56% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt 0 0.00% 85.56% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult 0 0.00% 85.56% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv 0 0.00% 85.56% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 85.56% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd 0 0.00% 85.56% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 85.56% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu 0 0.00% 85.56% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp 0 0.00% 85.56% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt 0 0.00% 85.56% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc 0 0.00% 85.56% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult 0 0.00% 85.56% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 85.56% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift 0 0.00% 85.56% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 85.56% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 85.56% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 85.56% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 85.56% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 85.56% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 85.56% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 85.56% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 85.56% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 85.56% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 85.56% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 85.56% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead 217161 11.15% 96.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite 64057 3.29% 100.00% # attempts to use FU when none available
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu2.iq.FU_type_0::No_OpClass 83075 0.03% 0.03% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu 266581381 96.08% 96.11% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult 59040 0.02% 96.13% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv 53621 0.02% 96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt 87 0.00% 96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.15% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead 7156038 2.58% 98.73% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite 3533403 1.27% 100.00% # Type of FU issued
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu2.iq.FU_type_0::total 277466645 # Type of FU issued
system.cpu2.iq.rate 1.782256 # Inst issue rate
system.cpu2.iq.fu_busy_cnt 1946922 # FU busy when requested
system.cpu2.iq.fu_busy_rate 0.007017 # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads 711637991 # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes 289314219 # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses 275821613 # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads 281 # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes 236 # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses 108 # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses 279330355 # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses 137 # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads 727263 # Number of loads that had data forwarded from stores
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu2.iew.lsq.thread0.squashedLoads 1301667 # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses 5946 # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation 5330 # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores 686178 # Number of stores squashed
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu2.iew.lsq.thread0.rescheduledLoads 750303 # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked 28695 # Number of times an access to memory failed due to the cache being blocked
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu2.iew.iewSquashCycles 359306 # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles 71000950 # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles 2910946 # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts 280131260 # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts 44826 # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts 6854348 # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts 3831116 # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts 254274 # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents 173954 # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents 2389293 # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents 5330 # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect 193600 # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect 205490 # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts 399090 # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts 276846611 # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts 7005762 # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts 563321 # Number of squashed instructions skipped in execute
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.iew.exec_swp 0 # number of swp insts executed
system.cpu2.iew.exec_nop 0 # number of nop insts executed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu2.iew.exec_refs 10447548 # number of memory reference insts executed
system.cpu2.iew.exec_branches 28131020 # Number of branches executed
system.cpu2.iew.exec_stores 3441786 # Number of stores executed
system.cpu2.iew.exec_rate 1.778273 # Inst execution rate
system.cpu2.iew.wb_sent 276647008 # cumulative count of insts sent to commit
system.cpu2.iew.wb_count 275821721 # cumulative count of insts written-back
system.cpu2.iew.wb_producers 215019240 # num instructions producing a value
system.cpu2.iew.wb_consumers 352722264 # num instructions consuming a value
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu2.iew.wb_rate 1.771690 # insts written-back per cycle
system.cpu2.iew.wb_fanout 0.609599 # average fanout of values written-back
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu2.commit.commitSquashedInsts 9550045 # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls 363403 # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts 345846 # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples 153217834 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean 1.765971 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev 2.651639 # Number of insts commited each cycle
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu2.commit.committed_per_cycle::0 95448328 62.30% 62.30% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1 4376826 2.86% 65.15% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2 1280143 0.84% 65.99% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3 24626260 16.07% 82.06% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4 968124 0.63% 82.69% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5 723433 0.47% 83.16% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6 420249 0.27% 83.44% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7 23244515 15.17% 98.61% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8 2129956 1.39% 100.00% # Number of insts commited each cycle
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu2.commit.committed_per_cycle::total 153217834 # Number of insts commited each cycle
system.cpu2.commit.committedInsts 137192415 # Number of instructions committed
system.cpu2.commit.committedOps 270578300 # Number of ops (including micro ops) committed
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu2.commit.refs 8697618 # Number of memory references committed
system.cpu2.commit.loads 5552680 # Number of loads committed
system.cpu2.commit.membars 162630 # Number of memory barriers committed
system.cpu2.commit.branches 27696347 # Number of branches committed
stats: changes due to recent changesets.
2015-01-11 01:06:43 +01:00
system.cpu2.commit.fp_insts 48 # Number of committed floating point instructions.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu2.commit.int_insts 247309305 # Number of committed integer instructions.
system.cpu2.commit.function_calls 454335 # Number of function calls committed.
system.cpu2.commit.op_class_0::No_OpClass 48751 0.02% 0.02% # Class of committed instruction
system.cpu2.commit.op_class_0::IntAlu 261723532 96.73% 96.75% # Class of committed instruction
system.cpu2.commit.op_class_0::IntMult 56607 0.02% 96.77% # Class of committed instruction
system.cpu2.commit.op_class_0::IntDiv 51834 0.02% 96.79% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.79% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.79% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCvt 16 0.00% 96.79% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.79% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.79% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.79% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.79% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.79% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.79% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.79% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.79% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.79% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.79% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.79% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.79% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.79% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.79% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.79% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.79% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.79% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.79% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.79% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.79% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.79% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.79% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.79% # Class of committed instruction
system.cpu2.commit.op_class_0::MemRead 5552622 2.05% 98.84% # Class of committed instruction
system.cpu2.commit.op_class_0::MemWrite 3144938 1.16% 100.00% # Class of committed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu2.commit.op_class_0::total 270578300 # Class of committed instruction
system.cpu2.commit.bw_lim_events 2129956 # number cycles where commit BW limit reached
system.cpu2.rob.rob_reads 431186663 # The number of ROB reads
system.cpu2.rob.rob_writes 561693850 # The number of ROB writes
system.cpu2.timesIdled 124283 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles 1034756 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles 4900728082 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts 137192415 # Number of Instructions Simulated
system.cpu2.committedOps 270578300 # Number of Ops (including micro ops) Simulated
system.cpu2.cpi 1.134777 # CPI: Cycles Per Instruction
system.cpu2.cpi_total 1.134777 # CPI: Total CPI of All Threads
system.cpu2.ipc 0.881230 # IPC: Instructions Per Cycle
system.cpu2.ipc_total 0.881230 # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads 368834984 # number of integer regfile reads
system.cpu2.int_regfile_writes 221067360 # number of integer regfile writes
system.cpu2.fp_regfile_reads 73020 # number of floating regfile reads
system.cpu2.fp_regfile_writes 72968 # number of floating regfile writes
system.cpu2.cc_regfile_reads 140711927 # number of cc regfile reads
system.cpu2.cc_regfile_writes 108060819 # number of cc regfile writes
system.cpu2.misc_regfile_reads 90227595 # number of misc regfile reads
system.cpu2.misc_regfile_writes 143035 # number of misc regfile writes
system.iobus.trans_dist::ReadReq 3553360 # Transaction distribution
system.iobus.trans_dist::ReadResp 3553360 # Transaction distribution
stats: changes due to recent changesets.
2015-01-11 01:06:43 +01:00
system.iobus.trans_dist::WriteReq 57725 # Transaction distribution
system.iobus.trans_dist::WriteResp 11005 # Transaction distribution
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.trans_dist::MessageReq 1679 # Transaction distribution
system.iobus.trans_dist::MessageResp 1679 # Transaction distribution
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
stats: changes due to recent changesets.
2015-01-11 01:06:43 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7082618 # Packet count per connected master and slave (bytes)
stats: changes due to recent changesets.
2015-01-11 01:06:43 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1154 # Packet count per connected master and slave (bytes)
x86: Update stats for the new Linux delay port.
2014-11-22 02:22:19 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
stats: changes due to recent changesets.
2015-01-11 01:06:43 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27896 # Packet count per connected master and slave (bytes)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::total 7126912 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95258 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95258 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3358 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3358 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 7225528 # Packet count per connected master and slave (bytes)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
stats: changes due to recent changesets.
2015-01-11 01:06:43 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3541309 # Cumulative packet size per connected master and slave (bytes)
stats: changes due to recent changesets.
2015-01-11 01:06:43 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2308 # Cumulative packet size per connected master and slave (bytes)
x86: Update stats for the new Linux delay port.
2014-11-22 02:22:19 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
stats: changes due to recent changesets.
2015-01-11 01:06:43 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13948 # Cumulative packet size per connected master and slave (bytes)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::total 3569655 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027816 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027816 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6716 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6716 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 6604187 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 2698688 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.reqLayer1.occupancy 21000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.reqLayer3.occupancy 5333000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 4000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer5.occupancy 758000 # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
stats: changes due to recent changesets.
2015-01-11 01:06:43 +01:00
system.iobus.reqLayer6.occupancy 34000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.reqLayer7.occupancy 15000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.reqLayer9.occupancy 141310000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.reqLayer10.occupancy 414000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.reqLayer11.occupancy 78000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.reqLayer14.occupancy 10425000 # Layer occupancy (ticks)
x86: Update stats for the new Linux delay port.
2014-11-22 02:22:19 +01:00
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.reqLayer18.occupancy 4000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.reqLayer19.occupancy 116029251 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
x86: Update stats for the new Linux delay port.
2014-11-22 02:22:19 +01:00
system.iobus.reqLayer20.occupancy 1032000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.respLayer0.occupancy 300958000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.respLayer1.occupancy 24266250 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.respLayer2.occupancy 1136000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.tags.replacements 47574 # number of replacements
system.iocache.tags.tagsinuse 0.081409 # Cycle average of tags in use
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.tags.sampled_refs 47590 # Sample count of references to valid blocks.
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.tags.warmup_cycle 5000597695009 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.081409 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005088 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.005088 # Average percentage of cache occupancy
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.tags.tag_accesses 428661 # Number of tag accesses
system.iocache.tags.data_accesses 428661 # Number of data accesses
system.iocache.ReadReq_misses::pc.south_bridge.ide 909 # number of ReadReq misses
system.iocache.ReadReq_misses::total 909 # number of ReadReq misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.demand_misses::pc.south_bridge.ide 909 # number of demand (read+write) misses
system.iocache.demand_misses::total 909 # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide 909 # number of overall misses
system.iocache.overall_misses::total 909 # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 125652013 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 125652013 # number of ReadReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 3845868988 # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total 3845868988 # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide 125652013 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 125652013 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide 125652013 # number of overall miss cycles
system.iocache.overall_miss_latency::total 125652013 # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide 909 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.demand_accesses::pc.south_bridge.ide 909 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 909 # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide 909 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 909 # number of overall (read+write) accesses
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 138231.037404 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 138231.037404 # average ReadReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 82317.401284 # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 82317.401284 # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 138231.037404 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 138231.037404 # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 138231.037404 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 138231.037404 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 13512 # number of cycles access was blocked
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.blocked::no_mshrs 2030 # number of cycles access was blocked
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.avg_blocked_cycles::no_mshrs 6.656158 # average number of cycles each access was blocked
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.fast_writes 0 # number of fast writes performed
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.cache_copies 0 # number of cache copies performed
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.writebacks::writebacks 46667 # number of writebacks
system.iocache.writebacks::total 46667 # number of writebacks
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 745 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 745 # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 21024 # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total 21024 # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide 745 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 745 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide 745 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 745 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 86664503 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 86664503 # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2752610998 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2752610998 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 86664503 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 86664503 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 86664503 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 86664503 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.819582 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 0.819582 # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.450000 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.450000 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.819582 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 0.819582 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.819582 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 0.819582 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 116328.191946 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 116328.191946 # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 130927.083238 # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 130927.083238 # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 116328.191946 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 116328.191946 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 116328.191946 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 116328.191946 # average overall mshr miss latency
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.l2c.tags.replacements 105420 # number of replacements
system.l2c.tags.tagsinuse 64829.150073 # Cycle average of tags in use
system.l2c.tags.total_refs 3714265 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 169452 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 21.919275 # Average number of references to valid blocks.
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.l2c.tags.occ_blocks::writebacks 51423.363344 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.134649 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 1822.192254 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 5065.443853 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 236.253380 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 1546.126379 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.dtb.walker 11.729356 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst 913.877634 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data 3810.029226 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.784658 # Average percentage of cache occupancy
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.l2c.tags.occ_percent::cpu0.inst 0.027804 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.077293 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.003605 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.023592 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000179 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst 0.013945 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data 0.058136 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.989214 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024 64032 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 535 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 3173 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 7219 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 53036 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024 0.977051 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 34034094 # Number of tag accesses
system.l2c.tags.data_accesses 34034094 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 19379 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 10642 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 295114 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 477769 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 12495 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 7386 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 160391 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 220397 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.dtb.walker 66650 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.itb.walker 14282 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst 407368 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data 616656 # number of ReadReq hits
system.l2c.ReadReq_hits::total 2308529 # number of ReadReq hits
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits
system.l2c.WriteReq_hits::total 2 # number of WriteReq hits
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.l2c.Writeback_hits::writebacks 1546722 # number of Writeback hits
system.l2c.Writeback_hits::total 1546722 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 113 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 56 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data 89 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 258 # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 58538 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 36097 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data 64817 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 159452 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 19379 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 10644 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 295114 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 536307 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 12495 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 7386 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 160391 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 256494 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.dtb.walker 66650 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.itb.walker 14282 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst 407368 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data 681473 # number of demand (read+write) hits
system.l2c.demand_hits::total 2467983 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 19379 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 10644 # number of overall hits
system.l2c.overall_hits::cpu0.inst 295114 # number of overall hits
system.l2c.overall_hits::cpu0.data 536307 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 12495 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 7386 # number of overall hits
system.l2c.overall_hits::cpu1.inst 160391 # number of overall hits
system.l2c.overall_hits::cpu1.data 256494 # number of overall hits
system.l2c.overall_hits::cpu2.dtb.walker 66650 # number of overall hits
system.l2c.overall_hits::cpu2.itb.walker 14282 # number of overall hits
system.l2c.overall_hits::cpu2.inst 407368 # number of overall hits
system.l2c.overall_hits::cpu2.data 681473 # number of overall hits
system.l2c.overall_hits::total 2467983 # number of overall hits
system.l2c.ReadReq_misses::cpu0.itb.walker 5 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst 6915 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 16100 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 2264 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 3859 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.dtb.walker 42 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst 5904 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data 13093 # number of ReadReq misses
system.l2c.ReadReq_misses::total 48182 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 632 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 257 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data 496 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 1385 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 68358 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 26158 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data 36472 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 130988 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.itb.walker 5 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 6915 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 84458 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 2264 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 30017 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.dtb.walker 42 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst 5904 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data 49565 # number of demand (read+write) misses
system.l2c.demand_misses::total 179170 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.itb.walker 5 # number of overall misses
system.l2c.overall_misses::cpu0.inst 6915 # number of overall misses
system.l2c.overall_misses::cpu0.data 84458 # number of overall misses
system.l2c.overall_misses::cpu1.inst 2264 # number of overall misses
system.l2c.overall_misses::cpu1.data 30017 # number of overall misses
system.l2c.overall_misses::cpu2.dtb.walker 42 # number of overall misses
system.l2c.overall_misses::cpu2.inst 5904 # number of overall misses
system.l2c.overall_misses::cpu2.data 49565 # number of overall misses
system.l2c.overall_misses::total 179170 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu1.inst 185117250 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 320324250 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 3767000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst 506409000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data 1123352250 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 2138969750 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 5734849 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data 6109808 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 11844657 # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 1967190465 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data 2891355862 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 4858546327 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu1.inst 185117250 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 2287514715 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.dtb.walker 3767000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst 506409000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data 4014708112 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 6997516077 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.inst 185117250 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 2287514715 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.dtb.walker 3767000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst 506409000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data 4014708112 # number of overall miss cycles
system.l2c.overall_miss_latency::total 6997516077 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 19379 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 10647 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 302029 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 493869 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 12495 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 7386 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 162655 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 224256 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.dtb.walker 66692 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.itb.walker 14282 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst 413272 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data 629749 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 2356711 # number of ReadReq accesses(hits+misses)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.l2c.WriteReq_accesses::cpu0.itb.walker 2 # number of WriteReq accesses(hits+misses)
system.l2c.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.l2c.Writeback_accesses::writebacks 1546722 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 1546722 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 745 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 313 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data 585 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 1643 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 126896 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 62255 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data 101289 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 290440 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 19379 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 10649 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 302029 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 620765 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 12495 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 7386 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 162655 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 286511 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.dtb.walker 66692 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.itb.walker 14282 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst 413272 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data 731038 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 2647153 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 19379 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 10649 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 302029 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 620765 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 12495 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 7386 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 162655 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 286511 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.dtb.walker 66692 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.itb.walker 14282 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst 413272 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data 731038 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2647153 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000470 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.022895 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.032600 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.013919 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.017208 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000630 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst 0.014286 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data 0.020791 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.020445 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.848322 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.821086 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data 0.847863 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.842970 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.538693 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.420175 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data 0.360079 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.450998 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.000470 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.022895 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.136055 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.013919 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.104767 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000630 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst 0.014286 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data 0.067801 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.067684 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.000470 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.022895 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.136055 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.013919 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.104767 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000630 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst 0.014286 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data 0.067801 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.067684 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 81765.569788 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 83007.061415 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 89690.476190 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 85773.882114 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data 85797.926373 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 44393.544270 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 22314.587549 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 12318.161290 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 8552.098917 # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75204.161824 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 79276.043595 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 37091.537599 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 81765.569788 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 76207.306360 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 89690.476190 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 85773.882114 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 80998.852255 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 39055.177078 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 81765.569788 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 76207.306360 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 89690.476190 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 85773.882114 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 80998.852255 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 39055.177078 # average overall miss latency
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.l2c.writebacks::writebacks 96719 # number of writebacks
system.l2c.writebacks::total 96719 # number of writebacks
system.l2c.ReadReq_mshr_misses::cpu1.inst 2264 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 3859 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 42 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.inst 5904 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.data 13093 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 25162 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 257 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data 496 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 753 # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 26158 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data 36472 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 62630 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 2264 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 30017 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.dtb.walker 42 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst 5904 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data 49565 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 87792 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 2264 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 30017 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.dtb.walker 42 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst 5904 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data 49565 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 87792 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 156732750 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 272024750 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 3239000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 432457000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data 959731250 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 1824184750 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5165744 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 8859994 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 14025738 # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1640131535 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 2435332138 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 4075463673 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 156732750 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 1912156285 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 3239000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst 432457000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data 3395063388 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 5899648423 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 156732750 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 1912156285 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 3239000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst 432457000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data 3395063388 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 5899648423 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 27747826000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30174191500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 57922017500 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 492354000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 747099000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 1239453000 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28240180000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data 30921290500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 59161470500 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.013919 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.017208 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000630 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.014286 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.020791 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.010677 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.821086 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.847863 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.458308 # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.420175 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.360079 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.215638 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.013919 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.104767 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000630 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014286 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data 0.067801 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.033165 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.013919 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.104767 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000630 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014286 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data 0.067801 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.033165 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69228.246466 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 70490.995076 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 77119.047619 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 73248.136856 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 73301.096005 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 72497.605516 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20100.171206 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 17862.891129 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 18626.478088 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62700.953246 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 66772.651294 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 65072.068865 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69228.246466 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63702.444781 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 77119.047619 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73248.136856 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 68497.193342 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 67200.296417 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69228.246466 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63702.444781 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 77119.047619 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73248.136856 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 68497.193342 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 67200.296417 # average overall mshr miss latency
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.trans_dist::ReadReq 5119167 # Transaction distribution
system.membus.trans_dist::ReadResp 5119165 # Transaction distribution
system.membus.trans_dist::WriteReq 13931 # Transaction distribution
system.membus.trans_dist::WriteResp 13931 # Transaction distribution
system.membus.trans_dist::Writeback 143386 # Transaction distribution
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.trans_dist::UpgradeReq 1652 # Transaction distribution
system.membus.trans_dist::UpgradeResp 1652 # Transaction distribution
system.membus.trans_dist::ReadExReq 130721 # Transaction distribution
system.membus.trans_dist::ReadExResp 130721 # Transaction distribution
system.membus.trans_dist::MessageReq 1679 # Transaction distribution
system.membus.trans_dist::MessageResp 1679 # Transaction distribution
stats: changes due to recent changesets.
2015-01-11 01:06:43 +01:00
system.membus.trans_dist::BadAddressError 2 # Transaction distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3358 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total 3358 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7126912 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3041102 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 457338 # Packet count per connected master and slave (bytes)
stats: changes due to recent changesets.
2015-01-11 01:06:43 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 4 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.pkt_count_system.l2c.mem_side::total 10625356 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141623 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 141623 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 10770337 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6716 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::total 6716 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3569655 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6082201 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17609408 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 27261264 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6015616 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 6015616 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 33283596 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 789 # Total snoops (count)
system.membus.snoop_fanout::samples 371599 # Request fanout histogram
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.snoop_fanout::1 371599 100.00% 100.00% # Request fanout histogram
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.snoop_fanout::total 371599 # Request fanout histogram
system.membus.reqLayer0.occupancy 233199000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.reqLayer1.occupancy 303775500 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.reqLayer2.occupancy 2272000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.reqLayer3.occupancy 587213160 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
stats: changes due to recent changesets.
2015-01-11 01:06:43 +01:00
system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.respLayer0.occupancy 1136000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.respLayer2.occupancy 1313776839 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.respLayer4.occupancy 24877750 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
stats: changes due to recent changesets.
2015-01-11 01:06:43 +01:00
system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.toL2Bus.trans_dist::ReadReq 7456393 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 7455858 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 13933 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 13933 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 1546722 # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq 21038 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 1643 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 1643 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 290440 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 290440 # Transaction distribution
stats: changes due to recent changesets.
2015-01-11 01:06:43 +01:00
system.toL2Bus.trans_dist::BadAddressError 2 # Transaction distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1755962 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 14994862 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 74580 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 223072 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 17048476 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 56190016 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213507600 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 279632 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 823928 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 270801176 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 69805 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 4272022 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 3.011152 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.105014 # Request fanout histogram
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.toL2Bus.snoop_fanout::3 4224379 98.88% 98.88% # Request fanout histogram
system.toL2Bus.snoop_fanout::4 47643 1.12% 100.00% # Request fanout histogram
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.toL2Bus.snoop_fanout::total 4272022 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 2506180983 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 318000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.toL2Bus.respLayer0.occupancy 865936683 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.toL2Bus.respLayer1.occupancy 1938409360 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 26348986 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.toL2Bus.respLayer3.occupancy 96467647 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
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