gem5/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  5.137752                       # Number of seconds simulated
sim_ticks                                5137751757500                       # Number of ticks simulated
final_tick                               5137751757500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 311526                       # Simulator instruction rate (inst/s)
host_op_rate                                   619354                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             6572918502                       # Simulator tick rate (ticks/s)
host_mem_usage                                 927072                       # Number of bytes of host memory used
host_seconds                                   781.65                       # Real time elapsed on the host
sim_insts                                   243506025                       # Number of instructions simulated
sim_ops                                     484120527                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          256                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           475328                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          5564736                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           130048                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          2113344                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker         2688                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst           362880                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data          2752000                       # Number of bytes read from this memory
system.physmem.bytes_read::total             11429696                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       475328                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       130048                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst       362880                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          968256                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      6180416                       # Number of bytes written to this memory
system.physmem.bytes_written::pc.south_bridge.ide      2990080                       # Number of bytes written to this memory
system.physmem.bytes_written::total           9170496                       # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            4                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst              7427                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             86949                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              2032                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             33021                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker           42                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst              5670                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data             43000                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                178589                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           96569                       # Number of write requests responded to by this memory
system.physmem.num_writes::pc.south_bridge.ide        46720                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               143289                       # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide         5518                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            50                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               92517                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             1083107                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker            12                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               25312                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              411336                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker           523                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst               70630                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data              535643                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2224649                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          92517                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          25312                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst          70630                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             188459                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1202942                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::pc.south_bridge.ide       581982                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1784924                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1202942                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide       587501                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           50                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              92517                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            1083107                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker           12                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              25312                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             411336                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker          523                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst              70630                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data             535643                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                4009573                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                         84209                       # Number of read requests accepted
system.physmem.writeReqs                        74716                       # Number of write requests accepted
system.physmem.readBursts                       84209                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      74716                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                  5376960                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     12416                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   4781824                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                   5389376                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                4781824                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      194                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs            805                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                5309                       # Per bank write bursts
system.physmem.perBankRdBursts::1                4164                       # Per bank write bursts
system.physmem.perBankRdBursts::2                4421                       # Per bank write bursts
system.physmem.perBankRdBursts::3                5747                       # Per bank write bursts
system.physmem.perBankRdBursts::4                5625                       # Per bank write bursts
system.physmem.perBankRdBursts::5                4848                       # Per bank write bursts
system.physmem.perBankRdBursts::6                4889                       # Per bank write bursts
system.physmem.perBankRdBursts::7                4803                       # Per bank write bursts
system.physmem.perBankRdBursts::8                5153                       # Per bank write bursts
system.physmem.perBankRdBursts::9                5288                       # Per bank write bursts
system.physmem.perBankRdBursts::10               4847                       # Per bank write bursts
system.physmem.perBankRdBursts::11               5280                       # Per bank write bursts
system.physmem.perBankRdBursts::12               5573                       # Per bank write bursts
system.physmem.perBankRdBursts::13               6540                       # Per bank write bursts
system.physmem.perBankRdBursts::14               6055                       # Per bank write bursts
system.physmem.perBankRdBursts::15               5473                       # Per bank write bursts
system.physmem.perBankWrBursts::0                4689                       # Per bank write bursts
system.physmem.perBankWrBursts::1                3818                       # Per bank write bursts
system.physmem.perBankWrBursts::2                3922                       # Per bank write bursts
system.physmem.perBankWrBursts::3                4862                       # Per bank write bursts
system.physmem.perBankWrBursts::4                4936                       # Per bank write bursts
system.physmem.perBankWrBursts::5                4229                       # Per bank write bursts
system.physmem.perBankWrBursts::6                4848                       # Per bank write bursts
system.physmem.perBankWrBursts::7                4482                       # Per bank write bursts
system.physmem.perBankWrBursts::8                4577                       # Per bank write bursts
system.physmem.perBankWrBursts::9                4853                       # Per bank write bursts
system.physmem.perBankWrBursts::10               4451                       # Per bank write bursts
system.physmem.perBankWrBursts::11               4689                       # Per bank write bursts
system.physmem.perBankWrBursts::12               4903                       # Per bank write bursts
system.physmem.perBankWrBursts::13               5464                       # Per bank write bursts
system.physmem.perBankWrBursts::14               5149                       # Per bank write bursts
system.physmem.perBankWrBursts::15               4844                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    5136577016500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                   84209                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  74716                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     79815                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      3315                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       428                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       133                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        41                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                        39                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                        35                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                        32                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                        28                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                        29                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                       29                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                       27                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                       26                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                       25                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        7                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                       123                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                        68                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                        66                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                        62                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                        58                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                        56                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                        56                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                        55                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                        55                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                        55                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                       55                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                       55                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                       54                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                       54                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                       55                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1333                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     1661                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     3664                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     3841                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     3881                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     4252                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     4400                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     4751                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     5087                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     5589                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     5179                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     4864                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     4484                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     4396                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     3849                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     3706                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     3707                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     3671                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                       72                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                       73                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                       82                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                       83                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                       86                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                       91                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      101                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                       80                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                       73                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                       65                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                       63                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                       71                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                       81                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                       65                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                       64                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                       66                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                       60                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       54                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       28                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       26                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       24                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       14                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       12                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       16                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        8                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        7                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        37237                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      272.814244                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     163.615678                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     301.614315                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          15278     41.03%     41.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255         9118     24.49%     65.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         3769     10.12%     75.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         2135      5.73%     81.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         1492      4.01%     85.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767          936      2.51%     87.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          657      1.76%     89.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          562      1.51%     91.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         3290      8.84%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          37237                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          3726                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        22.548309                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      194.901220                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511            3723     99.92%     99.92% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-1023            1      0.03%     99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::5632-6143            1      0.03%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::9728-10239            1      0.03%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            3726                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          3726                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.052603                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.849959                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       12.299765                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3                61      1.64%      1.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7                 9      0.24%      1.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11                1      0.03%      1.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15               4      0.11%      2.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            3105     83.33%     85.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23              37      0.99%     86.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              24      0.64%     86.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             154      4.13%     91.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             145      3.89%     95.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39               6      0.16%     95.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              11      0.30%     95.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47               2      0.05%     95.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              14      0.38%     95.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55               4      0.11%     96.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               1      0.03%     96.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             119      3.19%     99.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               5      0.13%     99.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               1      0.03%     99.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79               1      0.03%     99.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               6      0.16%     99.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               4      0.11%     99.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             1      0.03%     99.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123             1      0.03%     99.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131             9      0.24%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             1      0.03%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            3726                       # Writes before turning the bus around for reads
system.physmem.totQLat                      920887750                       # Total ticks spent queuing
system.physmem.totMemAccLat                2496169000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    420075000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       10960.99                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  29710.99                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.05                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.93                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.05                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.93                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        12.74                       # Average write queue length when enqueuing
system.physmem.readRowHits                      66918                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     54576                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   79.65                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  73.04                       # Row buffer hit rate for writes
system.physmem.avgGap                     32320761.47                       # Average gap between requests
system.physmem.pageHitRate                      76.54                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     4942660463000                       # Time in different power states
system.physmem.memoryStateTime::REF      171560740000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT       23528333250                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.physmem.actEnergy::0                 135618840                       # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1                 145892880                       # Energy for activate commands per rank (pJ)
system.physmem.preEnergy::0                  73998375                       # Energy for precharge commands per rank (pJ)
system.physmem.preEnergy::1                  79604250                       # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0                310486800                       # Energy for read commands per rank (pJ)
system.physmem.readEnergy::1                344830200                       # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0               231893280                       # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1               252266400                       # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0          335572807440                       # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1          335572807440                       # Energy for refresh commands per rank (pJ)
system.physmem.actBackEnergy::0          122729524065                       # Energy for active background per rank (pJ)
system.physmem.actBackEnergy::1          123386936985                       # Energy for active background per rank (pJ)
system.physmem.preBackEnergy::0          2974992236250                       # Energy for precharge background per rank (pJ)
system.physmem.preBackEnergy::1          2974415558250                       # Energy for precharge background per rank (pJ)
system.physmem.totalEnergy::0            3434046565050                       # Total energy per rank (pJ)
system.physmem.totalEnergy::1            3434197896405                       # Total energy per rank (pJ)
system.physmem.averagePower::0             668.395092                       # Core power per rank (mW)
system.physmem.averagePower::1             668.424547                       # Core power per rank (mW)
system.membus.trans_dist::ReadReq             5119571                       # Transaction distribution
system.membus.trans_dist::ReadResp            5119569                       # Transaction distribution
system.membus.trans_dist::WriteReq              13900                       # Transaction distribution
system.membus.trans_dist::WriteResp             13900                       # Transaction distribution
system.membus.trans_dist::Writeback             96569                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq        46720                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp        46720                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             1658                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            1658                       # Transaction distribution
system.membus.trans_dist::ReadExReq            130179                       # Transaction distribution
system.membus.trans_dist::ReadExResp           130179                       # Transaction distribution
system.membus.trans_dist::MessageReq             1687                       # Transaction distribution
system.membus.trans_dist::MessageResp            1687                       # Transaction distribution
system.membus.trans_dist::BadAddressError            2                       # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave         3374                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total         3374                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      7129206                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio      3039990                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       456177                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio            4                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total     10625377                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        94957                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        94957                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total               10723708                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave         6748                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::total         6748                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave      3570760                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio      6079977                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17581760                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     27232497                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      3029312                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      3029312                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                30268557                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              291                       # Total snoops (count)
system.membus.snoop_fanout::samples            323999                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  323999    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              323999                       # Request fanout histogram
system.membus.reqLayer0.occupancy           162958500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy           314938500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             2254000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer3.occupancy           804193000                       # Layer occupancy (ticks)
system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer4.occupancy                2000                       # Layer occupancy (ticks)
system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer0.occupancy            1127000                       # Layer occupancy (ticks)
system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1664243698                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer4.occupancy           28678745                       # Layer occupancy (ticks)
system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.l2c.tags.replacements                   104648                       # number of replacements
system.l2c.tags.tagsinuse                64825.327064                       # Cycle average of tags in use
system.l2c.tags.total_refs                    3691316                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   168821                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    21.865266                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   51329.060133                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.131449                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     1735.761730                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     4946.132925                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker     0.003182                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst      379.214744                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     1982.386911                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.dtb.walker    11.162749                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst      878.696468                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data     3562.776774                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.783219                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000002                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.026486                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.075472                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.005786                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.030249                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000170                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst       0.013408                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data       0.054364                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.989156                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024        64173                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           73                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          242                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         3770                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         7642                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        52446                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024     0.979202                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 33857298                       # Number of tag accesses
system.l2c.tags.data_accesses                33857298                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker        21885                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker        11413                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             321088                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             497388                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker        12632                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         6595                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             160077                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             224317                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.dtb.walker        53710                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.itb.walker        12539                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst             370609                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data             592462                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                2284715                       # number of ReadReq hits
system.l2c.WriteReq_hits::cpu0.itb.walker            2                       # number of WriteReq hits
system.l2c.WriteReq_hits::total                     2                       # number of WriteReq hits
system.l2c.Writeback_hits::writebacks         1547592                       # number of Writeback hits
system.l2c.Writeback_hits::total              1547592                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data             126                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              49                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data              89                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 264                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            63533                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            34910                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data            62567                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               161010                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker         21885                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker         11415                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              321088                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              560921                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         12632                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          6595                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              160077                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              259227                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.dtb.walker         53710                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.itb.walker         12539                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst              370609                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data              655029                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2445727                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        21885                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker        11415                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             321088                       # number of overall hits
system.l2c.overall_hits::cpu0.data             560921                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        12632                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         6595                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             160077                       # number of overall hits
system.l2c.overall_hits::cpu1.data             259227                       # number of overall hits
system.l2c.overall_hits::cpu2.dtb.walker        53710                       # number of overall hits
system.l2c.overall_hits::cpu2.itb.walker        12539                       # number of overall hits
system.l2c.overall_hits::cpu2.inst             370609                       # number of overall hits
system.l2c.overall_hits::cpu2.data             655029                       # number of overall hits
system.l2c.overall_hits::total                2445727                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.itb.walker            4                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst             7427                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data            17501                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             2032                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             4808                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.dtb.walker           42                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst             5670                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data            10484                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                47969                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data           766                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data           250                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data           384                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              1400                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          69535                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          28299                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data          32603                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             130437                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.itb.walker            4                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              7427                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             87036                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              2032                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             33107                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.dtb.walker           42                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst              5670                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data             43087                       # number of demand (read+write) misses
system.l2c.demand_misses::total                178406                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.itb.walker            4                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             7427                       # number of overall misses
system.l2c.overall_misses::cpu0.data            87036                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             2032                       # number of overall misses
system.l2c.overall_misses::cpu1.data            33107                       # number of overall misses
system.l2c.overall_misses::cpu2.dtb.walker           42                       # number of overall misses
system.l2c.overall_misses::cpu2.inst             5670                       # number of overall misses
system.l2c.overall_misses::cpu2.data            43087                       # number of overall misses
system.l2c.overall_misses::total               178406                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu1.itb.walker        74500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    150329750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    367685500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.dtb.walker      3647250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst    442043250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data    814497000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     1778277250                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      2652136                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data      4441809                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total      7093945                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   1942003664                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data   2343046915                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   4285050579                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker        74500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    150329750                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   2309689164                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.dtb.walker      3647250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst    442043250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data   3157543915                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      6063327829                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker        74500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    150329750                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   2309689164                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.dtb.walker      3647250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst    442043250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data   3157543915                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     6063327829                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker        21885                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker        11417                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         328515                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         514889                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker        12632                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         6596                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         162109                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         229125                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.dtb.walker        53752                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.itb.walker        12539                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst         376279                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data         602946                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2332684                       # number of ReadReq accesses(hits+misses)
system.l2c.WriteReq_accesses::cpu0.itb.walker            2                       # number of WriteReq accesses(hits+misses)
system.l2c.WriteReq_accesses::total                 2                       # number of WriteReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks      1547592                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total          1547592                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data          892                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data          299                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data          473                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            1664                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       133068                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        63209                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data        95170                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           291447                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        21885                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker        11419                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          328515                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          647957                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        12632                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         6596                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          162109                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          292334                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.dtb.walker        53752                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.itb.walker        12539                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst          376279                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data          698116                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2624133                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        21885                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker        11419                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         328515                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         647957                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        12632                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         6596                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         162109                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         292334                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.dtb.walker        53752                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.itb.walker        12539                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst         376279                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data         698116                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2624133                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000350                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.022608                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.033990                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.000152                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.012535                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.020984                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.000781                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst      0.015069                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data      0.017388                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.020564                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.858744                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.836120                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data     0.811839                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.841346                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.522552                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.447705                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data     0.342576                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.447550                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000350                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.022608                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.134324                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.000152                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.012535                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.113251                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.dtb.walker     0.000781                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.015069                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.061719                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.067987                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000350                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.022608                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.134324                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.000152                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.012535                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.113251                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.dtb.walker     0.000781                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.015069                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.061719                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.067987                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker        74500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 73981.176181                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 76473.689684                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 86839.285714                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 77961.772487                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data 77689.526898                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 37071.384644                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 10608.544000                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 11567.210938                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  5067.103571                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68624.462490                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 71865.991320                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 32851.495964                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker        74500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 73981.176181                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 69764.375026                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 86839.285714                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 77961.772487                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 73282.983615                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 33986.120585                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker        74500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 73981.176181                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 69764.375026                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 86839.285714                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 77961.772487                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 73282.983615                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 33986.120585                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               96569                       # number of writebacks
system.l2c.writebacks::total                    96569                       # number of writebacks
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         2032                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         4808                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker           42                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.inst         5670                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.data        10484                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           23037                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data          250                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data          384                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total          634                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        28299                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data        32603                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         60902                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         2032                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        33107                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.dtb.walker           42                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst         5670                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data        43087                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total            83939                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         2032                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        33107                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.dtb.walker           42                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst         5670                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data        43087                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total           83939                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker        62500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    124575250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    307568500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker      3127250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst    371081250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data    683718500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   1490133250                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      2500500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data      3860881                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total      6361381                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1578314336                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   1925294585                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   3503608921                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker        62500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    124575250                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   1885882836                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker      3127250                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst    371081250                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data   2609013085                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   4993742171                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker        62500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    124575250                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   1885882836                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker      3127250                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst    371081250                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data   2609013085                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   4993742171                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  27997217000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data  30232738500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total  58229955500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    537806500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    646167500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   1183974000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data  28535023500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data  30878906000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  59413929500                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.000152                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.012535                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.020984                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.000781                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.015069                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.017388                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.009876                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.836120                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.811839                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.381010                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.447705                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.342576                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.208964                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.000152                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.012535                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.113251                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.000781                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.015069                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.061719                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.031987                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.000152                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.012535                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.113251                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.000781                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.015069                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.061719                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.031987                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61306.717520                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63970.153910                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 74458.333333                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 65446.428571                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 65215.423502                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 64684.344750                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        10002                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10054.377604                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10033.723975                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55772.795364                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 59052.681808                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 57528.634872                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61306.717520                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56963.265654                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 74458.333333                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 65446.428571                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 60552.210295                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 59492.514457                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61306.717520                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56963.265654                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 74458.333333                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 65446.428571                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 60552.210295                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 59492.514457                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.iocache.tags.replacements                47569                       # number of replacements
system.iocache.tags.tagsinuse                0.092434                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                47585                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         5000571333009                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.092434                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide     0.005777                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.005777                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               428616                       # Number of tag accesses
system.iocache.tags.data_accesses              428616                       # Number of data accesses
system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq hits
system.iocache.WriteInvalidateReq_hits::total        46720                       # number of WriteInvalidateReq hits
system.iocache.ReadReq_misses::pc.south_bridge.ide          904                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              904                       # number of ReadReq misses
system.iocache.demand_misses::pc.south_bridge.ide          904                       # number of demand (read+write) misses
system.iocache.demand_misses::total               904                       # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide          904                       # number of overall misses
system.iocache.overall_misses::total              904                       # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    131931527                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total    131931527                       # number of ReadReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide    131931527                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total    131931527                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide    131931527                       # number of overall miss cycles
system.iocache.overall_miss_latency::total    131931527                       # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide          904                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            904                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total        46720                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide          904                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             904                       # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide          904                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            904                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 145941.954646                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 145941.954646                       # average ReadReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 145941.954646                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 145941.954646                       # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 145941.954646                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 145941.954646                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs           471                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                   39                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    12.076923                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                      46720                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          734                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          734                       # number of ReadReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide          734                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          734                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide          734                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          734                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     93740027                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     93740027                       # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide   1329860248                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total   1329860248                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     93740027                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     93740027                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     93740027                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     93740027                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide     0.811947                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total     0.811947                       # mshr miss rate for ReadReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide     0.811947                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total     0.811947                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide     0.811947                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total     0.811947                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 127711.208447                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 127711.208447                       # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide          inf                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 127711.208447                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 127711.208447                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 127711.208447                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 127711.208447                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs           31                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
system.toL2Bus.trans_dist::ReadReq            7431790                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           7431262                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             13902                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            13902                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback          1547592                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq        22056                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq            1664                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp           1664                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           291447                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          291447                       # Transaction distribution
system.toL2Bus.trans_dist::BadAddressError            2                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1733856                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     14997138                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side        72735                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side       201275                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              17005004                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     55482624                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    213567857                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side       271280                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side       749120                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              270070881                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                           66934                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          4248687                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            3.011209                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.105278                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::3                4201063     98.88%     98.88% # Request fanout histogram
system.toL2Bus.snoop_fanout::4                  47624      1.12%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              3                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              4                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            4248687                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         5247340592                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           936000                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        2425844552                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        4872344858                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy          24091410                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy          80681637                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq              3554542                       # Transaction distribution
system.iobus.trans_dist::ReadResp             3554542                       # Transaction distribution
system.iobus.trans_dist::WriteReq               57685                       # Transaction distribution
system.iobus.trans_dist::WriteResp              33021                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp        24664                       # Transaction distribution
system.iobus.trans_dist::MessageReq              1687                       # Transaction distribution
system.iobus.trans_dist::MessageResp             1687                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11134                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1364                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           86                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           54                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio      7085054                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1126                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio          170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27782                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total      7129206                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95248                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95248                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3374                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3374                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                 7227828                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6712                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf          221                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          682                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           43                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           27                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio      3542527                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2252                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio           85                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio        13891                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total      3570760                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027776                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027776                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6748                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6748                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  6605284                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy              2693792                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                27000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 6000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy              4846000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                 4000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy               758000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                25000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                15000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy                18000                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy            142528000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy              333000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy              134000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy            10264000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy           199614020                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy             1032000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy           303080000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            27344255                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer2.occupancy             1127000                       # Layer occupancy (ticks)
system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
system.cpu0.apic_clk_domain.clock                8000                       # Clock period in ticks
system.cpu0.numCycles                       818767223                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                   72040073                       # Number of instructions committed
system.cpu0.committedOps                    146798683                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            134677148                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
system.cpu0.num_func_calls                     957492                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     14259376                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   134677148                       # number of integer instructions
system.cpu0.num_fp_insts                            0                       # number of float instructions
system.cpu0.num_int_register_reads          247199145                       # number of times the integer registers were read
system.cpu0.num_int_register_writes         115729599                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads            83822967                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes           55940767                       # number of times the CC registers were written
system.cpu0.num_mem_refs                     13836630                       # number of memory refs
system.cpu0.num_load_insts                   10218166                       # Number of load instructions
system.cpu0.num_store_insts                   3618464                       # Number of store instructions
system.cpu0.num_idle_cycles              776544159.837226                       # Number of idle cycles
system.cpu0.num_busy_cycles              42223063.162775                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.051569                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.948431                       # Percentage of idle cycles
system.cpu0.Branches                         15573109                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                95028      0.06%      0.06% # Class of executed instruction
system.cpu0.op_class::IntAlu                132757091     90.43%     90.50% # Class of executed instruction
system.cpu0.op_class::IntMult                   59427      0.04%     90.54% # Class of executed instruction
system.cpu0.op_class::IntDiv                    51115      0.03%     90.57% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc                 0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     90.57% # Class of executed instruction
system.cpu0.op_class::MemRead                10218166      6.96%     97.54% # Class of executed instruction
system.cpu0.op_class::MemWrite                3618464      2.46%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 146799291                       # Class of executed instruction
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu0.icache.tags.replacements           866413                       # number of replacements
system.cpu0.icache.tags.tagsinuse          510.840210                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          130156159                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs           866925                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs           150.135432                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle     149014386250                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   138.994027                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst   266.522548                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst   105.323634                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.271473                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.520552                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst     0.205710                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.997735                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           84                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          133                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          295                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        131912504                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       131912504                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     87639896                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst     39531787                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst      2984476                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      130156159                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     87639896                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst     39531787                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst      2984476                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       130156159                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     87639896                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst     39531787                       # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst      2984476                       # number of overall hits
system.cpu0.icache.overall_hits::total      130156159                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       328528                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst       162109                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst       398768                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       889405                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       328528                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst       162109                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst       398768                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        889405                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       328528                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst       162109                       # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst       398768                       # number of overall misses
system.cpu0.icache.overall_misses::total       889405                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   2245844750                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   5606326194                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total   7852170944                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst   2245844750                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst   5606326194                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total   7852170944                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst   2245844750                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst   5606326194                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total   7852170944                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     87968424                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst     39693896                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst      3383244                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    131045564                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     87968424                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst     39693896                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst      3383244                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    131045564                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     87968424                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst     39693896                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst      3383244                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    131045564                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.003735                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.004084                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.117866                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.006787                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.003735                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.004084                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst     0.117866                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.006787                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.003735                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.004084                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst     0.117866                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.006787                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13853.917734                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14059.117567                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  8828.566226                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13853.917734                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14059.117567                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  8828.566226                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13853.917734                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14059.117567                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  8828.566226                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         4938                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              262                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    18.847328                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        22465                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        22465                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu2.inst        22465                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        22465                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu2.inst        22465                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        22465                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       162109                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       376303                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       538412                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst       162109                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst       376303                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       538412                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst       162109                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst       376303                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       538412                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1920905250                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   4627637688                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   6548542938                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1920905250                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   4627637688                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   6548542938                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1920905250                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   4627637688                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   6548542938                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.004084                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.111225                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.004109                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.004084                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.111225                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.004109                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.004084                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.111225                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.004109                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11849.467025                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12297.636979                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12162.698710                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11849.467025                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12297.636979                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12162.698710                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11849.467025                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12297.636979                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12162.698710                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements          1637866                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.999423                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           19673585                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          1638378                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            12.007965                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle          7549500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   126.297276                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data   280.648639                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data   105.053508                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.246674                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.548142                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data     0.205183                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999999                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          270                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          221                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           21                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         88453877                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        88453877                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data      5010669                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data      2623262                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data      3898583                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       11532514                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3480346                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data      1810737                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data      2788314                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       8079397                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data        20263                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data        10587                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu2.data        29029                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total        59879                       # number of SoftPFReq hits
system.cpu0.dcache.demand_hits::cpu0.data      8491015                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data      4433999                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data      6686897                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        19611911                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data      8511278                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data      4444586                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data      6715926                       # number of overall hits
system.cpu0.dcache.overall_hits::total       19671790                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       362952                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data       164891                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data       772037                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      1299880                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       133960                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data        65129                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data       126515                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       325604                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       151937                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data        64294                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu2.data       190363                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       406594                       # number of SoftPFReq misses
system.cpu0.dcache.demand_misses::cpu0.data       496912                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data       230020                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data       898552                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       1625484                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       648849                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data       294314                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data      1088915                       # number of overall misses
system.cpu0.dcache.overall_misses::total      2032078                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2296036750                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  11919855793                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  14215892543                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   2581335822                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data   3855689962                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total   6437025784                       # number of WriteReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data   4877372572                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data  15775545755                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  20652918327                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data   4877372572                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data  15775545755                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  20652918327                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      5373621                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data      2788153                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data      4670620                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     12832394                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      3614306                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data      1875866                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data      2914829                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      8405001                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       172200                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data        74881                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       219392                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       466473                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data      8987927                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data      4664019                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data      7585449                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     21237395                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data      9160127                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data      4738900                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data      7804841                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     21703868                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.067543                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.059140                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.165296                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.101297                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.037064                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.034719                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.043404                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.038739                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.882329                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.858616                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.867684                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.871635                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.055287                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.049318                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data     0.118457                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.076539                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.070834                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.062106                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data     0.139518                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.093627                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13924.572900                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15439.487736                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 10936.311462                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39634.200157                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30476.148773                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 19769.492340                       # average WriteReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21204.123867                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17556.630841                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 12705.703856                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16572.003275                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 14487.398700                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 10163.447627                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs       128010                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs            27734                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs     4.615634                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks      1547592                       # number of writebacks
system.cpu0.dcache.writebacks::total          1547592                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data           59                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       355847                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       355906                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         1633                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data        30941                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total        32574                       # number of WriteReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data         1692                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data       386788                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total       388480                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data         1692                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data       386788                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total       388480                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       164832                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       416190                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       581022                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        63496                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        95574                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       159070                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        64293                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       186824                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       251117                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data       228328                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data       511764                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       740092                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data       292621                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data       698588                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       991209                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   1964999750                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   5660700319                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   7625700069                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   2364352650                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   3101755528                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5466108178                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    883443250                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   2757990753                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   3641434003                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   4329352400                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   8762455847                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  13091808247                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   5212795650                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  11520446600                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  16733242250                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  30452050000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  32985877000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  63437927000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    577982500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    687759500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1265742000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  31030032500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  33673636500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  64703669000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.059119                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.089108                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.045278                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.033849                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.032789                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018926                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.858602                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.851553                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.538331                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.048955                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.067467                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.034849                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.061749                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.089507                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.045670                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11921.227371                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13601.240585                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13124.632233                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 37236.245590                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32453.967899                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34362.910530                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13740.893254                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14762.507777                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14500.945786                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18961.110333                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17122.063777                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17689.433539                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17814.154316                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16491.045652                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16881.648825                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.numCycles                      2606022983                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                   35939339                       # Number of instructions committed
system.cpu1.committedOps                     69774923                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses             64844483                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
system.cpu1.num_func_calls                     499287                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      6580388                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                    64844483                       # number of integer instructions
system.cpu1.num_fp_insts                            0                       # number of float instructions
system.cpu1.num_int_register_reads          120226227                       # number of times the integer registers were read
system.cpu1.num_int_register_writes          55826198                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads            36586824                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes           27309791                       # number of times the CC registers were written
system.cpu1.num_mem_refs                      4927873                       # number of memory refs
system.cpu1.num_load_insts                    3050339                       # Number of load instructions
system.cpu1.num_store_insts                   1877534                       # Number of store instructions
system.cpu1.num_idle_cycles              2477290986.248718                       # Number of idle cycles
system.cpu1.num_busy_cycles              128731996.751282                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.049398                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.950602                       # Percentage of idle cycles
system.cpu1.Branches                          7259898                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                35461      0.05%      0.05% # Class of executed instruction
system.cpu1.op_class::IntAlu                 64754697     92.80%     92.86% # Class of executed instruction
system.cpu1.op_class::IntMult                   31756      0.05%     92.90% # Class of executed instruction
system.cpu1.op_class::IntDiv                    25505      0.04%     92.94% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     92.94% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     92.94% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     92.94% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     92.94% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     92.94% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     92.94% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     92.94% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     92.94% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     92.94% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     92.94% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     92.94% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     92.94% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     92.94% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     92.94% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     92.94% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     92.94% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     92.94% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     92.94% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     92.94% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     92.94% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     92.94% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     92.94% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc                 0      0.00%     92.94% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     92.94% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     92.94% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     92.94% # Class of executed instruction
system.cpu1.op_class::MemRead                 3050339      4.37%     97.31% # Class of executed instruction
system.cpu1.op_class::MemWrite                1877534      2.69%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                  69775292                       # Class of executed instruction
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu2.branchPred.lookups               29000272                       # Number of BP lookups
system.cpu2.branchPred.condPredicted         29000272                       # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect           311632                       # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups            26370508                       # Number of BTB lookups
system.cpu2.branchPred.BTBHits               25723888                       # Number of BTB hits
system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct            97.547943                       # BTB Hit Percentage
system.cpu2.branchPred.usedRAS                 573459                       # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect             63282                       # Number of incorrect RAS predictions.
system.cpu2.numCycles                       153009050                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles          10521285                       # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts                     142969715                       # Number of instructions fetch has processed
system.cpu2.fetch.Branches                   29000272                       # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches          26297347                       # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles                    141031314                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles                 650011                       # Number of cycles fetch has spent squashing
system.cpu2.fetch.TlbCycles                     92984                       # Number of cycles fetch has spent waiting for tlb
system.cpu2.fetch.MiscStallCycles                4408                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.PendingDrainCycles             9006                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu2.fetch.PendingTrapStallCycles        47091                       # Number of stall cycles due to pending traps
system.cpu2.fetch.PendingQuiesceStallCycles         2529                       # Number of stall cycles due to pending quiesce instructions
system.cpu2.fetch.IcacheWaitRetryStallCycles          579                       # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines                  3383247                       # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes               163781                       # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.ItlbSquashes                   3234                       # Number of outstanding ITLB misses that were squashed
system.cpu2.fetch.rateDist::samples         152033550                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean             1.852472                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev            3.031588                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0                97124192     63.88%     63.88% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1                  819598      0.54%     64.42% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2                23594190     15.52%     79.94% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3                  577537      0.38%     80.32% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4                  790978      0.52%     80.84% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5                  823076      0.54%     81.38% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6                  560198      0.37%     81.75% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7                  693420      0.46%     82.21% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8                27050361     17.79%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total           152033550                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate                 0.189533                       # Number of branch fetches per cycle
system.cpu2.fetch.rate                       0.934387                       # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles                 9712542                       # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles             92934302                       # Number of cycles decode is blocked
system.cpu2.decode.RunCycles                 23280371                       # Number of cycles decode is running
system.cpu2.decode.UnblockCycles              5017317                       # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles                325657                       # Number of cycles decode is squashing
system.cpu2.decode.DecodedInsts             278875678                       # Number of instructions handled by decode
system.cpu2.rename.SquashCycles                325657                       # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles                11857648                       # Number of cycles rename is idle
system.cpu2.rename.BlockCycles               75889768                       # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles       4419845                       # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles                 25919685                       # Number of cycles rename is running
system.cpu2.rename.UnblockCycles             12857653                       # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts             277706863                       # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents               221466                       # Number of times rename has blocked due to ROB full
system.cpu2.rename.IQFullEvents               5888159                       # Number of times rename has blocked due to IQ full
system.cpu2.rename.LQFullEvents                 42783                       # Number of times rename has blocked due to LQ full
system.cpu2.rename.SQFullEvents               4808995                       # Number of times rename has blocked due to SQ full
system.cpu2.rename.RenamedOperands          331833488                       # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups            605194394                       # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups       371618079                       # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups               36                       # Number of floating rename lookups
system.cpu2.rename.CommittedMaps            320107208                       # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps                11726280                       # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts            151218                       # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts        152719                       # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts                 24489304                       # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads             6338862                       # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores            3553328                       # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads           367719                       # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores          319565                       # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded                 275826769                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded             413139                       # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued                273878584                       # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued            98557                       # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined        8364175                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined     12972199                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved         61453                       # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples    152033550                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean        1.801435                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev       2.398557                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0           89826062     59.08%     59.08% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1            5325607      3.50%     62.59% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2            3883778      2.55%     65.14% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3            3618974      2.38%     67.52% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4           22318323     14.68%     82.20% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5            2568868      1.69%     83.89% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6           23837030     15.68%     99.57% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7             450577      0.30%     99.87% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8             204331      0.13%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total      152033550                       # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu                1765790     86.71%     86.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult                     6      0.00%     86.71% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv                     95      0.00%     86.72% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     86.72% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     86.72% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     86.72% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult                   0      0.00%     86.72% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     86.72% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     86.72% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     86.72% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     86.72% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     86.72% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     86.72% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     86.72% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     86.72% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult                    0      0.00%     86.72% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     86.72% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift                   0      0.00%     86.72% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     86.72% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     86.72% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     86.72% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     86.72% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     86.72% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     86.72% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     86.72% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     86.72% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     86.72% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     86.72% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     86.72% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead                213483     10.48%     97.20% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite                57008      2.80%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass            75484      0.03%      0.03% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu            263736524     96.30%     96.32% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult               54819      0.02%     96.34% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv                47031      0.02%     96.36% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     96.36% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     96.36% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     96.36% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     96.36% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     96.36% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     96.36% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     96.36% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     96.36% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     96.36% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     96.36% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     96.36% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     96.36% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     96.36% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     96.36% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     96.36% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     96.36% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     96.36% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     96.36% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     96.36% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     96.36% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     96.36% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     96.36% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     96.36% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     96.36% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.36% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     96.36% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead             6686249      2.44%     98.80% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite            3278477      1.20%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total             273878584                       # Type of FU issued
system.cpu2.iq.rate                          1.789950                       # Inst issue rate
system.cpu2.iq.fu_busy_cnt                    2036382                       # FU busy when requested
system.cpu2.iq.fu_busy_rate                  0.007435                       # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads         701925596                       # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes        284608270                       # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses    272313229                       # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads                 61                       # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes                68                       # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses             275839453                       # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses                     29                       # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads          685704                       # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads      1161006                       # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses         6104                       # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation         4803                       # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores       634153                       # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads       755552                       # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked        21313                       # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles                325657                       # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles               70767994                       # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles              1741893                       # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts          276239908                       # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts            40444                       # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts              6338884                       # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts             3553328                       # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts            236248                       # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents                194416                       # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents              1250638                       # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents          4803                       # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect        177191                       # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect       184398                       # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts              361589                       # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts            273320009                       # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts              6554812                       # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts           510377                       # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
system.cpu2.iew.exec_nop                            0                       # number of nop insts executed
system.cpu2.iew.exec_refs                     9748811                       # number of memory reference insts executed
system.cpu2.iew.exec_branches                27755327                       # Number of branches executed
system.cpu2.iew.exec_stores                   3193999                       # Number of stores executed
system.cpu2.iew.exec_rate                    1.786300                       # Inst execution rate
system.cpu2.iew.wb_sent                     273134840                       # cumulative count of insts sent to commit
system.cpu2.iew.wb_count                    272313245                       # cumulative count of insts written-back
system.cpu2.iew.wb_producers                212432379                       # num instructions producing a value
system.cpu2.iew.wb_consumers                348339663                       # num instructions consuming a value
system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate                      1.779720                       # insts written-back per cycle
system.cpu2.iew.wb_fanout                    0.609843                       # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitSquashedInsts        8691419                       # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls         351686                       # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts           314047                       # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples    150733678                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean     1.774964                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev     2.652543                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0     93656646     62.13%     62.13% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1      4148238      2.75%     64.89% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2      1235888      0.82%     65.71% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3     24514613     16.26%     81.97% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4      1002757      0.67%     82.63% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5       665638      0.44%     83.08% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6       467092      0.31%     83.39% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7     23101150     15.33%     98.71% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8      1941656      1.29%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total    150733678                       # Number of insts commited each cycle
system.cpu2.commit.committedInsts           135526613                       # Number of instructions committed
system.cpu2.commit.committedOps             267546921                       # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu2.commit.refs                       8097053                       # Number of memory references committed
system.cpu2.commit.loads                      5177878                       # Number of loads committed
system.cpu2.commit.membars                     162019                       # Number of memory barriers committed
system.cpu2.commit.branches                  27358633                       # Number of branches committed
system.cpu2.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu2.commit.int_insts                244351653                       # Number of committed integer instructions.
system.cpu2.commit.function_calls              425746                       # Number of function calls committed.
system.cpu2.commit.op_class_0::No_OpClass        44568      0.02%      0.02% # Class of committed instruction
system.cpu2.commit.op_class_0::IntAlu       259307312     96.92%     96.94% # Class of committed instruction
system.cpu2.commit.op_class_0::IntMult          52493      0.02%     96.96% # Class of committed instruction
system.cpu2.commit.op_class_0::IntDiv           45495      0.02%     96.97% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     96.97% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     96.97% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     96.97% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMult            0      0.00%     96.97% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     96.97% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     96.97% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     96.97% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     96.97% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     96.97% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     96.97% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     96.97% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     96.97% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMult             0      0.00%     96.97% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     96.97% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShift            0      0.00%     96.97% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     96.97% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     96.97% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     96.97% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     96.97% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     96.97% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     96.97% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     96.97% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     96.97% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     96.97% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     96.97% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     96.97% # Class of committed instruction
system.cpu2.commit.op_class_0::MemRead        5177878      1.94%     98.91% # Class of committed instruction
system.cpu2.commit.op_class_0::MemWrite       2919175      1.09%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::total        267546921                       # Class of committed instruction
system.cpu2.commit.bw_lim_events              1941656                       # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu2.rob.rob_reads                   425004820                       # The number of ROB reads
system.cpu2.rob.rob_writes                  553782312                       # The number of ROB writes
system.cpu2.timesIdled                         113608                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles                         975500                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles                  4910108147                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts                  135526613                       # Number of Instructions Simulated
system.cpu2.committedOps                    267546921                       # Number of Ops (including micro ops) Simulated
system.cpu2.cpi                              1.128996                       # CPI: Cycles Per Instruction
system.cpu2.cpi_total                        1.128996                       # CPI: Total CPI of All Threads
system.cpu2.ipc                              0.885742                       # IPC: Instructions Per Cycle
system.cpu2.ipc_total                        0.885742                       # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads               363608614                       # number of integer regfile reads
system.cpu2.int_regfile_writes              218247524                       # number of integer regfile writes
system.cpu2.fp_regfile_reads                    72984                       # number of floating regfile reads
system.cpu2.fp_regfile_writes                   72968                       # number of floating regfile writes
system.cpu2.cc_regfile_reads                138904210                       # number of cc regfile reads
system.cpu2.cc_regfile_writes               106846664                       # number of cc regfile writes
system.cpu2.misc_regfile_reads               88678814                       # number of misc regfile reads
system.cpu2.misc_regfile_writes                129757                       # number of misc regfile writes
system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------