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gem5/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt

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x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
---------- Begin Simulation Statistics ----------
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
sim_seconds 5.136081 # Number of seconds simulated
sim_ticks 5136081138000 # Number of ticks simulated
final_tick 5136081138000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
host_inst_rate 275445 # Simulator instruction rate (inst/s)
host_op_rate 547622 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 5813086840 # Simulator tick rate (ticks/s)
host_mem_usage 1006240 # Number of bytes of host memory used
host_seconds 883.54 # Real time elapsed on the host
sim_insts 243366027 # Number of instructions simulated
sim_ops 483844707 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.bytes_read::cpu0.inst 488576 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 5525632 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 145728 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 1937472 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker 1792 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst 336128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 2922880 # Number of bytes read from this memory
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.bytes_read::total 11386880 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 488576 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 145728 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 336128 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 970432 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 9156352 # Number of bytes written to this memory
system.physmem.bytes_written::total 9156352 # Number of bytes written to this memory
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.num_reads::cpu0.inst 7634 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 86338 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 2277 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 30273 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker 28 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst 5252 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 45670 # Number of read requests responded to by this memory
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.num_reads::total 177920 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 143068 # Number of write requests responded to by this memory
system.physmem.num_writes::total 143068 # Number of write requests responded to by this memory
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.bw_read::cpu0.inst 95126 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 1075846 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 28373 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 377228 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker 349 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst 65444 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data 569088 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::pc.south_bridge.ide 5520 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2217037 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 95126 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 28373 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst 65444 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 188944 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1782751 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1782751 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1782751 # Total bandwidth to/from this memory (bytes/s)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.bw_total::cpu0.inst 95126 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 1075846 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 28373 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 377228 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker 349 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst 65444 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data 569088 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide 5520 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 3999787 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 83943 # Number of read requests accepted
system.physmem.writeReqs 110041 # Number of write requests accepted
system.physmem.readBursts 83943 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 110041 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 5367872 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 4480 # Total number of bytes read from write queue
system.physmem.bytesWritten 6959552 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 5372352 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 7042624 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 70 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 1298 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 825 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 5657 # Per bank write bursts
system.physmem.perBankRdBursts::1 4325 # Per bank write bursts
system.physmem.perBankRdBursts::2 4452 # Per bank write bursts
system.physmem.perBankRdBursts::3 6002 # Per bank write bursts
system.physmem.perBankRdBursts::4 5499 # Per bank write bursts
system.physmem.perBankRdBursts::5 4854 # Per bank write bursts
system.physmem.perBankRdBursts::6 4847 # Per bank write bursts
system.physmem.perBankRdBursts::7 4597 # Per bank write bursts
system.physmem.perBankRdBursts::8 5338 # Per bank write bursts
system.physmem.perBankRdBursts::9 5444 # Per bank write bursts
system.physmem.perBankRdBursts::10 5075 # Per bank write bursts
system.physmem.perBankRdBursts::11 5197 # Per bank write bursts
system.physmem.perBankRdBursts::12 5244 # Per bank write bursts
system.physmem.perBankRdBursts::13 6205 # Per bank write bursts
system.physmem.perBankRdBursts::14 5705 # Per bank write bursts
system.physmem.perBankRdBursts::15 5432 # Per bank write bursts
system.physmem.perBankWrBursts::0 8070 # Per bank write bursts
system.physmem.perBankWrBursts::1 6584 # Per bank write bursts
system.physmem.perBankWrBursts::2 6149 # Per bank write bursts
system.physmem.perBankWrBursts::3 7200 # Per bank write bursts
system.physmem.perBankWrBursts::4 7057 # Per bank write bursts
system.physmem.perBankWrBursts::5 6223 # Per bank write bursts
system.physmem.perBankWrBursts::6 6693 # Per bank write bursts
system.physmem.perBankWrBursts::7 6492 # Per bank write bursts
system.physmem.perBankWrBursts::8 6300 # Per bank write bursts
system.physmem.perBankWrBursts::9 6374 # Per bank write bursts
system.physmem.perBankWrBursts::10 7150 # Per bank write bursts
system.physmem.perBankWrBursts::11 7064 # Per bank write bursts
system.physmem.perBankWrBursts::12 7000 # Per bank write bursts
system.physmem.perBankWrBursts::13 7706 # Per bank write bursts
system.physmem.perBankWrBursts::14 6569 # Per bank write bursts
system.physmem.perBankWrBursts::15 6112 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.totGap 5132269646500 # Total gap between requests
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.readPktSize::6 83943 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.writePktSize::6 110041 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 78296 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 4371 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 740 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 145 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 41 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 33 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 28 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 27 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 26 # What read queue length does an incoming req see
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.wrQLenPdf::0 125 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 66 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 64 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 60 # What write queue length does an incoming req see
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.wrQLenPdf::4 57 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 55 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 55 # What write queue length does an incoming req see
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.wrQLenPdf::7 55 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 54 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 54 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 54 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 53 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 53 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 54 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 56 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 1636 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 3134 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 5343 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 6137 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 6435 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 7094 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 7393 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 8076 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 7821 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 8157 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 7462 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 7092 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 6097 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 5684 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 4696 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 4427 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 4367 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 4254 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 231 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 214 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 206 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 179 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 163 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 154 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 156 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 155 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 138 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 126 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 104 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 89 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 93 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 92 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 71 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 71 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 69 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 62 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 55 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 40 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 28 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 14 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.wrQLenPdf::58 1 # What write queue length does an incoming req see
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.bytesPerActivate::samples 39516 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 311.960320 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 180.025881 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 337.744102 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 15369 38.89% 38.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 9220 23.33% 62.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 3764 9.53% 71.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 2091 5.29% 77.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 1514 3.83% 80.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 970 2.45% 83.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 639 1.62% 84.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 601 1.52% 86.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 5348 13.53% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 39516 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 4123 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 20.342712 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 185.525630 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511 4120 99.93% 99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-1535 1 0.02% 99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6144-6655 1 0.02% 99.98% # Reads before turning the bus around for writes
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.rdPerTurnAround::9728-10239 1 0.02% 100.00% # Reads before turning the bus around for writes
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.rdPerTurnAround::total 4123 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 4123 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 26.374727 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 20.353037 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 26.922743 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-7 71 1.72% 1.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-15 7 0.17% 1.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-23 3190 77.37% 79.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-31 194 4.71% 83.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-39 131 3.18% 87.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-47 35 0.85% 87.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-55 132 3.20% 91.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-63 15 0.36% 91.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-71 23 0.56% 92.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-79 42 1.02% 93.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-87 60 1.46% 94.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-95 20 0.49% 95.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-103 93 2.26% 97.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-111 8 0.19% 97.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-119 26 0.63% 98.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-127 5 0.12% 98.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-135 22 0.53% 98.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-143 8 0.19% 99.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-151 11 0.27% 99.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-159 2 0.05% 99.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-167 5 0.12% 99.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-175 3 0.07% 99.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-183 3 0.07% 99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-191 3 0.07% 99.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-199 2 0.05% 99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-207 5 0.12% 99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::216-223 4 0.10% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-231 1 0.02% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-247 1 0.02% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 4123 # Writes before turning the bus around for reads
system.physmem.totQLat 931934250 # Total ticks spent queuing
system.physmem.totMemAccLat 2504553000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 419365000 # Total ticks spent in databus transfers
system.physmem.avgQLat 11111.25 # Average queueing delay per DRAM burst
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.avgMemAccLat 29861.25 # Average memory access latency per DRAM burst
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.physmem.avgRdBW 1.05 # Average DRAM read bandwidth in MiByte/s
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.avgWrBW 1.36 # Average achieved write bandwidth in MiByte/s
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.physmem.avgRdBWSys 1.05 # Average system read bandwidth in MiByte/s
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.avgWrBWSys 1.37 # Average system write bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.physmem.busUtil 0.02 # Data bus utilization in percentage
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.avgWrQLen 12.18 # Average write queue length when enqueuing
system.physmem.readRowHits 66618 # Number of row buffer hits during reads
system.physmem.writeRowHits 86482 # Number of row buffer hits during writes
system.physmem.readRowHitRate 79.43 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 79.53 # Row buffer hit rate for writes
system.physmem.avgGap 26457180.21 # Average gap between requests
system.physmem.pageHitRate 79.48 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 145862640 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 79389750 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 313817400 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 352952640 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 250172869440 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 94379716215 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 2235135422250 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 2580580030335 # Total energy per rank (pJ)
system.physmem_0.averagePower 667.988936 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 3685687946000 # Time in different power states
system.physmem_0.memoryStateTime::REF 127900240000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 17077044750 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 152878320 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 83263125 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 340392000 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 351702000 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 250172869440 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 95036922225 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 2235169487250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 2581307514360 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.001289 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 3684742447500 # Time in different power states
system.physmem_1.memoryStateTime::REF 127900240000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 18039817250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.numCycles 818737889 # number of cpu cycles simulated
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.committedInsts 71815441 # Number of instructions committed
system.cpu0.committedOps 146372002 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 134241940 # Number of integer alu accesses
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.num_func_calls 946109 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 14229680 # number of instructions that are conditional controls
system.cpu0.num_int_insts 134241940 # number of integer instructions
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu0.num_fp_insts 0 # number of float instructions
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.num_int_register_reads 246318200 # number of times the integer registers were read
system.cpu0.num_int_register_writes 115340862 # number of times the integer registers were written
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.num_cc_register_reads 83590760 # number of times the CC registers were read
system.cpu0.num_cc_register_writes 55777582 # number of times the CC registers were written
system.cpu0.num_mem_refs 13734986 # number of memory refs
system.cpu0.num_load_insts 10122778 # Number of load instructions
system.cpu0.num_store_insts 3612208 # Number of store instructions
system.cpu0.num_idle_cycles 777021055.677311 # Number of idle cycles
system.cpu0.num_busy_cycles 41716833.322689 # Number of busy cycles
system.cpu0.not_idle_fraction 0.050953 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.949047 # Percentage of idle cycles
system.cpu0.Branches 15525387 # Number of branches fetched
system.cpu0.op_class::No_OpClass 95218 0.07% 0.07% # Class of executed instruction
system.cpu0.op_class::IntAlu 132436366 90.48% 90.54% # Class of executed instruction
system.cpu0.op_class::IntMult 58371 0.04% 90.58% # Class of executed instruction
system.cpu0.op_class::IntDiv 47638 0.03% 90.62% # Class of executed instruction
system.cpu0.op_class::FloatAdd 0 0.00% 90.62% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 90.62% # Class of executed instruction
system.cpu0.op_class::FloatCvt 0 0.00% 90.62% # Class of executed instruction
system.cpu0.op_class::FloatMult 0 0.00% 90.62% # Class of executed instruction
system.cpu0.op_class::FloatDiv 0 0.00% 90.62% # Class of executed instruction
system.cpu0.op_class::FloatSqrt 0 0.00% 90.62% # Class of executed instruction
system.cpu0.op_class::SimdAdd 0 0.00% 90.62% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc 0 0.00% 90.62% # Class of executed instruction
system.cpu0.op_class::SimdAlu 0 0.00% 90.62% # Class of executed instruction
system.cpu0.op_class::SimdCmp 0 0.00% 90.62% # Class of executed instruction
system.cpu0.op_class::SimdCvt 0 0.00% 90.62% # Class of executed instruction
system.cpu0.op_class::SimdMisc 0 0.00% 90.62% # Class of executed instruction
system.cpu0.op_class::SimdMult 0 0.00% 90.62% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc 0 0.00% 90.62% # Class of executed instruction
system.cpu0.op_class::SimdShift 0 0.00% 90.62% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.62% # Class of executed instruction
system.cpu0.op_class::SimdSqrt 0 0.00% 90.62% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.62% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.62% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.62% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.62% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.62% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.62% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 90.62% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.62% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.62% # Class of executed instruction
system.cpu0.op_class::MemRead 10122778 6.92% 97.53% # Class of executed instruction
system.cpu0.op_class::MemWrite 3612208 2.47% 100.00% # Class of executed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.op_class::total 146372579 # Class of executed instruction
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dcache.tags.replacements 1637223 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.999462 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 19645241 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 1637735 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 11.995372 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dcache.tags.occ_blocks::cpu0.data 126.457209 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 281.700690 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data 103.841562 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.246987 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.550197 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data 0.202816 # Average percentage of cache occupancy
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 239 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dcache.tags.tag_accesses 88377043 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 88377043 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 4914910 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 2565511 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data 4026210 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 11506631 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 3467385 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 1750714 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data 2858968 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 8077067 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 20221 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data 10190 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu2.data 29345 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 59756 # number of SoftPFReq hits
system.cpu0.dcache.demand_hits::cpu0.data 8382295 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 4316225 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data 6885178 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 19583698 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 8402516 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 4326415 # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data 6914523 # number of overall hits
system.cpu0.dcache.overall_hits::total 19643454 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 362607 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 162199 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data 784843 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 1309649 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 140483 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 61206 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data 123727 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 325416 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 152674 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data 62891 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu2.data 190739 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 406304 # number of SoftPFReq misses
system.cpu0.dcache.demand_misses::cpu0.data 503090 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 223405 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data 908570 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 1635065 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 655764 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 286296 # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data 1099309 # number of overall misses
system.cpu0.dcache.overall_misses::total 2041369 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2292566250 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 12877344029 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 15169910279 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2335955064 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 3849112259 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 6185067323 # number of WriteReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 4628521314 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data 16726456288 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 21354977602 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 4628521314 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data 16726456288 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 21354977602 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 5277517 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 2727710 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data 4811053 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 12816280 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 3607868 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 1811920 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data 2982695 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 8402483 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 172895 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 73081 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 220084 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 466060 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 8885385 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 4539630 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data 7793748 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 21218763 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 9058280 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 4612711 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data 8013832 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 21684823 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.068708 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.059463 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.163133 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.102186 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.038938 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.033780 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.041482 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.038729 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.883045 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.860566 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.866665 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.871785 # miss rate for SoftPFReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.056620 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.049212 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data 0.116577 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.077058 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.072394 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.062067 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data 0.137176 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.094138 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14134.281037 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16407.541418 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 11583.187769 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 38165.458681 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 31109.719455 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 19006.647869 # average WriteReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20718.073964 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 18409.650647 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 13060.629151 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16166.908773 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 15215.427408 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 10461.106053 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 134433 # number of cycles access was blocked
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dcache.blocked::no_mshrs 27793 # number of cycles access was blocked
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 4.836937 # average number of cycles each access was blocked
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dcache.writebacks::writebacks 1546924 # number of writebacks
system.cpu0.dcache.writebacks::total 1546924 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 56 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 365946 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 366002 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1557 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 30874 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 32431 # number of WriteReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data 1613 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data 396820 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 398433 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data 1613 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data 396820 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 398433 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 162143 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 418897 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 581040 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 59649 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 92853 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 152502 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 62890 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 187206 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 250096 # number of SoftPFReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 221792 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data 511750 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 733542 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 284682 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data 698956 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 983638 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1966861250 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 5809520082 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7776381332 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2132969160 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3102124491 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5235093651 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 862802000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 2814001254 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 3676803254 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4099830410 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 8911644573 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 13011474983 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4962632410 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 11725645827 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 16688278237 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30452841000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 32981775500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63434616500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 580448000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 654820000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1235268000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31033289000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33636595500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 64669884500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.059443 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.087070 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.045336 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032920 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.031131 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018150 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.860552 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.850612 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.536618 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.048857 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.065662 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.034570 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.061717 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.087219 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.045361 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12130.411119 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13868.612289 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13383.555920 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35758.674244 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 33408.985073 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34328.032754 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13719.224042 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15031.576199 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14701.567614 # average SoftPFReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18485.023851 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17414.058765 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17737.873200 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17432.195959 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16775.942730 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16965.873865 # average overall mshr miss latency
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.icache.tags.replacements 864556 # number of replacements
system.cpu0.icache.tags.tagsinuse 510.818449 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 129670562 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 865068 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 149.896380 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 150508783000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 137.666475 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 267.493000 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst 105.658974 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.268880 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.522447 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst 0.206365 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.997692 # Average percentage of cache occupancy
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.icache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.icache.tags.age_task_id_blocks_1024::1 132 # Occupied blocks per task id
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.icache.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.icache.tags.tag_accesses 131423060 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 131423060 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 87330581 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 39275354 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst 3064627 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 129670562 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 87330581 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 39275354 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst 3064627 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 129670562 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 87330581 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 39275354 # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst 3064627 # number of overall hits
system.cpu0.icache.overall_hits::total 129670562 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 333345 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 159327 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst 394745 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 887417 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 333345 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 159327 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst 394745 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 887417 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 333345 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 159327 # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst 394745 # number of overall misses
system.cpu0.icache.overall_misses::total 887417 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2225138500 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5515741155 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 7740879655 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 2225138500 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst 5515741155 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 7740879655 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 2225138500 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst 5515741155 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 7740879655 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 87663926 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 39434681 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst 3459372 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 130557979 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 87663926 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 39434681 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst 3459372 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 130557979 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 87663926 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 39434681 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst 3459372 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 130557979 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003803 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004040 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.114109 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.006797 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003803 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004040 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst 0.114109 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.006797 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003803 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004040 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst 0.114109 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.006797 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13965.859522 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13972.922152 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 8722.933700 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13965.859522 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13972.922152 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 8722.933700 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13965.859522 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13972.922152 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 8722.933700 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 4752 # number of cycles access was blocked
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.icache.blocked::no_mshrs 268 # number of cycles access was blocked
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.731343 # average number of cycles each access was blocked
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 22336 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 22336 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu2.inst 22336 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 22336 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu2.inst 22336 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 22336 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 159327 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 372409 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 531736 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 159327 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst 372409 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 531736 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 159327 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst 372409 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 531736 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1905663500 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4555263703 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 6460927203 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1905663500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4555263703 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 6460927203 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1905663500 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4555263703 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 6460927203 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004040 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.107652 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004073 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004040 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.107652 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.004073 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004040 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.107652 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.004073 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11960.706597 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12231.884039 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12150.629641 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11960.706597 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12231.884039 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12150.629641 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11960.706597 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12231.884039 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12150.629641 # average overall mshr miss latency
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.numCycles 2604019962 # number of cpu cycles simulated
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.committedInsts 35730684 # Number of instructions committed
system.cpu1.committedOps 69408718 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 64481893 # Number of integer alu accesses
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.num_func_calls 491880 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 6558534 # number of instructions that are conditional controls
system.cpu1.num_int_insts 64481893 # number of integer instructions
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu1.num_fp_insts 0 # number of float instructions
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.num_int_register_reads 119402180 # number of times the integer registers were read
system.cpu1.num_int_register_writes 55560948 # number of times the integer registers were written
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.num_cc_register_reads 36459460 # number of times the CC registers were read
system.cpu1.num_cc_register_writes 27231683 # number of times the CC registers were written
system.cpu1.num_mem_refs 4801643 # number of memory refs
system.cpu1.num_load_insts 2988079 # Number of load instructions
system.cpu1.num_store_insts 1813564 # Number of store instructions
system.cpu1.num_idle_cycles 2476018804.880995 # Number of idle cycles
system.cpu1.num_busy_cycles 128001157.119005 # Number of busy cycles
system.cpu1.not_idle_fraction 0.049155 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.950845 # Percentage of idle cycles
system.cpu1.Branches 7226738 # Number of branches fetched
system.cpu1.op_class::No_OpClass 34859 0.05% 0.05% # Class of executed instruction
system.cpu1.op_class::IntAlu 64514544 92.95% 93.00% # Class of executed instruction
system.cpu1.op_class::IntMult 31705 0.05% 93.04% # Class of executed instruction
system.cpu1.op_class::IntDiv 26275 0.04% 93.08% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 93.08% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 93.08% # Class of executed instruction
system.cpu1.op_class::FloatCvt 0 0.00% 93.08% # Class of executed instruction
system.cpu1.op_class::FloatMult 0 0.00% 93.08% # Class of executed instruction
system.cpu1.op_class::FloatDiv 0 0.00% 93.08% # Class of executed instruction
system.cpu1.op_class::FloatSqrt 0 0.00% 93.08% # Class of executed instruction
system.cpu1.op_class::SimdAdd 0 0.00% 93.08% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc 0 0.00% 93.08% # Class of executed instruction
system.cpu1.op_class::SimdAlu 0 0.00% 93.08% # Class of executed instruction
system.cpu1.op_class::SimdCmp 0 0.00% 93.08% # Class of executed instruction
system.cpu1.op_class::SimdCvt 0 0.00% 93.08% # Class of executed instruction
system.cpu1.op_class::SimdMisc 0 0.00% 93.08% # Class of executed instruction
system.cpu1.op_class::SimdMult 0 0.00% 93.08% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc 0 0.00% 93.08% # Class of executed instruction
system.cpu1.op_class::SimdShift 0 0.00% 93.08% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.08% # Class of executed instruction
system.cpu1.op_class::SimdSqrt 0 0.00% 93.08% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.08% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.08% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.08% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.08% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.08% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.08% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 93.08% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.08% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.08% # Class of executed instruction
system.cpu1.op_class::MemRead 2988079 4.31% 97.39% # Class of executed instruction
system.cpu1.op_class::MemWrite 1813564 2.61% 100.00% # Class of executed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.op_class::total 69409026 # Class of executed instruction
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu2.branchPred.lookups 29092929 # Number of BP lookups
system.cpu2.branchPred.condPredicted 29092929 # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect 315476 # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups 26409431 # Number of BTB lookups
system.cpu2.branchPred.BTBHits 25746575 # Number of BTB hits
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu2.branchPred.BTBHitPct 97.490078 # BTB Hit Percentage
system.cpu2.branchPred.usedRAS 584007 # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect 63229 # Number of incorrect RAS predictions.
system.cpu2.numCycles 153281353 # number of cpu cycles simulated
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu2.fetch.icacheStallCycles 10494646 # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts 143459530 # Number of instructions fetch has processed
system.cpu2.fetch.Branches 29092929 # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches 26330582 # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles 141345595 # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles 659748 # Number of cycles fetch has spent squashing
system.cpu2.fetch.TlbCycles 97189 # Number of cycles fetch has spent waiting for tlb
system.cpu2.fetch.MiscStallCycles 4757 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.PendingDrainCycles 7888 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu2.fetch.PendingTrapStallCycles 55541 # Number of stall cycles due to pending traps
system.cpu2.fetch.PendingQuiesceStallCycles 2125 # Number of stall cycles due to pending quiesce instructions
system.cpu2.fetch.IcacheWaitRetryStallCycles 437 # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines 3459376 # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes 164097 # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.ItlbSquashes 3515 # Number of outstanding ITLB misses that were squashed
system.cpu2.fetch.rateDist::samples 152337401 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean 1.854593 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev 3.033085 # Number of instructions fetched each cycle (Total)
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu2.fetch.rateDist::0 97296263 63.87% 63.87% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1 832536 0.55% 64.42% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2 23575408 15.48% 79.89% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3 586344 0.38% 80.28% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4 814239 0.53% 80.81% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5 832677 0.55% 81.36% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6 567105 0.37% 81.73% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7 704147 0.46% 82.19% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8 27128682 17.81% 100.00% # Number of instructions fetched each cycle (Total)
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu2.fetch.rateDist::total 152337401 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate 0.189801 # Number of branch fetches per cycle
system.cpu2.fetch.rate 0.935923 # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles 9688238 # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles 93124886 # Number of cycles decode is blocked
system.cpu2.decode.RunCycles 23395204 # Number of cycles decode is running
system.cpu2.decode.UnblockCycles 5013369 # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles 330525 # Number of cycles decode is squashing
system.cpu2.decode.DecodedInsts 279674043 # Number of instructions handled by decode
system.cpu2.rename.SquashCycles 330525 # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles 11836052 # Number of cycles rename is idle
system.cpu2.rename.BlockCycles 76001562 # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles 4488572 # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles 26027497 # Number of cycles rename is running
system.cpu2.rename.UnblockCycles 12868079 # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts 278471354 # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents 223428 # Number of times rename has blocked due to ROB full
system.cpu2.rename.IQFullEvents 5927671 # Number of times rename has blocked due to IQ full
system.cpu2.rename.LQFullEvents 64367 # Number of times rename has blocked due to LQ full
system.cpu2.rename.SQFullEvents 4764004 # Number of times rename has blocked due to SQ full
system.cpu2.rename.RenamedOperands 332707542 # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups 607302278 # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups 372965322 # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups 116 # Number of floating rename lookups
system.cpu2.rename.CommittedMaps 320669422 # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps 12038120 # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts 154906 # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts 156494 # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts 24500450 # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads 6532282 # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores 3632430 # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads 395237 # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores 325236 # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded 276569941 # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded 416887 # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued 274532538 # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued 100855 # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined 8584816 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined 13350787 # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved 62925 # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples 152337401 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean 1.802135 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev 2.398465 # Number of insts issued each cycle
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu2.iq.issued_per_cycle::0 89943207 59.04% 59.04% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1 5345468 3.51% 62.55% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2 3937636 2.58% 65.14% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3 3657575 2.40% 67.54% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4 22350485 14.67% 82.21% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5 2587133 1.70% 83.91% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6 23826816 15.64% 99.55% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7 472076 0.31% 99.86% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8 217005 0.14% 100.00% # Number of insts issued each cycle
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu2.iq.issued_per_cycle::total 152337401 # Number of insts issued each cycle
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu2.iq.fu_full::IntAlu 1755222 86.36% 86.36% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult 0 0.00% 86.36% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv 168 0.01% 86.37% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd 0 0.00% 86.37% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp 0 0.00% 86.37% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt 0 0.00% 86.37% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult 0 0.00% 86.37% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv 0 0.00% 86.37% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 86.37% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd 0 0.00% 86.37% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 86.37% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu 0 0.00% 86.37% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp 0 0.00% 86.37% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt 0 0.00% 86.37% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc 0 0.00% 86.37% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult 0 0.00% 86.37% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 86.37% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift 0 0.00% 86.37% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 86.37% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 86.37% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 86.37% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 86.37% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 86.37% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 86.37% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 86.37% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 86.37% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 86.37% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 86.37% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 86.37% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead 216539 10.65% 97.02% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite 60595 2.98% 100.00% # attempts to use FU when none available
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu2.iq.FU_type_0::No_OpClass 75570 0.03% 0.03% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu 264135020 96.21% 96.24% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult 55664 0.02% 96.26% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv 49906 0.02% 96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.28% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead 6866354 2.50% 98.78% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite 3350024 1.22% 100.00% # Type of FU issued
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu2.iq.FU_type_0::total 274532538 # Type of FU issued
system.cpu2.iq.rate 1.791037 # Inst issue rate
system.cpu2.iq.fu_busy_cnt 2032524 # FU busy when requested
system.cpu2.iq.fu_busy_rate 0.007404 # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads 703535734 # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes 285575754 # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses 272952384 # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads 122 # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes 212 # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses 276489433 # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses 59 # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads 719306 # Number of loads that had data forwarded from stores
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu2.iew.lsq.thread0.squashedLoads 1204229 # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses 6084 # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation 4820 # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores 645551 # Number of stores squashed
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu2.iew.lsq.thread0.rescheduledLoads 756143 # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked 21686 # Number of times an access to memory failed due to the cache being blocked
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu2.iew.iewSquashCycles 330525 # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles 70849508 # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles 1741832 # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts 276986828 # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts 38338 # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts 6532282 # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts 3632430 # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts 240586 # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents 193301 # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents 1249611 # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents 4820 # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect 179927 # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect 186201 # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts 366128 # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts 273965652 # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts 6730604 # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts 516589 # Number of squashed instructions skipped in execute
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.iew.exec_swp 0 # number of swp insts executed
system.cpu2.iew.exec_nop 0 # number of nop insts executed
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu2.iew.exec_refs 9996676 # number of memory reference insts executed
system.cpu2.iew.exec_branches 27816636 # Number of branches executed
system.cpu2.iew.exec_stores 3266072 # Number of stores executed
system.cpu2.iew.exec_rate 1.787338 # Inst execution rate
system.cpu2.iew.wb_sent 273775485 # cumulative count of insts sent to commit
system.cpu2.iew.wb_count 272952416 # cumulative count of insts written-back
system.cpu2.iew.wb_producers 212880444 # num instructions producing a value
system.cpu2.iew.wb_consumers 349125324 # num instructions consuming a value
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu2.iew.wb_rate 1.780728 # insts written-back per cycle
system.cpu2.iew.wb_fanout 0.609754 # average fanout of values written-back
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu2.commit.commitSquashedInsts 8921992 # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls 353962 # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts 318190 # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples 151004847 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean 1.775201 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev 2.653055 # Number of insts commited each cycle
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu2.commit.committed_per_cycle::0 93801921 62.12% 62.12% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1 4186228 2.77% 64.89% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2 1259762 0.83% 65.72% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3 24518557 16.24% 81.96% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4 1012800 0.67% 82.63% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5 677237 0.45% 83.08% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6 473264 0.31% 83.39% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7 23075029 15.28% 98.68% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8 2000049 1.32% 100.00% # Number of insts commited each cycle
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu2.commit.committed_per_cycle::total 151004847 # Number of insts commited each cycle
system.cpu2.commit.committedInsts 135819902 # Number of instructions committed
system.cpu2.commit.committedOps 268063987 # Number of ops (including micro ops) committed
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu2.commit.refs 8314932 # Number of memory references committed
system.cpu2.commit.loads 5328053 # Number of loads committed
system.cpu2.commit.membars 161474 # Number of memory barriers committed
system.cpu2.commit.branches 27411077 # Number of branches committed
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu2.commit.int_insts 244897516 # Number of committed integer instructions.
system.cpu2.commit.function_calls 434912 # Number of function calls committed.
system.cpu2.commit.op_class_0::No_OpClass 44620 0.02% 0.02% # Class of committed instruction
system.cpu2.commit.op_class_0::IntAlu 259602696 96.84% 96.86% # Class of committed instruction
system.cpu2.commit.op_class_0::IntMult 53542 0.02% 96.88% # Class of committed instruction
system.cpu2.commit.op_class_0::IntDiv 48197 0.02% 96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.90% # Class of committed instruction
system.cpu2.commit.op_class_0::MemRead 5328053 1.99% 98.89% # Class of committed instruction
system.cpu2.commit.op_class_0::MemWrite 2986879 1.11% 100.00% # Class of committed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu2.commit.op_class_0::total 268063987 # Class of committed instruction
system.cpu2.commit.bw_lim_events 2000049 # number cycles where commit BW limit reached
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu2.rob.rob_reads 425964171 # The number of ROB reads
system.cpu2.rob.rob_writes 555310468 # The number of ROB writes
system.cpu2.timesIdled 112460 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles 943952 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles 4909839532 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts 135819902 # Number of Instructions Simulated
system.cpu2.committedOps 268063987 # Number of Ops (including micro ops) Simulated
system.cpu2.cpi 1.128563 # CPI: Cycles Per Instruction
system.cpu2.cpi_total 1.128563 # CPI: Total CPI of All Threads
system.cpu2.ipc 0.886082 # IPC: Instructions Per Cycle
system.cpu2.ipc_total 0.886082 # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads 364708409 # number of integer regfile reads
system.cpu2.int_regfile_writes 218787106 # number of integer regfile writes
system.cpu2.fp_regfile_reads 72944 # number of floating regfile reads
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu2.fp_regfile_writes 72912 # number of floating regfile writes
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu2.cc_regfile_reads 139159619 # number of cc regfile reads
system.cpu2.cc_regfile_writes 107004309 # number of cc regfile writes
system.cpu2.misc_regfile_reads 89032423 # number of misc regfile reads
system.cpu2.misc_regfile_writes 133306 # number of misc regfile writes
system.iobus.trans_dist::ReadReq 3554527 # Transaction distribution
system.iobus.trans_dist::ReadResp 3554527 # Transaction distribution
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.trans_dist::WriteReq 57693 # Transaction distribution
system.iobus.trans_dist::WriteResp 10973 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
system.iobus.trans_dist::MessageReq 1666 # Transaction distribution
system.iobus.trans_dist::MessageResp 1666 # Transaction distribution
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7085054 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1154 # Packet count per connected master and slave (bytes)
x86: Update stats for the new Linux delay port.
2014-11-22 02:22:19 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27740 # Packet count per connected master and slave (bytes)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.bridge.master::total 7129192 # Packet count per connected master and slave (bytes)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95248 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95248 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3332 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3332 # Packet count per connected master and slave (bytes)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.iobus.pkt_count::total 7227772 # Packet count per connected master and slave (bytes)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3542527 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2308 # Cumulative packet size per connected master and slave (bytes)
x86: Update stats for the new Linux delay port.
2014-11-22 02:22:19 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13870 # Cumulative packet size per connected master and slave (bytes)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.bridge.master::total 3570795 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027776 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027776 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6664 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6664 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.iobus.pkt_size::total 6605235 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 2673040 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 27000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.iobus.reqLayer3.occupancy 4313000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 4000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer5.occupancy 758000 # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.iobus.reqLayer6.occupancy 22000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 15000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer9.occupancy 142528000 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.iobus.reqLayer10.occupancy 345000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer11.occupancy 134000 # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.iobus.reqLayer14.occupancy 10349000 # Layer occupancy (ticks)
x86: Update stats for the new Linux delay port.
2014-11-22 02:22:19 +01:00
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
x86: Update stats for the new Linux delay port.
2014-11-22 02:22:19 +01:00
system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.iobus.reqLayer19.occupancy 277910069 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
x86: Update stats for the new Linux delay port.
2014-11-22 02:22:19 +01:00
system.iobus.reqLayer20.occupancy 1032000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.iobus.respLayer0.occupancy 302790000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.iobus.respLayer1.occupancy 34215251 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.iobus.respLayer2.occupancy 1117000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.iocache.tags.replacements 47569 # number of replacements
system.iocache.tags.tagsinuse 0.087266 # Cycle average of tags in use
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks.
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.iocache.tags.warmup_cycle 5000571413009 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.087266 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005454 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.005454 # Average percentage of cache occupancy
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.iocache.tags.tag_accesses 428616 # Number of tag accesses
system.iocache.tags.data_accesses 428616 # Number of data accesses
system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses
system.iocache.ReadReq_misses::total 904 # number of ReadReq misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.iocache.demand_misses::pc.south_bridge.ide 904 # number of demand (read+write) misses
system.iocache.demand_misses::total 904 # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide 904 # number of overall misses
system.iocache.overall_misses::total 904 # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 131125053 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 131125053 # number of ReadReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 7701347765 # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total 7701347765 # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide 131125053 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 131125053 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide 131125053 # number of overall miss cycles
system.iocache.overall_miss_latency::total 131125053 # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.iocache.demand_accesses::pc.south_bridge.ide 904 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 904 # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide 904 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 904 # number of overall (read+write) accesses
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 145049.837389 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 145049.837389 # average ReadReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 164840.491545 # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 164840.491545 # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 145049.837389 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 145049.837389 # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 145049.837389 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 145049.837389 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 44239 # number of cycles access was blocked
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.iocache.blocked::no_mshrs 5740 # number of cycles access was blocked
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.iocache.avg_blocked_cycles::no_mshrs 7.707143 # average number of cycles each access was blocked
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.fast_writes 0 # number of fast writes performed
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.cache_copies 0 # number of cache copies performed
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.writebacks::writebacks 46667 # number of writebacks
system.iocache.writebacks::total 46667 # number of writebacks
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 737 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 737 # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 28920 # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total 28920 # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide 737 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 737 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide 737 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 737 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 92773553 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 92773553 # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 6197505767 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6197505767 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 92773553 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 92773553 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 92773553 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 92773553 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.815265 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 0.815265 # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.619007 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.619007 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.815265 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 0.815265 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.815265 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 0.815265 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 125879.990502 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 125879.990502 # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 214298.263036 # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 214298.263036 # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 125879.990502 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 125879.990502 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 125879.990502 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 125879.990502 # average overall mshr miss latency
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.l2c.tags.replacements 104557 # number of replacements
system.l2c.tags.tagsinuse 64826.146133 # Cycle average of tags in use
system.l2c.tags.total_refs 3692284 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 168716 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 21.884611 # Average number of references to valid blocks.
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.l2c.tags.occ_blocks::writebacks 51357.956330 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.134652 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 1732.560753 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 4954.090850 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 380.669805 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 1966.640889 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.dtb.walker 6.273350 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst 862.228039 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data 3565.591465 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.783660 # Average percentage of cache occupancy
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.l2c.tags.occ_percent::cpu0.inst 0.026437 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.075593 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.005809 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.030009 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000096 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst 0.013157 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data 0.054407 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.989168 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024 64159 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 2872 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 7102 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 53894 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024 0.978989 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 33845084 # Number of tag accesses
system.l2c.tags.data_accesses 33845084 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 19958 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 10605 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 325698 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 500488 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 12200 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 6454 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 157050 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 219829 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.dtb.walker 57606 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.itb.walker 13614 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst 367139 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data 593198 # number of ReadReq hits
system.l2c.ReadReq_hits::total 2283839 # number of ReadReq hits
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits
system.l2c.WriteReq_hits::total 2 # number of WriteReq hits
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.l2c.Writeback_hits::writebacks 1546924 # number of Writeback hits
system.l2c.Writeback_hits::total 1546924 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 142 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 42 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data 83 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 267 # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 67626 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 34040 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data 59382 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 161048 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 19958 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 10607 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 325698 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 568114 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 12200 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 6454 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 157050 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 253869 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.dtb.walker 57606 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.itb.walker 13614 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst 367139 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data 652580 # number of demand (read+write) hits
system.l2c.demand_hits::total 2444889 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 19958 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 10607 # number of overall hits
system.l2c.overall_hits::cpu0.inst 325698 # number of overall hits
system.l2c.overall_hits::cpu0.data 568114 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 12200 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 6454 # number of overall hits
system.l2c.overall_hits::cpu1.inst 157050 # number of overall hits
system.l2c.overall_hits::cpu1.data 253869 # number of overall hits
system.l2c.overall_hits::cpu2.dtb.walker 57606 # number of overall hits
system.l2c.overall_hits::cpu2.itb.walker 13614 # number of overall hits
system.l2c.overall_hits::cpu2.inst 367139 # number of overall hits
system.l2c.overall_hits::cpu2.data 652580 # number of overall hits
system.l2c.overall_hits::total 2444889 # number of overall hits
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.l2c.ReadReq_misses::cpu0.itb.walker 5 # number of ReadReq misses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.l2c.ReadReq_misses::cpu0.inst 7634 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 14793 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 2277 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 5204 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.dtb.walker 28 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst 5252 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data 12827 # number of ReadReq misses
system.l2c.ReadReq_misses::total 48020 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 716 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 252 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data 429 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 1397 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 71999 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 25327 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data 33038 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 130364 # number of ReadExReq misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.l2c.demand_misses::cpu0.itb.walker 5 # number of demand (read+write) misses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.l2c.demand_misses::cpu0.inst 7634 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 86792 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 2277 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 30531 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.dtb.walker 28 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst 5252 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data 45865 # number of demand (read+write) misses
system.l2c.demand_misses::total 178384 # number of demand (read+write) misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.l2c.overall_misses::cpu0.itb.walker 5 # number of overall misses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.l2c.overall_misses::cpu0.inst 7634 # number of overall misses
system.l2c.overall_misses::cpu0.data 86792 # number of overall misses
system.l2c.overall_misses::cpu1.inst 2277 # number of overall misses
system.l2c.overall_misses::cpu1.data 30531 # number of overall misses
system.l2c.overall_misses::cpu2.dtb.walker 28 # number of overall misses
system.l2c.overall_misses::cpu2.inst 5252 # number of overall misses
system.l2c.overall_misses::cpu2.data 45865 # number of overall misses
system.l2c.overall_misses::total 178384 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu1.inst 168366000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 397984750 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 2372250 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst 409592250 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data 1011202500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 1989517750 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 3186900 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data 4949298 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 8136198 # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 1722829913 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data 2376737177 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 4099567090 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu1.inst 168366000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 2120814663 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.dtb.walker 2372250 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst 409592250 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data 3387939677 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 6089084840 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.inst 168366000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 2120814663 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.dtb.walker 2372250 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst 409592250 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data 3387939677 # number of overall miss cycles
system.l2c.overall_miss_latency::total 6089084840 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 19958 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 10610 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 333332 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 515281 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 12200 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 6454 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 159327 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 225033 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.dtb.walker 57634 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.itb.walker 13614 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst 372391 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data 606025 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 2331859 # number of ReadReq accesses(hits+misses)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.l2c.WriteReq_accesses::cpu0.itb.walker 2 # number of WriteReq accesses(hits+misses)
system.l2c.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.l2c.Writeback_accesses::writebacks 1546924 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 1546924 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 858 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 294 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data 512 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 1664 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 139625 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 59367 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data 92420 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 291412 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 19958 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 10612 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 333332 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 654906 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 12200 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 6454 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 159327 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 284400 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.dtb.walker 57634 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.itb.walker 13614 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst 372391 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data 698445 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 2623273 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 19958 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 10612 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 333332 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 654906 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 12200 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 6454 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 159327 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 284400 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.dtb.walker 57634 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.itb.walker 13614 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst 372391 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data 698445 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2623273 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000471 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.022902 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.028709 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.014291 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.023125 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000486 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst 0.014103 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data 0.021166 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.020593 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.834499 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.857143 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data 0.837891 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.839543 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.515660 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.426617 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data 0.357477 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.447353 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.000471 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.022902 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.132526 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.014291 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.107352 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000486 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst 0.014103 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data 0.065667 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.068001 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.000471 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.022902 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.132526 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.014291 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.107352 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000486 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst 0.014103 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data 0.065667 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.068001 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 73942.028986 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 76476.700615 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 84723.214286 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 77987.861767 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data 78833.905044 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 41431.023532 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 12646.428571 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 11536.825175 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 5824.050107 # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68023.449797 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 71939.499274 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 31447.079639 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 73942.028986 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 69464.303921 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 84723.214286 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 77987.861767 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 73867.648032 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 34134.702888 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 73942.028986 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 69464.303921 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 84723.214286 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 77987.861767 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 73867.648032 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 34134.702888 # average overall miss latency
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.l2c.writebacks::writebacks 96401 # number of writebacks
system.l2c.writebacks::total 96401 # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu2.data 1 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu2.data 1 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu2.data 1 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu1.inst 2277 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 5204 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 28 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.inst 5252 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.data 12826 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 25587 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 252 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data 429 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 681 # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 25327 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data 33038 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 58365 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 2277 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 30531 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.dtb.walker 28 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst 5252 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data 45864 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 83952 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 2277 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 30531 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.dtb.walker 28 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst 5252 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data 45864 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 83952 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 139476000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 332911750 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 2025250 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 343880250 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data 851567000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 1669860250 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 3120740 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 4453925 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 7574665 # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1397470587 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1953261823 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 3350732410 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 139476000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 1730382337 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 2025250 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst 343880250 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data 2804828823 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 5020592660 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 139476000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 1730382337 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 2025250 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst 343880250 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data 2804828823 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 5020592660 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 27997956000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30229371500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 58227327500 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 540082000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 615936000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 1156018000 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28538038000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data 30845307500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 59383345500 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014291 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.023125 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000486 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.014103 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.021164 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.010973 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.857143 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.837891 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.409255 # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.426617 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.357477 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.200283 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014291 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.107352 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000486 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014103 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data 0.065666 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.032003 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014291 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.107352 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000486 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014103 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data 0.065666 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.032003 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61254.281950 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63972.280938 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 72330.357143 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 65476.056740 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 66393.809450 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 65262.056904 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 12383.888889 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10382.109557 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 11122.856094 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55177.106921 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 59121.672710 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 57409.961621 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61254.281950 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56676.241754 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 72330.357143 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 65476.056740 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 61155.346743 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 59803.133457 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61254.281950 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56676.241754 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 72330.357143 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 65476.056740 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 61155.346743 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 59803.133457 # average overall mshr miss latency
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.trans_dist::ReadReq 5119668 # Transaction distribution
system.membus.trans_dist::ReadResp 5119668 # Transaction distribution
system.membus.trans_dist::WriteReq 13886 # Transaction distribution
system.membus.trans_dist::WriteResp 13886 # Transaction distribution
system.membus.trans_dist::Writeback 143068 # Transaction distribution
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.trans_dist::UpgradeReq 1653 # Transaction distribution
system.membus.trans_dist::UpgradeResp 1653 # Transaction distribution
system.membus.trans_dist::ReadExReq 130108 # Transaction distribution
system.membus.trans_dist::ReadExResp 130108 # Transaction distribution
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.trans_dist::MessageReq 1666 # Transaction distribution
system.membus.trans_dist::MessageResp 1666 # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3332 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total 3332 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7129192 # Packet count per connected master and slave (bytes)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3040070 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 455653 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 10624915 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141621 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 141621 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 10769868 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6664 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::total 6664 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3570795 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6080137 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17551104 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 27202036 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6015808 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 6015808 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 33224508 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 602 # Total snoops (count)
system.membus.snoop_fanout::samples 370472 # Request fanout histogram
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::1 370472 100.00% 100.00% # Request fanout histogram
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::total 370472 # Request fanout histogram
system.membus.reqLayer0.occupancy 162446500 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.reqLayer1.occupancy 314906500 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.reqLayer2.occupancy 2234000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.reqLayer3.occupancy 1120775500 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.respLayer0.occupancy 1117000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.respLayer2.occupancy 1662967675 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.respLayer4.occupancy 35567749 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.toL2Bus.trans_dist::ReadReq 7434879 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 7434349 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 13888 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 13888 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 1546924 # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq 28920 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 1664 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 1664 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 291412 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 291412 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1730144 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 14995223 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 73480 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 207718 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 17006565 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 55364032 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213483380 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 273608 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 760144 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 269881164 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 70776 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 4251023 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 3.011203 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.105249 # Request fanout histogram
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.toL2Bus.snoop_fanout::3 4203399 98.88% 98.88% # Request fanout histogram
system.toL2Bus.snoop_fanout::4 47624 1.12% 100.00% # Request fanout histogram
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.toL2Bus.snoop_fanout::total 4251023 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 5194614325 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.toL2Bus.snoopLayer0.occupancy 931500 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.toL2Bus.respLayer0.occupancy 2395792281 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.toL2Bus.respLayer1.occupancy 4837647628 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.toL2Bus.respLayer2.occupancy 25185912 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.toL2Bus.respLayer3.occupancy 87831597 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
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