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gem5/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt

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x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
---------- Begin Simulation Statistics ----------
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
sim_seconds 5.142213 # Number of seconds simulated
sim_ticks 5142212861500 # Number of ticks simulated
final_tick 5142212861500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
host_inst_rate 316771 # Simulator instruction rate (inst/s)
host_op_rate 629731 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 6695034949 # Simulator tick rate (ticks/s)
host_mem_usage 960996 # Number of bytes of host memory used
host_seconds 768.06 # Real time elapsed on the host
sim_insts 243300298 # Number of instructions simulated
sim_ops 483673350 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 424320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 5246720 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 163840 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 2163392 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker 1984 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst 379584 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 2979328 # Number of bytes read from this memory
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.physmem.bytes_read::total 11387840 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 424320 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 163840 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 379584 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 967744 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 9172160 # Number of bytes written to this memory
system.physmem.bytes_written::total 9172160 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 6630 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 81980 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 2560 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 33803 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker 31 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst 5931 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 46552 # Number of read requests responded to by this memory
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.physmem.num_reads::total 177935 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 143315 # Number of write requests responded to by this memory
system.physmem.num_writes::total 143315 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 82517 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 1020323 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 12 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 31862 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 420712 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker 386 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst 73817 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data 579386 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::pc.south_bridge.ide 5514 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2214580 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 82517 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 31862 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst 73817 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 188196 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1783699 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1783699 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1783699 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 82517 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 1020323 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 12 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 31862 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 420712 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker 386 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst 73817 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data 579386 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide 5514 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 3998279 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 88878 # Number of read requests accepted
system.physmem.writeReqs 113942 # Number of write requests accepted
system.physmem.readBursts 88878 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 113942 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 5683264 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 4928 # Total number of bytes read from write queue
system.physmem.bytesWritten 7207296 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 5688192 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 7292288 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 77 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 1310 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 940 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 5243 # Per bank write bursts
system.physmem.perBankRdBursts::1 4719 # Per bank write bursts
system.physmem.perBankRdBursts::2 5104 # Per bank write bursts
system.physmem.perBankRdBursts::3 5729 # Per bank write bursts
system.physmem.perBankRdBursts::4 5898 # Per bank write bursts
system.physmem.perBankRdBursts::5 5027 # Per bank write bursts
system.physmem.perBankRdBursts::6 5470 # Per bank write bursts
system.physmem.perBankRdBursts::7 5567 # Per bank write bursts
system.physmem.perBankRdBursts::8 5651 # Per bank write bursts
system.physmem.perBankRdBursts::9 5723 # Per bank write bursts
system.physmem.perBankRdBursts::10 5167 # Per bank write bursts
system.physmem.perBankRdBursts::11 5483 # Per bank write bursts
system.physmem.perBankRdBursts::12 5886 # Per bank write bursts
system.physmem.perBankRdBursts::13 6693 # Per bank write bursts
system.physmem.perBankRdBursts::14 5960 # Per bank write bursts
system.physmem.perBankRdBursts::15 5481 # Per bank write bursts
system.physmem.perBankWrBursts::0 7238 # Per bank write bursts
system.physmem.perBankWrBursts::1 6716 # Per bank write bursts
system.physmem.perBankWrBursts::2 7069 # Per bank write bursts
system.physmem.perBankWrBursts::3 6723 # Per bank write bursts
system.physmem.perBankWrBursts::4 7013 # Per bank write bursts
system.physmem.perBankWrBursts::5 6703 # Per bank write bursts
system.physmem.perBankWrBursts::6 6619 # Per bank write bursts
system.physmem.perBankWrBursts::7 7556 # Per bank write bursts
system.physmem.perBankWrBursts::8 6486 # Per bank write bursts
system.physmem.perBankWrBursts::9 6985 # Per bank write bursts
system.physmem.perBankWrBursts::10 6508 # Per bank write bursts
system.physmem.perBankWrBursts::11 6763 # Per bank write bursts
system.physmem.perBankWrBursts::12 7496 # Per bank write bursts
system.physmem.perBankWrBursts::13 7338 # Per bank write bursts
system.physmem.perBankWrBursts::14 7696 # Per bank write bursts
system.physmem.perBankWrBursts::15 7705 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.physmem.totGap 5141212728000 # Total gap between requests
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.physmem.readPktSize::6 88878 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.physmem.writePktSize::6 113942 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 84289 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 3858 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 535 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 113 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.physmem.wrQLenPdf::0 127 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 69 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 65 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 64 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 60 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 59 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 59 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 59 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 58 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 58 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 57 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 58 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 57 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 58 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 58 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 1715 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 3249 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 5668 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 6433 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 6693 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 7316 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 7663 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 8264 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 7957 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 8287 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 7612 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 7231 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 6274 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 5871 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 4870 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 4666 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 4625 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 4543 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 290 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 249 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 217 # What write queue length does an incoming req see
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.wrQLenPdf::36 179 # What write queue length does an incoming req see
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.physmem.wrQLenPdf::37 160 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 155 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 140 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 148 # What write queue length does an incoming req see
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.wrQLenPdf::41 138 # What write queue length does an incoming req see
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.physmem.wrQLenPdf::42 131 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 129 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 108 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 103 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 84 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 73 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 80 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 68 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 58 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 33 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 18 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 9 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 3 # What write queue length does an incoming req see
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.physmem.bytesPerActivate::samples 41455 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 310.951538 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 179.940976 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 336.089751 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 16126 38.90% 38.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 9571 23.09% 61.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 4083 9.85% 71.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 2278 5.50% 77.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 1502 3.62% 80.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1068 2.58% 83.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 718 1.73% 85.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 598 1.44% 86.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 5511 13.29% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 41455 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 4333 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 20.493423 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 181.058580 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511 4330 99.93% 99.93% # Reads before turning the bus around for writes
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.rdPerTurnAround::1024-1535 1 0.02% 99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6144-6655 1 0.02% 99.98% # Reads before turning the bus around for writes
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.rdPerTurnAround::9728-10239 1 0.02% 100.00% # Reads before turning the bus around for writes
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.physmem.rdPerTurnAround::total 4333 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 4333 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 25.989845 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 20.182522 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 26.410005 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3 65 1.50% 1.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7 6 0.14% 1.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11 1 0.02% 1.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15 7 0.16% 1.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 3364 77.64% 79.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 26 0.60% 80.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 23 0.53% 80.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 179 4.13% 84.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 85 1.96% 86.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 35 0.81% 87.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 25 0.58% 88.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 23 0.53% 88.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 117 2.70% 91.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 7 0.16% 91.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 4 0.09% 91.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 4 0.09% 91.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 14 0.32% 91.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 9 0.21% 92.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 10 0.23% 92.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 35 0.81% 93.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 78 1.80% 95.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 2 0.05% 95.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91 4 0.09% 95.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 7 0.16% 95.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 92 2.12% 97.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 1 0.02% 97.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 7 0.16% 97.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 24 0.55% 98.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119 3 0.07% 98.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123 4 0.09% 98.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 1 0.02% 98.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 14 0.32% 98.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 4 0.09% 98.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139 1 0.02% 98.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 5 0.12% 98.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147 7 0.16% 99.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151 6 0.14% 99.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155 3 0.07% 99.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 1 0.02% 99.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163 3 0.07% 99.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167 3 0.07% 99.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-171 2 0.05% 99.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175 3 0.07% 99.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179 2 0.05% 99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183 1 0.02% 99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-187 2 0.05% 99.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191 2 0.05% 99.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::196-199 1 0.02% 99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-203 3 0.07% 99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::212-215 2 0.05% 99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::216-219 2 0.05% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-227 1 0.02% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::228-231 3 0.07% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 4333 # Writes before turning the bus around for reads
system.physmem.totQLat 976769250 # Total ticks spent queuing
system.physmem.totMemAccLat 2641788000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 444005000 # Total ticks spent in databus transfers
system.physmem.avgQLat 10999.53 # Average queueing delay per DRAM burst
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.physmem.avgMemAccLat 29749.53 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1.11 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.40 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1.11 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.42 # Average system write bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.physmem.busUtil 0.02 # Data bus utilization in percentage
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.physmem.avgWrQLen 10.09 # Average write queue length when enqueuing
system.physmem.readRowHits 70835 # Number of row buffer hits during reads
system.physmem.writeRowHits 89124 # Number of row buffer hits during writes
system.physmem.readRowHitRate 79.77 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 79.13 # Row buffer hit rate for writes
system.physmem.avgGap 25348647.71 # Average gap between requests
system.physmem.pageHitRate 79.41 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 153097560 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 83370375 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 333504600 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 360527760 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 250475462640 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 95043085920 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 2239708824000 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 2586157872855 # Total energy per rank (pJ)
system.physmem_0.averagePower 667.947189 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 3689335375500 # Time in different power states
system.physmem_0.memoryStateTime::REF 128054940000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.physmem_0.memoryStateTime::ACT 17909174750 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.physmem_1.actEnergy 160302240 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 87313875 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 359135400 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 369210960 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 250475462640 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 95555045385 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 2233887892500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 2580894363000 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.132718 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 3688582993750 # Time in different power states
system.physmem_1.memoryStateTime::REF 128054940000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.physmem_1.memoryStateTime::ACT 18657353000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu0.numCycles 905515045 # number of cpu cycles simulated
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu0.committedInsts 71354866 # Number of instructions committed
system.cpu0.committedOps 145718889 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 133579753 # Number of integer alu accesses
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu0.num_func_calls 936391 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 14189595 # number of instructions that are conditional controls
system.cpu0.num_int_insts 133579753 # number of integer instructions
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu0.num_fp_insts 0 # number of float instructions
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu0.num_int_register_reads 244625676 # number of times the integer registers were read
system.cpu0.num_int_register_writes 114972528 # number of times the integer registers were written
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu0.num_cc_register_reads 83222516 # number of times the CC registers were read
system.cpu0.num_cc_register_writes 55621681 # number of times the CC registers were written
system.cpu0.num_mem_refs 13385296 # number of memory refs
system.cpu0.num_load_insts 10015665 # Number of load instructions
system.cpu0.num_store_insts 3369631 # Number of store instructions
system.cpu0.num_idle_cycles 858514977.989050 # Number of idle cycles
system.cpu0.num_busy_cycles 47000067.010950 # Number of busy cycles
system.cpu0.not_idle_fraction 0.051904 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.948096 # Percentage of idle cycles
system.cpu0.Branches 15470512 # Number of branches fetched
system.cpu0.op_class::No_OpClass 89016 0.06% 0.06% # Class of executed instruction
system.cpu0.op_class::IntAlu 132139784 90.68% 90.74% # Class of executed instruction
system.cpu0.op_class::IntMult 57056 0.04% 90.78% # Class of executed instruction
system.cpu0.op_class::IntDiv 49774 0.03% 90.82% # Class of executed instruction
system.cpu0.op_class::FloatAdd 0 0.00% 90.82% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 90.82% # Class of executed instruction
system.cpu0.op_class::FloatCvt 0 0.00% 90.82% # Class of executed instruction
system.cpu0.op_class::FloatMult 0 0.00% 90.82% # Class of executed instruction
system.cpu0.op_class::FloatDiv 0 0.00% 90.82% # Class of executed instruction
system.cpu0.op_class::FloatSqrt 0 0.00% 90.82% # Class of executed instruction
system.cpu0.op_class::SimdAdd 0 0.00% 90.82% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc 0 0.00% 90.82% # Class of executed instruction
system.cpu0.op_class::SimdAlu 0 0.00% 90.82% # Class of executed instruction
system.cpu0.op_class::SimdCmp 0 0.00% 90.82% # Class of executed instruction
system.cpu0.op_class::SimdCvt 0 0.00% 90.82% # Class of executed instruction
system.cpu0.op_class::SimdMisc 0 0.00% 90.82% # Class of executed instruction
system.cpu0.op_class::SimdMult 0 0.00% 90.82% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc 0 0.00% 90.82% # Class of executed instruction
system.cpu0.op_class::SimdShift 0 0.00% 90.82% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.82% # Class of executed instruction
system.cpu0.op_class::SimdSqrt 0 0.00% 90.82% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.82% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.82% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.82% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.82% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.82% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.82% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 90.82% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.82% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.82% # Class of executed instruction
system.cpu0.op_class::MemRead 10013957 6.87% 97.69% # Class of executed instruction
system.cpu0.op_class::MemWrite 3369631 2.31% 100.00% # Class of executed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu0.op_class::total 145719218 # Class of executed instruction
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu0.dcache.tags.replacements 1638885 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.999440 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 19690308 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 1639397 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 12.010701 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu0.dcache.tags.occ_blocks::cpu0.data 129.361524 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 276.707159 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data 105.930757 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.252659 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.540444 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data 0.206896 # Average percentage of cache occupancy
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 321 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu0.dcache.tags.tag_accesses 88564731 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 88564731 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 4814748 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 2752692 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data 3969504 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 11536944 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 3244156 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 1918293 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data 2929310 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 8091759 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 19629 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data 10883 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu2.data 29286 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 59798 # number of SoftPFReq hits
system.cpu0.dcache.demand_hits::cpu0.data 8058904 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 4670985 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data 6898814 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 19628703 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 8078533 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 4681868 # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data 6928100 # number of overall hits
system.cpu0.dcache.overall_hits::total 19688501 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 357538 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 167572 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data 785074 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 1310184 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 120756 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 69485 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data 135769 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 326010 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 148495 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data 65341 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu2.data 192799 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 406635 # number of SoftPFReq misses
system.cpu0.dcache.demand_misses::cpu0.data 478294 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 237057 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data 920843 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 1636194 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 626789 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 302398 # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data 1113642 # number of overall misses
system.cpu0.dcache.overall_misses::total 2042829 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2347978500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 12373504263 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 14721482763 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2672090343 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 4159812296 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 6831902639 # number of WriteReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 5020068843 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data 16533316559 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 21553385402 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 5020068843 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data 16533316559 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 21553385402 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 5172286 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 2920264 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data 4754578 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 12847128 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 3364912 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 1987778 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data 3065079 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 8417769 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 168124 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 76224 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 222085 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 466433 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 8537198 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 4908042 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data 7819657 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 21264897 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 8705322 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 4984266 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data 8041742 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 21731330 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.069126 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.057382 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.165120 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.101983 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.035887 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.034956 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.044295 # miss rate for WriteReq accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dcache.WriteReq_miss_rate::total 0.038729 # miss rate for WriteReq accesses
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.883247 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.857223 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.868132 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.871797 # miss rate for SoftPFReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.056025 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.048300 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data 0.117760 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.076943 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.072001 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.060671 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data 0.138483 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.094004 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14011.759124 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15760.940068 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 11236.194888 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 38455.642844 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30638.896184 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 20956.113736 # average WriteReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21176.631962 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17954.544433 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 13172.878890 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16600.866550 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 14846.168301 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 10550.753588 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 139088 # number of cycles access was blocked
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu0.dcache.blocked::no_mshrs 28318 # number of cycles access was blocked
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 4.911646 # average number of cycles each access was blocked
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu0.dcache.writebacks::writebacks 1548383 # number of writebacks
system.cpu0.dcache.writebacks::total 1548383 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 50 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 365650 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 365700 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1634 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 30896 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 32530 # number of WriteReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data 1684 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data 396546 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 398230 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data 1684 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data 396546 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 398230 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 167522 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 419424 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 586946 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 67851 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 104873 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 172724 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 65340 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 189253 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 254593 # number of SoftPFReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 235373 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data 524297 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 759670 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 300713 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data 713550 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 1014263 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2011520500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 5751163604 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7762684104 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2447353879 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3384543386 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5831897265 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 907433250 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 2811202754 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 3718636004 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4458874379 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 9135706990 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 13594581369 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 5366307629 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 11946909744 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 17313217373 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30399909500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 32917271000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63317180500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 595136500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 580150000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1175286500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 30995046000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33497421000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 64492467000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.057365 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.088215 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.045687 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034134 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.034215 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.020519 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.857210 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.852165 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.545830 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.047957 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.067049 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.035724 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.060332 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.088731 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.046673 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12007.500507 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13712.051776 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13225.550739 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36069.532932 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32272.781231 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33764.255489 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13887.867309 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14854.204446 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14606.198929 # average SoftPFReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18943.865180 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17424.679123 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17895.377426 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17845.279815 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16742.918848 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17069.751507 # average overall mshr miss latency
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu0.icache.tags.replacements 866284 # number of replacements
system.cpu0.icache.tags.tagsinuse 510.794521 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 129883292 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 866796 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 149.842976 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 150549039500 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 149.181539 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 259.570231 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst 102.042751 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.291370 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.506973 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst 0.199302 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.997646 # Average percentage of cache occupancy
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu0.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 264 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 145 # Occupied blocks per task id
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu0.icache.tags.tag_accesses 131639749 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 131639749 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 86686522 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 40192040 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst 3004730 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 129883292 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 86686522 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 40192040 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst 3004730 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 129883292 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 86686522 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 40192040 # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst 3004730 # number of overall hits
system.cpu0.icache.overall_hits::total 129883292 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 314910 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 175554 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst 399185 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 889649 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 314910 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 175554 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst 399185 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 889649 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 314910 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 175554 # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst 399185 # number of overall misses
system.cpu0.icache.overall_misses::total 889649 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2455749750 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5633265441 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 8089015191 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 2455749750 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst 5633265441 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 8089015191 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 2455749750 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst 5633265441 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 8089015191 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 87001432 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 40367594 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst 3403915 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 130772941 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 87001432 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 40367594 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst 3403915 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 130772941 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 87001432 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 40367594 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst 3403915 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 130772941 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003620 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004349 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.117272 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.006803 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003620 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004349 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst 0.117272 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.006803 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003620 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004349 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst 0.117272 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.006803 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13988.571892 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14111.916633 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 9092.366980 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13988.571892 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14111.916633 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 9092.366980 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13988.571892 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14111.916633 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 9092.366980 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 5386 # number of cycles access was blocked
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu0.icache.blocked::no_mshrs 277 # number of cycles access was blocked
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu0.icache.avg_blocked_cycles::no_mshrs 19.444043 # average number of cycles each access was blocked
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 22841 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 22841 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu2.inst 22841 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 22841 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu2.inst 22841 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 22841 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 175554 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 376344 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 551898 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 175554 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst 376344 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 551898 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 175554 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst 376344 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 551898 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2103717250 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4645372892 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 6749090142 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2103717250 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4645372892 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 6749090142 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2103717250 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4645372892 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 6749090142 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004349 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.110562 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004220 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004349 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.110562 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.004220 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004349 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.110562 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.004220 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11983.305707 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12343.422220 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12228.872259 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11983.305707 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12343.422220 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12228.872259 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11983.305707 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12343.422220 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12228.872259 # average overall mshr miss latency
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu1.numCycles 2608019043 # number of cpu cycles simulated
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu1.committedInsts 36458068 # Number of instructions committed
system.cpu1.committedOps 70720299 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 65779411 # Number of integer alu accesses
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu1.num_func_calls 521390 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 6639276 # number of instructions that are conditional controls
system.cpu1.num_int_insts 65779411 # number of integer instructions
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu1.num_fp_insts 0 # number of float instructions
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu1.num_int_register_reads 122190876 # number of times the integer registers were read
system.cpu1.num_int_register_writes 56554100 # number of times the integer registers were written
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu1.num_cc_register_reads 37054979 # number of times the CC registers were read
system.cpu1.num_cc_register_writes 27544073 # number of times the CC registers were written
system.cpu1.num_mem_refs 5171486 # number of memory refs
system.cpu1.num_load_insts 3182631 # Number of load instructions
system.cpu1.num_store_insts 1988855 # Number of store instructions
system.cpu1.num_idle_cycles 2476913850.669656 # Number of idle cycles
system.cpu1.num_busy_cycles 131105192.330343 # Number of busy cycles
system.cpu1.not_idle_fraction 0.050270 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.949730 # Percentage of idle cycles
system.cpu1.Branches 7356329 # Number of branches fetched
system.cpu1.op_class::No_OpClass 36814 0.05% 0.05% # Class of executed instruction
system.cpu1.op_class::IntAlu 65455015 92.55% 92.61% # Class of executed instruction
system.cpu1.op_class::IntMult 34008 0.05% 92.65% # Class of executed instruction
system.cpu1.op_class::IntDiv 24962 0.04% 92.69% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 92.69% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 92.69% # Class of executed instruction
system.cpu1.op_class::FloatCvt 0 0.00% 92.69% # Class of executed instruction
system.cpu1.op_class::FloatMult 0 0.00% 92.69% # Class of executed instruction
system.cpu1.op_class::FloatDiv 0 0.00% 92.69% # Class of executed instruction
system.cpu1.op_class::FloatSqrt 0 0.00% 92.69% # Class of executed instruction
system.cpu1.op_class::SimdAdd 0 0.00% 92.69% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc 0 0.00% 92.69% # Class of executed instruction
system.cpu1.op_class::SimdAlu 0 0.00% 92.69% # Class of executed instruction
system.cpu1.op_class::SimdCmp 0 0.00% 92.69% # Class of executed instruction
system.cpu1.op_class::SimdCvt 0 0.00% 92.69% # Class of executed instruction
system.cpu1.op_class::SimdMisc 0 0.00% 92.69% # Class of executed instruction
system.cpu1.op_class::SimdMult 0 0.00% 92.69% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc 0 0.00% 92.69% # Class of executed instruction
system.cpu1.op_class::SimdShift 0 0.00% 92.69% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc 0 0.00% 92.69% # Class of executed instruction
system.cpu1.op_class::SimdSqrt 0 0.00% 92.69% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd 0 0.00% 92.69% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu 0 0.00% 92.69% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp 0 0.00% 92.69% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 0 0.00% 92.69% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 92.69% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc 0 0.00% 92.69% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 92.69% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 92.69% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 92.69% # Class of executed instruction
system.cpu1.op_class::MemRead 3181010 4.50% 97.19% # Class of executed instruction
system.cpu1.op_class::MemWrite 1988855 2.81% 100.00% # Class of executed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu1.op_class::total 70720664 # Class of executed instruction
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu2.branchPred.lookups 28980045 # Number of BP lookups
system.cpu2.branchPred.condPredicted 28980045 # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect 316258 # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups 26301179 # Number of BTB lookups
system.cpu2.branchPred.BTBHits 25662962 # Number of BTB hits
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu2.branchPred.BTBHitPct 97.573428 # BTB Hit Percentage
system.cpu2.branchPred.usedRAS 575120 # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect 62760 # Number of incorrect RAS predictions.
system.cpu2.numCycles 153675594 # number of cpu cycles simulated
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu2.fetch.icacheStallCycles 10522056 # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts 142983634 # Number of instructions fetch has processed
system.cpu2.fetch.Branches 28980045 # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches 26238082 # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles 141648223 # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles 664532 # Number of cycles fetch has spent squashing
system.cpu2.fetch.TlbCycles 102750 # Number of cycles fetch has spent waiting for tlb
system.cpu2.fetch.MiscStallCycles 5712 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.PendingDrainCycles 8254 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu2.fetch.PendingTrapStallCycles 65359 # Number of stall cycles due to pending traps
system.cpu2.fetch.PendingQuiesceStallCycles 18 # Number of stall cycles due to pending quiesce instructions
system.cpu2.fetch.IcacheWaitRetryStallCycles 587 # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines 3403920 # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes 164909 # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.ItlbSquashes 3818 # Number of outstanding ITLB misses that were squashed
system.cpu2.fetch.rateDist::samples 152684574 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean 1.843447 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev 3.027165 # Number of instructions fetched each cycle (Total)
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu2.fetch.rateDist::0 97834881 64.08% 64.08% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1 827461 0.54% 64.62% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2 23508780 15.40% 80.02% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3 590429 0.39% 80.40% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4 809590 0.53% 80.93% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5 824910 0.54% 81.47% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6 565945 0.37% 81.84% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7 689592 0.45% 82.29% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8 27032986 17.71% 100.00% # Number of instructions fetched each cycle (Total)
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu2.fetch.rateDist::total 152684574 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate 0.188579 # Number of branch fetches per cycle
system.cpu2.fetch.rate 0.930425 # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles 9666714 # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles 93465476 # Number of cycles decode is blocked
system.cpu2.decode.RunCycles 23018277 # Number of cycles decode is running
system.cpu2.decode.UnblockCycles 4894255 # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles 332917 # Number of cycles decode is squashing
system.cpu2.decode.DecodedInsts 278595760 # Number of instructions handled by decode
system.cpu2.rename.SquashCycles 332917 # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles 11754676 # Number of cycles rename is idle
system.cpu2.rename.BlockCycles 75764311 # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles 4472306 # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles 25597731 # Number of cycles rename is running
system.cpu2.rename.UnblockCycles 13455764 # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts 277400530 # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents 224282 # Number of times rename has blocked due to ROB full
system.cpu2.rename.IQFullEvents 5843297 # Number of times rename has blocked due to IQ full
system.cpu2.rename.LQFullEvents 52985 # Number of times rename has blocked due to LQ full
system.cpu2.rename.SQFullEvents 5514893 # Number of times rename has blocked due to SQ full
system.cpu2.rename.RenamedOperands 331330378 # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups 605053013 # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups 371514373 # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups 36 # Number of floating rename lookups
system.cpu2.rename.CommittedMaps 319639627 # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps 11690749 # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts 161038 # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts 162632 # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts 24003573 # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads 6435164 # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores 3706636 # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads 363903 # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores 318629 # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded 275503234 # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded 421288 # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued 273595538 # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued 103309 # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined 8356083 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined 12887842 # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved 64640 # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples 152684574 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean 1.791900 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev 2.394187 # Number of insts issued each cycle
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu2.iq.issued_per_cycle::0 90392452 59.20% 59.20% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1 5451363 3.57% 62.77% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2 3935423 2.58% 65.35% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3 3565723 2.34% 67.69% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4 22424664 14.69% 82.37% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5 2492768 1.63% 84.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6 23751475 15.56% 99.56% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7 460834 0.30% 99.86% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8 209872 0.14% 100.00% # Number of insts issued each cycle
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu2.iq.issued_per_cycle::total 152684574 # Number of insts issued each cycle
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu2.iq.fu_full::IntAlu 1676714 85.59% 85.59% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult 0 0.00% 85.59% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv 168 0.01% 85.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd 0 0.00% 85.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp 0 0.00% 85.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt 0 0.00% 85.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult 0 0.00% 85.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv 0 0.00% 85.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 85.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd 0 0.00% 85.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 85.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu 0 0.00% 85.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp 0 0.00% 85.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt 0 0.00% 85.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc 0 0.00% 85.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult 0 0.00% 85.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 85.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift 0 0.00% 85.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 85.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 85.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 85.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 85.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 85.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 85.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 85.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 85.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 85.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 85.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 85.60% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead 221197 11.29% 96.89% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite 60976 3.11% 100.00% # attempts to use FU when none available
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu2.iq.FU_type_0::No_OpClass 82248 0.03% 0.03% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu 263185371 96.20% 96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult 54901 0.02% 96.25% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv 48803 0.02% 96.26% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.26% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.26% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.26% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.26% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.26% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.26% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.26% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.26% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.26% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.26% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.26% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.26% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.26% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.26% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.26% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.26% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.26% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.26% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.26% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.26% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.26% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.26% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.26% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.26% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.26% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.26% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead 6793041 2.48% 98.75% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite 3431174 1.25% 100.00% # Type of FU issued
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu2.iq.FU_type_0::total 273595538 # Type of FU issued
system.cpu2.iq.rate 1.780345 # Inst issue rate
system.cpu2.iq.fu_busy_cnt 1959055 # FU busy when requested
system.cpu2.iq.fu_busy_rate 0.007160 # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads 701937961 # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes 284284863 # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses 272009603 # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads 52 # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes 68 # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses 12 # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses 275472321 # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses 24 # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads 698574 # Number of loads that had data forwarded from stores
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu2.iew.lsq.thread0.squashedLoads 1169867 # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses 6207 # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation 4815 # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores 637978 # Number of stores squashed
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu2.iew.lsq.thread0.rescheduledLoads 755628 # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked 24889 # Number of times an access to memory failed due to the cache being blocked
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu2.iew.iewSquashCycles 332917 # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles 70606528 # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles 1760004 # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts 275924522 # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts 40123 # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts 6435186 # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts 3706636 # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts 246888 # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents 186471 # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents 1275738 # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents 4815 # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect 176824 # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect 191426 # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts 368250 # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts 273027006 # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts 6657386 # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts 516016 # Number of squashed instructions skipped in execute
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.iew.exec_swp 0 # number of swp insts executed
system.cpu2.iew.exec_nop 0 # number of nop insts executed
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu2.iew.exec_refs 10001726 # number of memory reference insts executed
system.cpu2.iew.exec_branches 27723980 # Number of branches executed
system.cpu2.iew.exec_stores 3344340 # Number of stores executed
system.cpu2.iew.exec_rate 1.776645 # Inst execution rate
system.cpu2.iew.wb_sent 272834661 # cumulative count of insts sent to commit
system.cpu2.iew.wb_count 272009615 # cumulative count of insts written-back
system.cpu2.iew.wb_producers 211997747 # num instructions producing a value
system.cpu2.iew.wb_consumers 347754146 # num instructions consuming a value
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu2.iew.wb_rate 1.770025 # insts written-back per cycle
system.cpu2.iew.wb_fanout 0.609620 # average fanout of values written-back
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu2.commit.commitSquashedInsts 8688913 # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls 356648 # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts 319605 # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples 151378980 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean 1.765332 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev 2.647504 # Number of insts commited each cycle
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu2.commit.committed_per_cycle::0 94244642 62.26% 62.26% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1 4276340 2.82% 65.08% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2 1271564 0.84% 65.92% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3 24442364 16.15% 82.07% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4 1016704 0.67% 82.74% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5 679552 0.45% 83.19% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6 473445 0.31% 83.50% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7 23012596 15.20% 98.70% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8 1961773 1.30% 100.00% # Number of insts commited each cycle
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu2.commit.committed_per_cycle::total 151378980 # Number of insts commited each cycle
system.cpu2.commit.committedInsts 135487364 # Number of instructions committed
system.cpu2.commit.committedOps 267234162 # Number of ops (including micro ops) committed
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu2.commit.refs 8333976 # Number of memory references committed
system.cpu2.commit.loads 5265318 # Number of loads committed
system.cpu2.commit.membars 160044 # Number of memory barriers committed
system.cpu2.commit.branches 27319158 # Number of branches committed
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu2.commit.int_insts 244126615 # Number of committed integer instructions.
system.cpu2.commit.function_calls 428007 # Number of function calls committed.
system.cpu2.commit.op_class_0::No_OpClass 46777 0.02% 0.02% # Class of committed instruction
system.cpu2.commit.op_class_0::IntAlu 258753265 96.83% 96.84% # Class of committed instruction
system.cpu2.commit.op_class_0::IntMult 52699 0.02% 96.86% # Class of committed instruction
system.cpu2.commit.op_class_0::IntDiv 47480 0.02% 96.88% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.88% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.88% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 96.88% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.88% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.88% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.88% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.88% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.88% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.88% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.88% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.88% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.88% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.88% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.88% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.88% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.88% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.88% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.88% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.88% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.88% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.88% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.88% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.88% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.88% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.88% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.88% # Class of committed instruction
system.cpu2.commit.op_class_0::MemRead 5265283 1.97% 98.85% # Class of committed instruction
system.cpu2.commit.op_class_0::MemWrite 3068658 1.15% 100.00% # Class of committed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu2.commit.op_class_0::total 267234162 # Class of committed instruction
system.cpu2.commit.bw_lim_events 1961773 # number cycles where commit BW limit reached
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.cpu2.rob.rob_reads 425310506 # The number of ROB reads
system.cpu2.rob.rob_writes 553158006 # The number of ROB writes
system.cpu2.timesIdled 113704 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles 991020 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles 4914719574 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts 135487364 # Number of Instructions Simulated
system.cpu2.committedOps 267234162 # Number of Ops (including micro ops) Simulated
system.cpu2.cpi 1.134243 # CPI: Cycles Per Instruction
system.cpu2.cpi_total 1.134243 # CPI: Total CPI of All Threads
system.cpu2.ipc 0.881645 # IPC: Instructions Per Cycle
system.cpu2.ipc_total 0.881645 # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads 363574277 # number of integer regfile reads
system.cpu2.int_regfile_writes 217910153 # number of integer regfile writes
system.cpu2.fp_regfile_reads 72980 # number of floating regfile reads
system.cpu2.fp_regfile_writes 73024 # number of floating regfile writes
system.cpu2.cc_regfile_reads 138812774 # number of cc regfile reads
system.cpu2.cc_regfile_writes 106705933 # number of cc regfile writes
system.cpu2.misc_regfile_reads 88766274 # number of misc regfile reads
system.cpu2.misc_regfile_writes 139734 # number of misc regfile writes
system.iobus.trans_dist::ReadReq 3554581 # Transaction distribution
system.iobus.trans_dist::ReadResp 3554581 # Transaction distribution
system.iobus.trans_dist::WriteReq 57732 # Transaction distribution
system.iobus.trans_dist::WriteResp 11012 # Transaction distribution
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iobus.trans_dist::MessageReq 1688 # Transaction distribution
system.iobus.trans_dist::MessageResp 1688 # Transaction distribution
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7085054 # Packet count per connected master and slave (bytes)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1126 # Packet count per connected master and slave (bytes)
x86: Update stats for the new Linux delay port.
2014-11-22 02:22:19 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27910 # Packet count per connected master and slave (bytes)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iobus.pkt_count_system.bridge.master::total 7129380 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95246 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95246 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3376 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3376 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 7228002 # Packet count per connected master and slave (bytes)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3542527 # Cumulative packet size per connected master and slave (bytes)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2252 # Cumulative packet size per connected master and slave (bytes)
x86: Update stats for the new Linux delay port.
2014-11-22 02:22:19 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13955 # Cumulative packet size per connected master and slave (bytes)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iobus.pkt_size_system.bridge.master::total 3570850 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027768 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027768 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6752 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6752 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 6605370 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 2500128 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 27000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iobus.reqLayer3.occupancy 3583000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 4000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer5.occupancy 758000 # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.iobus.reqLayer6.occupancy 22000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iobus.reqLayer7.occupancy 12000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer9.occupancy 142528000 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iobus.reqLayer10.occupancy 318000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer11.occupancy 134000 # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iobus.reqLayer14.occupancy 10022000 # Layer occupancy (ticks)
x86: Update stats for the new Linux delay port.
2014-11-22 02:22:19 +01:00
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
x86: Update stats for the new Linux delay port.
2014-11-22 02:22:19 +01:00
system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iobus.reqLayer19.occupancy 273258249 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
x86: Update stats for the new Linux delay port.
2014-11-22 02:22:19 +01:00
system.iobus.reqLayer20.occupancy 1032000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iobus.respLayer0.occupancy 301483000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iobus.respLayer1.occupancy 28884002 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iobus.respLayer2.occupancy 1044000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iocache.tags.replacements 47568 # number of replacements
system.iocache.tags.tagsinuse 0.106184 # Cycle average of tags in use
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iocache.tags.sampled_refs 47584 # Sample count of references to valid blocks.
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iocache.tags.warmup_cycle 5000571396009 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.106184 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006636 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.006636 # Average percentage of cache occupancy
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iocache.tags.tag_accesses 428607 # Number of tag accesses
system.iocache.tags.data_accesses 428607 # Number of data accesses
system.iocache.ReadReq_misses::pc.south_bridge.ide 903 # number of ReadReq misses
system.iocache.ReadReq_misses::total 903 # number of ReadReq misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iocache.demand_misses::pc.south_bridge.ide 903 # number of demand (read+write) misses
system.iocache.demand_misses::total 903 # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide 903 # number of overall misses
system.iocache.overall_misses::total 903 # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 21110907 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 21110907 # number of ReadReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 7547175340 # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total 7547175340 # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide 21110907 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 21110907 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide 21110907 # number of overall miss cycles
system.iocache.overall_miss_latency::total 21110907 # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide 903 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 903 # number of ReadReq accesses(hits+misses)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iocache.demand_accesses::pc.south_bridge.ide 903 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 903 # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide 903 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 903 # number of overall (read+write) accesses
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 23378.634551 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 23378.634551 # average ReadReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 161540.568065 # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 161540.568065 # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 23378.634551 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 23378.634551 # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 23378.634551 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 23378.634551 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 42516 # number of cycles access was blocked
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iocache.blocked::no_mshrs 5560 # number of cycles access was blocked
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iocache.avg_blocked_cycles::no_mshrs 7.646763 # average number of cycles each access was blocked
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.fast_writes 0 # number of fast writes performed
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.cache_copies 0 # number of cache copies performed
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.writebacks::writebacks 46667 # number of writebacks
system.iocache.writebacks::total 46667 # number of writebacks
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 186 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 186 # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 28512 # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total 28512 # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide 186 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 186 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide 186 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 186 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 11438907 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 11438907 # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 6064547344 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6064547344 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 11438907 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 11438907 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 11438907 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 11438907 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.205980 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 0.205980 # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.610274 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.610274 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.205980 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 0.205980 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.205980 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 0.205980 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 61499.500000 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 61499.500000 # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212701.576319 # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212701.576319 # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 61499.500000 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 61499.500000 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 61499.500000 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 61499.500000 # average overall mshr miss latency
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.l2c.tags.replacements 104912 # number of replacements
system.l2c.tags.tagsinuse 64826.396555 # Cycle average of tags in use
system.l2c.tags.total_refs 3699624 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 169121 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 21.875604 # Average number of references to valid blocks.
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.l2c.tags.occ_blocks::writebacks 51247.277585 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.131369 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 1719.764589 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 5034.334216 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 0.003270 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 365.232722 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 1988.868841 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.dtb.walker 6.547985 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst 847.123033 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data 3617.112946 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.781971 # Average percentage of cache occupancy
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.l2c.tags.occ_percent::cpu0.inst 0.026242 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.076818 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.005573 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.030348 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000100 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst 0.012926 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data 0.055193 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.989172 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024 64209 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 571 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 3164 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 7713 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 52703 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024 0.979752 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 33891817 # Number of tag accesses
system.l2c.tags.data_accesses 33891817 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 20180 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 10473 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 308266 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 489820 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 12327 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 6781 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 172994 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 227559 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.dtb.walker 57791 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.itb.walker 13812 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst 370398 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data 597307 # number of ReadReq hits
system.l2c.ReadReq_hits::total 2287708 # number of ReadReq hits
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits
system.l2c.WriteReq_hits::total 2 # number of WriteReq hits
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.l2c.Writeback_hits::writebacks 1548383 # number of Writeback hits
system.l2c.Writeback_hits::total 1548383 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 79 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 91 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data 107 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 277 # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 53903 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 38692 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data 68887 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 161482 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 20180 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 10475 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 308266 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 543723 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 12327 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 6781 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 172994 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 266251 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.dtb.walker 57791 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.itb.walker 13812 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst 370398 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data 666194 # number of demand (read+write) hits
system.l2c.demand_hits::total 2449192 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 20180 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 10475 # number of overall hits
system.l2c.overall_hits::cpu0.inst 308266 # number of overall hits
system.l2c.overall_hits::cpu0.data 543723 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 12327 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 6781 # number of overall hits
system.l2c.overall_hits::cpu1.inst 172994 # number of overall hits
system.l2c.overall_hits::cpu1.data 266251 # number of overall hits
system.l2c.overall_hits::cpu2.dtb.walker 57791 # number of overall hits
system.l2c.overall_hits::cpu2.itb.walker 13812 # number of overall hits
system.l2c.overall_hits::cpu2.inst 370398 # number of overall hits
system.l2c.overall_hits::cpu2.data 666194 # number of overall hits
system.l2c.overall_hits::total 2449192 # number of overall hits
system.l2c.ReadReq_misses::cpu0.itb.walker 4 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst 6631 # number of ReadReq misses
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system.l2c.ReadReq_misses::cpu1.inst 2560 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 5303 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.dtb.walker 31 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst 5931 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data 11301 # number of ReadReq misses
system.l2c.ReadReq_misses::total 47975 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 511 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 312 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data 553 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 1376 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 66263 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 28768 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data 35396 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 130427 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 6631 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 82476 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 2560 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 34071 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.dtb.walker 31 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst 5931 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data 46697 # number of demand (read+write) misses
system.l2c.demand_misses::total 178402 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.itb.walker 4 # number of overall misses
system.l2c.overall_misses::cpu0.inst 6631 # number of overall misses
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system.l2c.overall_misses::cpu1.inst 2560 # number of overall misses
system.l2c.overall_misses::cpu1.data 34071 # number of overall misses
system.l2c.overall_misses::cpu2.dtb.walker 31 # number of overall misses
system.l2c.overall_misses::cpu2.inst 5931 # number of overall misses
system.l2c.overall_misses::cpu2.data 46697 # number of overall misses
system.l2c.overall_misses::total 178402 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu1.itb.walker 284500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 189834750 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 401835750 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 2798250 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst 462159250 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data 899751250 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 1956663750 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 4146362 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data 6070248 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 10216610 # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 1977655692 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data 2547627717 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 4525283409 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker 284500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 189834750 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 2379491442 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.dtb.walker 2798250 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst 462159250 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data 3447378967 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 6481947159 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker 284500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 189834750 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 2379491442 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.dtb.walker 2798250 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst 462159250 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data 3447378967 # number of overall miss cycles
system.l2c.overall_miss_latency::total 6481947159 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 20180 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 10477 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 314897 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 506033 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 12327 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 6782 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 175554 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 232862 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.dtb.walker 57822 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.itb.walker 13812 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst 376329 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data 608608 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 2335683 # number of ReadReq accesses(hits+misses)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.l2c.WriteReq_accesses::cpu0.itb.walker 2 # number of WriteReq accesses(hits+misses)
system.l2c.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.l2c.Writeback_accesses::writebacks 1548383 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 1548383 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 590 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 403 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data 660 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 1653 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 120166 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 67460 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data 104283 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 291909 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 20180 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 10479 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 314897 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 626199 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 12327 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 6782 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 175554 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 300322 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.dtb.walker 57822 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.itb.walker 13812 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst 376329 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data 712891 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 2627594 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 20180 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 10479 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 314897 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 626199 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 12327 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 6782 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 175554 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 300322 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.dtb.walker 57822 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.itb.walker 13812 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst 376329 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data 712891 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2627594 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000382 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.021058 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.032039 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000147 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.014582 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.022773 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000536 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst 0.015760 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data 0.018569 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.020540 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.866102 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.774194 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data 0.837879 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.832426 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.551429 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.426445 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data 0.339423 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.446807 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.000382 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.021058 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.131709 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker 0.000147 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.014582 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.113448 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000536 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst 0.015760 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data 0.065504 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.067896 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.000382 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.021058 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.131709 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker 0.000147 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.014582 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.113448 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000536 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst 0.015760 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data 0.065504 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.067896 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 284500 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 74154.199219 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 75775.174430 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 90266.129032 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 77922.652167 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data 79616.958676 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 40785.070349 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 13289.621795 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 10976.940325 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 7424.861919 # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68744.983732 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 71975.017431 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 34695.909658 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 284500 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 74154.199219 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 69839.201726 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 90266.129032 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 77922.652167 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 73824.420562 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 36333.377199 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 284500 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 74154.199219 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 69839.201726 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 90266.129032 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 77922.652167 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 73824.420562 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 36333.377199 # average overall miss latency
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.l2c.writebacks::writebacks 96648 # number of writebacks
system.l2c.writebacks::total 96648 # number of writebacks
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.l2c.ReadReq_mshr_hits::cpu2.data 1 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu2.data 1 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu2.data 1 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst 2560 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 5303 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 31 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.inst 5931 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.data 11300 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 25126 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 312 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data 553 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 865 # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 28768 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data 35396 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 64164 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 2560 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 34071 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.dtb.walker 31 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst 5931 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data 46696 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 89290 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 2560 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 34071 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.dtb.walker 31 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst 5931 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data 46696 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 89290 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 272000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 157363750 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 335556250 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 2417750 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 387910250 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data 758972250 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 1642492250 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 3770799 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 5695048 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 9465847 # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1607962308 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 2093715283 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 3701677591 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 272000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 157363750 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 1943518558 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 2417750 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst 387910250 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data 2852687533 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 5344169841 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 272000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 157363750 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 1943518558 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 2417750 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst 387910250 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data 2852687533 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 5344169841 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 27950237000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30169349000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 58119586000 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 553626000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 546753000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 1100379000 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28503863000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data 30716102000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 59219965000 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000147 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014582 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.022773 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000536 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.015760 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.018567 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.010757 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.774194 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.837879 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.523291 # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.426445 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.339423 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.219808 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000147 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014582 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.113448 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000536 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.015760 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data 0.065502 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.033982 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000147 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014582 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.113448 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000536 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.015760 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data 0.065502 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.033982 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 272000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61470.214844 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63276.683010 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 77991.935484 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 65403.852639 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 67165.685841 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 65370.224071 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 12085.894231 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10298.459313 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10943.175723 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55894.129171 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 59151.183269 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 57690.879481 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 272000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61470.214844 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57043.190925 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 77991.935484 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 65403.852639 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 61090.618747 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 59851.829331 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 272000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61470.214844 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57043.190925 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 77991.935484 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 65403.852639 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 61090.618747 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 59851.829331 # average overall mshr miss latency
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.membus.trans_dist::ReadReq 5122016 # Transaction distribution
system.membus.trans_dist::ReadResp 5122015 # Transaction distribution
system.membus.trans_dist::WriteReq 13950 # Transaction distribution
system.membus.trans_dist::WriteResp 13950 # Transaction distribution
system.membus.trans_dist::Writeback 143315 # Transaction distribution
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.membus.trans_dist::UpgradeReq 1630 # Transaction distribution
system.membus.trans_dist::UpgradeResp 1630 # Transaction distribution
system.membus.trans_dist::ReadExReq 130173 # Transaction distribution
system.membus.trans_dist::ReadExResp 130173 # Transaction distribution
system.membus.trans_dist::MessageReq 1688 # Transaction distribution
system.membus.trans_dist::MessageResp 1688 # Transaction distribution
system.membus.trans_dist::BadAddressError 1 # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3376 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total 3376 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7129380 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3044798 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 455864 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 2 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 10630044 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141727 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 141727 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 10775147 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6752 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::total 6752 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3570850 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6089593 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17566400 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 27226843 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6022656 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 6022656 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 33256251 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 522 # Total snoops (count)
system.membus.snoop_fanout::samples 370715 # Request fanout histogram
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.membus.snoop_fanout::1 370715 100.00% 100.00% # Request fanout histogram
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.membus.snoop_fanout::total 370715 # Request fanout histogram
system.membus.reqLayer0.occupancy 161293000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.membus.reqLayer1.occupancy 314500500 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.membus.reqLayer2.occupancy 2088000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.membus.reqLayer3.occupancy 1165884999 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks)
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.membus.respLayer0.occupancy 1044000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.membus.respLayer2.occupancy 1714039312 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.membus.respLayer4.occupancy 30187998 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.toL2Bus.trans_dist::ReadReq 7445356 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 7445355 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 13952 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 13952 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 1548383 # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq 28512 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 1653 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 1653 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 291909 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 291909 # Transaction distribution
system.toL2Bus.trans_dist::BadAddressError 1 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1733601 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 15004877 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 73054 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 211316 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 17022848 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 55474752 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213691163 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 265608 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 747576 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 270179099 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 79089 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 4261601 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 3.011175 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.105119 # Request fanout histogram
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.toL2Bus.snoop_fanout::3 4213978 98.88% 98.88% # Request fanout histogram
system.toL2Bus.snoop_fanout::4 47623 1.12% 100.00% # Request fanout histogram
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.toL2Bus.snoop_fanout::total 4261601 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 5362619847 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.toL2Bus.snoopLayer0.occupancy 837000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.toL2Bus.respLayer0.occupancy 2486663092 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.toL2Bus.respLayer1.occupancy 4974743955 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.toL2Bus.respLayer2.occupancy 27294890 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.toL2Bus.respLayer3.occupancy 94899067 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
x86: regressions: add switcher full test
2013-04-23 07:03:09 +02:00
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
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