2011-01-18 23:30:06 +01:00
---------- Begin Simulation Statistics ----------
2015-11-06 09:26:50 +01:00
sim_seconds 0.000019 # Number of seconds simulated
2016-04-08 18:01:45 +02:00
sim_ticks 18821000 # Number of ticks simulated
final_tick 18821000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2011-01-18 23:30:06 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
2016-06-06 18:16:44 +02:00
host_inst_rate 84019 # Simulator instruction rate (inst/s)
host_op_rate 98384 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 344256847 # Simulator tick rate (ticks/s)
host_mem_usage 306884 # Number of bytes of host memory used
host_seconds 0.05 # Real time elapsed on the host
2015-04-30 21:17:43 +02:00
sim_insts 4592 # Number of instructions simulated
sim_ops 5378 # Number of ops (including micro ops) simulated
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2016-06-06 18:16:44 +02:00
system.physmem.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states
2016-04-08 18:01:45 +02:00
system.physmem.bytes_read::cpu.inst 18560 # Number of bytes read from this memory
2015-11-06 09:26:50 +01:00
system.physmem.bytes_read::cpu.data 8064 # Number of bytes read from this memory
2014-12-23 15:31:20 +01:00
system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 # Number of bytes read from this memory
2016-04-08 18:01:45 +02:00
system.physmem.bytes_read::total 28352 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 18560 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 18560 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 290 # Number of read requests responded to by this memory
2015-11-06 09:26:50 +01:00
system.physmem.num_reads::cpu.data 126 # Number of read requests responded to by this memory
2014-12-23 15:31:20 +01:00
system.physmem.num_reads::cpu.l2cache.prefetcher 27 # Number of read requests responded to by this memory
2016-04-08 18:01:45 +02:00
system.physmem.num_reads::total 443 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 986132512 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 428457574 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher 91812337 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1506402423 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 986132512 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 986132512 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 986132512 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 428457574 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher 91812337 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1506402423 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 443 # Number of read requests accepted
2013-11-01 16:56:34 +01:00
system.physmem.writeReqs 0 # Number of write requests accepted
2016-04-08 18:01:45 +02:00
system.physmem.readBursts 443 # Number of DRAM read bursts, including those serviced by the write queue
2013-11-01 16:56:34 +01:00
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
2016-04-08 18:01:45 +02:00
system.physmem.bytesReadDRAM 28352 # Total number of bytes read from DRAM
2013-11-01 16:56:34 +01:00
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
2016-04-08 18:01:45 +02:00
system.physmem.bytesReadSys 28352 # Total read bytes from the system interface side
2013-11-01 16:56:34 +01:00
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
2015-11-06 09:26:50 +01:00
system.physmem.perBankRdBursts::0 101 # Per bank write bursts
system.physmem.perBankRdBursts::1 48 # Per bank write bursts
2014-12-23 15:31:20 +01:00
system.physmem.perBankRdBursts::2 19 # Per bank write bursts
2016-04-08 18:01:45 +02:00
system.physmem.perBankRdBursts::3 45 # Per bank write bursts
2015-11-06 09:26:50 +01:00
system.physmem.perBankRdBursts::4 19 # Per bank write bursts
system.physmem.perBankRdBursts::5 37 # Per bank write bursts
system.physmem.perBankRdBursts::6 46 # Per bank write bursts
2014-12-23 15:31:20 +01:00
system.physmem.perBankRdBursts::7 10 # Per bank write bursts
system.physmem.perBankRdBursts::8 4 # Per bank write bursts
2015-11-06 09:26:50 +01:00
system.physmem.perBankRdBursts::9 8 # Per bank write bursts
system.physmem.perBankRdBursts::10 27 # Per bank write bursts
2014-09-20 23:18:53 +02:00
system.physmem.perBankRdBursts::11 47 # Per bank write bursts
system.physmem.perBankRdBursts::12 17 # Per bank write bursts
2015-11-06 09:26:50 +01:00
system.physmem.perBankRdBursts::13 8 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.perBankRdBursts::14 0 # Per bank write bursts
2015-11-06 09:26:50 +01:00
system.physmem.perBankRdBursts::15 7 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
2016-04-08 18:01:45 +02:00
system.physmem.totGap 18779500 # Total gap between requests
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2016-04-08 18:01:45 +02:00
system.physmem.readPktSize::6 443 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
2016-04-08 18:01:45 +02:00
system.physmem.rdQLenPdf::0 246 # What read queue length does an incoming req see
2015-11-06 09:26:50 +01:00
system.physmem.rdQLenPdf::1 134 # What read queue length does an incoming req see
2016-04-08 18:01:45 +02:00
system.physmem.rdQLenPdf::2 34 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see
2015-11-06 09:26:50 +01:00
system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
2015-03-02 11:04:20 +01:00
system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
2015-07-30 09:42:27 +02:00
system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see
2014-12-23 15:31:20 +01:00
system.physmem.rdQLenPdf::7 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 2 # What read queue length does an incoming req see
2015-07-30 09:42:27 +02:00
system.physmem.rdQLenPdf::9 2 # What read queue length does an incoming req see
2014-12-23 15:31:20 +01:00
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
2015-11-06 09:26:50 +01:00
system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation
2016-04-08 18:01:45 +02:00
system.physmem.bytesPerActivate::mean 427.682540 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 292.140083 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 354.445538 # Bytes accessed per row activation
2015-11-06 09:26:50 +01:00
system.physmem.bytesPerActivate::0-127 7 11.11% 11.11% # Bytes accessed per row activation
2016-04-08 18:01:45 +02:00
system.physmem.bytesPerActivate::128-255 18 28.57% 39.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 11 17.46% 57.14% # Bytes accessed per row activation
2015-11-06 09:26:50 +01:00
system.physmem.bytesPerActivate::384-511 7 11.11% 68.25% # Bytes accessed per row activation
2016-04-08 18:01:45 +02:00
system.physmem.bytesPerActivate::512-639 1 1.59% 69.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 4 6.35% 76.19% # Bytes accessed per row activation
2015-11-06 09:26:50 +01:00
system.physmem.bytesPerActivate::768-895 1 1.59% 77.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 2 3.17% 80.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 12 19.05% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation
2016-04-08 18:01:45 +02:00
system.physmem.totQLat 3401243 # Total ticks spent queuing
system.physmem.totMemAccLat 11707493 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2215000 # Total ticks spent in databus transfers
system.physmem.avgQLat 7677.75 # Average queueing delay per DRAM burst
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2016-04-08 18:01:45 +02:00
system.physmem.avgMemAccLat 26427.75 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1506.40 # Average DRAM read bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
2016-04-08 18:01:45 +02:00
system.physmem.avgRdBWSys 1506.40 # Average system read bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2016-04-08 18:01:45 +02:00
system.physmem.busUtil 11.77 # Data bus utilization in percentage
system.physmem.busUtilRead 11.77 # Data bus utilization in percentage for reads
2013-11-01 16:56:34 +01:00
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
2016-04-08 18:01:45 +02:00
system.physmem.avgRdQLen 1.80 # Average read queue length when enqueuing
2013-11-01 16:56:34 +01:00
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
2016-04-08 18:01:45 +02:00
system.physmem.readRowHits 371 # Number of row buffer hits during reads
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
2016-04-08 18:01:45 +02:00
system.physmem.readRowHitRate 83.75 # Row buffer hit rate for reads
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
2016-04-08 18:01:45 +02:00
system.physmem.avgGap 42391.65 # Average gap between requests
system.physmem.pageHitRate 83.75 # Row buffer hit rate, read and write combined
2015-04-30 21:17:43 +02:00
system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ)
2015-11-06 09:26:50 +01:00
system.physmem_0.readEnergy 2160600 # Energy for read commands per rank (pJ)
2014-12-23 15:31:20 +01:00
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
2016-04-08 18:01:45 +02:00
system.physmem_0.actBackEnergy 10755900 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 64500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 14453835 # Total energy per rank (pJ)
system.physmem_0.averagePower 912.921838 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 51750 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::REF 520000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
2016-04-08 18:01:45 +02:00
system.physmem_0.memoryStateTime::ACT 15274500 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
2015-03-02 11:04:20 +01:00
system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ)
2015-11-06 09:26:50 +01:00
system.physmem_1.readEnergy 811200 # Energy for read commands per rank (pJ)
2014-12-23 15:31:20 +01:00
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
2016-04-08 18:01:45 +02:00
system.physmem_1.actBackEnergy 10734525 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 83250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 12844740 # Total energy per rank (pJ)
system.physmem_1.averagePower 811.289436 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 945250 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::REF 520000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
2016-04-08 18:01:45 +02:00
system.physmem_1.memoryStateTime::ACT 15229250 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
2016-06-06 18:16:44 +02:00
system.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states
2016-04-08 18:01:45 +02:00
system.cpu.branchPred.lookups 2438 # Number of BP lookups
system.cpu.branchPred.condPredicted 1442 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 524 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 915 # Number of BTB lookups
system.cpu.branchPred.BTBHits 449 # Number of BTB hits
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2016-04-08 18:01:45 +02:00
system.cpu.branchPred.BTBHitPct 49.071038 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 286 # Number of times the RAS was used to get a target.
2015-11-06 09:26:50 +01:00
system.cpu.branchPred.RASInCorrect 57 # Number of incorrect RAS predictions.
2016-04-08 18:01:45 +02:00
system.cpu.branchPred.indirectLookups 163 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 13 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 150 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 60 # Number of mispredicted indirect branches.
2014-12-23 15:31:20 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2016-06-06 18:16:44 +02:00
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-06-06 18:16:44 +02:00
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2011-05-23 17:59:13 +02:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
2016-06-06 18:16:44 +02:00
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-06-06 18:16:44 +02:00
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2011-05-23 17:59:13 +02:00
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 13 # Number of system calls
2016-06-06 18:16:44 +02:00
system.cpu.pwrStateResidencyTicks::ON 18821000 # Cumulative time (in ticks) in various power states
2016-04-08 18:01:45 +02:00
system.cpu.numCycles 37643 # number of cpu cycles simulated
2011-05-23 17:59:13 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
2016-04-08 18:01:45 +02:00
system.cpu.fetch.icacheStallCycles 6083 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 11454 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2438 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 748 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 8291 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1091 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 169 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 272 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 412 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 3904 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 178 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 15772 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.863365 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.208800 # Number of instructions fetched each cycle (Total)
2011-05-23 17:59:13 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2016-04-08 18:01:45 +02:00
system.cpu.fetch.rateDist::0 9389 59.53% 59.53% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 2507 15.90% 75.42% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 518 3.28% 78.71% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 3358 21.29% 100.00% # Number of instructions fetched each cycle (Total)
2011-05-23 17:59:13 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
2014-09-20 23:18:53 +02:00
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
2016-04-08 18:01:45 +02:00
system.cpu.fetch.rateDist::total 15772 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.064766 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.304280 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 5832 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 4243 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 5178 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 133 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 386 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 373 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 161 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 10169 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 1675 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 386 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 6945 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 1086 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 2318 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 4187 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 850 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 9093 # Number of instructions processed by rename
system.cpu.rename.SquashedInsts 454 # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents 23 # Number of times rename has blocked due to ROB full
2015-04-30 21:17:43 +02:00
system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full
2015-11-06 09:26:50 +01:00
system.cpu.rename.LQFullEvents 28 # Number of times rename has blocked due to LQ full
2016-04-08 18:01:45 +02:00
system.cpu.rename.SQFullEvents 744 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 9450 # Number of destination operands rename has renamed
2016-06-02 15:14:36 +02:00
system.cpu.rename.RenameLookups 41121 # Number of register rename lookups that rename has made
2016-04-08 18:01:45 +02:00
system.cpu.rename.int_rename_lookups 9999 # Number of integer rename lookups
2015-03-02 11:04:20 +01:00
system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups
2014-09-03 13:42:59 +02:00
system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed
2016-04-08 18:01:45 +02:00
system.cpu.rename.UndoneMaps 3956 # Number of HB maps that are undone due to squashing
2015-11-06 09:26:50 +01:00
system.cpu.rename.serializingInsts 29 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed
2016-04-08 18:01:45 +02:00
system.cpu.rename.skidInsts 331 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 1823 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1291 # Number of stores inserted to the mem dependence unit.
2014-09-20 23:18:53 +02:00
system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
2016-04-08 18:01:45 +02:00
system.cpu.iq.iqInstsAdded 8515 # Number of instructions added to the IQ (excludes non-spec)
2015-11-06 09:26:50 +01:00
system.cpu.iq.iqNonSpecInstsAdded 38 # Number of non-speculative instructions added to the IQ
2016-04-08 18:01:45 +02:00
system.cpu.iq.iqInstsIssued 7234 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 175 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 3175 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 8237 # Number of squashed operands that are examined and possibly removed from graph
2015-11-06 09:26:50 +01:00
system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed
2016-04-08 18:01:45 +02:00
system.cpu.iq.issued_per_cycle::samples 15772 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.458661 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 0.847067 # Number of insts issued each cycle
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2016-04-08 18:01:45 +02:00
system.cpu.iq.issued_per_cycle::0 11502 72.93% 72.93% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 1999 12.67% 85.60% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 1621 10.28% 95.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 607 3.85% 99.73% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 43 0.27% 100.00% # Number of insts issued each cycle
2014-09-20 23:18:53 +02:00
system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
2014-09-20 23:18:53 +02:00
system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle
2016-04-08 18:01:45 +02:00
system.cpu.iq.issued_per_cycle::total 15772 # Number of insts issued each cycle
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2016-04-08 18:01:45 +02:00
system.cpu.iq.fu_full::IntAlu 415 28.78% 28.78% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 28.78% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 28.78% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.78% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.78% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.78% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 28.78% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.78% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 28.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 28.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.78% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.78% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 474 32.87% 61.65% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 553 38.35% 100.00% # attempts to use FU when none available
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
2016-04-08 18:01:45 +02:00
system.cpu.iq.FU_type_0::IntAlu 4534 62.68% 62.68% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.75% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.75% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.75% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.75% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.75% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.75% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.75% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.75% # Type of FU issued
2015-11-06 09:26:50 +01:00
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.79% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.79% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.79% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.79% # Type of FU issued
2016-04-08 18:01:45 +02:00
system.cpu.iq.FU_type_0::MemRead 1605 22.19% 84.97% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 1087 15.03% 100.00% # Type of FU issued
2011-05-23 17:59:13 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2016-04-08 18:01:45 +02:00
system.cpu.iq.FU_type_0::total 7234 # Type of FU issued
system.cpu.iq.rate 0.192174 # Inst issue rate
system.cpu.iq.fu_busy_cnt 1442 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.199336 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 31813 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 11719 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 6621 # Number of integer instruction queue wakeup accesses
2014-12-23 15:31:20 +01:00
system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads
2015-03-02 11:04:20 +01:00
system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
2014-09-20 23:18:53 +02:00
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
2016-04-08 18:01:45 +02:00
system.cpu.iq.int_alu_accesses 8648 # Number of integer alu accesses
2014-12-23 15:31:20 +01:00
system.cpu.iq.fp_alu_accesses 28 # Number of floating point alu accesses
2015-11-06 09:26:50 +01:00
system.cpu.iew.lsq.thread0.forwLoads 11 # Number of loads that had data forwarded from stores
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2016-04-08 18:01:45 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 796 # Number of loads squashed
2014-12-23 15:31:20 +01:00
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
2014-09-20 23:18:53 +02:00
system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations
2016-04-08 18:01:45 +02:00
system.cpu.iew.lsq.thread0.squashedStores 353 # Number of stores squashed
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2016-04-08 18:01:45 +02:00
system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled
2015-03-02 11:04:20 +01:00
system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked
2011-05-23 17:59:13 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2016-04-08 18:01:45 +02:00
system.cpu.iew.iewSquashCycles 386 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 336 # Number of cycles IEW is blocking
2015-11-06 09:26:50 +01:00
system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking
2016-04-08 18:01:45 +02:00
system.cpu.iew.iewDispatchedInsts 8566 # Number of instructions dispatched to IQ
2014-09-20 23:18:53 +02:00
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
2016-04-08 18:01:45 +02:00
system.cpu.iew.iewDispLoadInsts 1823 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 1291 # Number of dispatched store instructions
2015-11-06 09:26:50 +01:00
system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
2015-07-03 16:15:03 +02:00
system.cpu.iew.iewLSQFullEvents 6 # Number of times the LSQ has become full, causing a stall
2014-09-20 23:18:53 +02:00
system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations
2016-04-08 18:01:45 +02:00
system.cpu.iew.predictedTakenIncorrect 59 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 319 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 6824 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 1421 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 410 # Number of squashed instructions skipped in execute
2011-05-23 17:59:13 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
2016-04-08 18:01:45 +02:00
system.cpu.iew.exec_nop 13 # number of nop insts executed
system.cpu.iew.exec_refs 2451 # number of memory reference insts executed
system.cpu.iew.exec_branches 1299 # Number of branches executed
system.cpu.iew.exec_stores 1030 # Number of stores executed
system.cpu.iew.exec_rate 0.181282 # Inst execution rate
system.cpu.iew.wb_sent 6681 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 6637 # cumulative count of insts written-back
system.cpu.iew.wb_producers 2986 # num instructions producing a value
system.cpu.iew.wb_consumers 5424 # num instructions consuming a value
system.cpu.iew.wb_rate 0.176314 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.550516 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 2706 # The number of squashed insts skipped by commit
2013-01-08 14:54:16 +01:00
system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards
2016-04-08 18:01:45 +02:00
system.cpu.commit.branchMispredicts 365 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 15204 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.353723 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 0.993092 # Number of insts commited each cycle
2011-04-20 03:45:23 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2016-04-08 18:01:45 +02:00
system.cpu.commit.committed_per_cycle::0 12538 82.47% 82.47% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 1405 9.24% 91.71% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 597 3.93% 95.63% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 300 1.97% 97.61% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 170 1.12% 98.72% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 79 0.52% 99.24% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 44 0.29% 99.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 28 0.18% 99.72% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 43 0.28% 100.00% # Number of insts commited each cycle
2011-04-20 03:45:23 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2016-04-08 18:01:45 +02:00
system.cpu.commit.committed_per_cycle::total 15204 # Number of insts commited each cycle
2015-04-30 21:17:43 +02:00
system.cpu.commit.committedInsts 4592 # Number of instructions committed
system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed
2011-05-23 17:59:13 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
2014-09-03 13:42:59 +02:00
system.cpu.commit.refs 1965 # Number of memory references committed
system.cpu.commit.loads 1027 # Number of loads committed
2011-04-20 03:45:23 +02:00
system.cpu.commit.membars 12 # Number of memory barriers committed
2015-04-30 21:17:43 +02:00
system.cpu.commit.branches 1008 # Number of branches committed
2011-05-23 17:59:13 +02:00
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
2014-09-03 13:42:59 +02:00
system.cpu.commit.int_insts 4624 # Number of committed integer instructions.
2011-05-23 17:59:13 +02:00
system.cpu.commit.function_calls 82 # Number of function calls committed.
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2015-04-30 21:17:43 +02:00
system.cpu.commit.op_class_0::IntAlu 3406 63.33% 63.33% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 4 0.07% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.41% # Class of committed instruction
2014-09-03 13:42:59 +02:00
system.cpu.commit.op_class_0::SimdFloatMisc 3 0.06% 63.46% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2015-04-30 21:17:43 +02:00
system.cpu.commit.op_class_0::total 5378 # Class of committed instruction
2015-07-03 16:15:03 +02:00
system.cpu.commit.bw_lim_events 43 # number cycles where commit BW limit reached
2016-04-08 18:01:45 +02:00
system.cpu.rob.rob_reads 23088 # The number of ROB reads
system.cpu.rob.rob_writes 16743 # The number of ROB writes
system.cpu.timesIdled 215 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 21871 # Total number of cycles that the CPU has spent unscheduled due to idling
2015-04-30 21:17:43 +02:00
system.cpu.committedInsts 4592 # Number of Instructions Simulated
system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated
2016-04-08 18:01:45 +02:00
system.cpu.cpi 8.197517 # CPI: Cycles Per Instruction
system.cpu.cpi_total 8.197517 # CPI: Total CPI of All Threads
system.cpu.ipc 0.121988 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.121988 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 6777 # number of integer regfile reads
system.cpu.int_regfile_writes 3787 # number of integer regfile writes
2014-09-20 23:18:53 +02:00
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
2016-04-08 18:01:45 +02:00
system.cpu.cc_regfile_reads 24229 # number of cc regfile reads
system.cpu.cc_regfile_writes 2921 # number of cc regfile writes
2016-06-02 15:14:36 +02:00
system.cpu.misc_regfile_reads 2562 # number of misc regfile reads
2013-01-08 14:54:16 +01:00
system.cpu.misc_regfile_writes 24 # number of misc regfile writes
2016-06-06 18:16:44 +02:00
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.replacements 1 # number of replacements
2016-04-08 18:01:45 +02:00
system.cpu.dcache.tags.tagsinuse 84.368926 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1930 # Total number of references to valid blocks.
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks.
2016-04-08 18:01:45 +02:00
system.cpu.dcache.tags.avg_refs 13.496503 # Average number of references to valid blocks.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-04-08 18:01:45 +02:00
system.cpu.dcache.tags.occ_blocks::cpu.data 84.368926 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.164783 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.164783 # Average percentage of cache occupancy
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
2015-03-02 11:04:20 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 0.277344 # Percentage of cache occupancy per task id
2016-04-08 18:01:45 +02:00
system.cpu.dcache.tags.tag_accesses 4723 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 4723 # Number of data accesses
2016-06-06 18:16:44 +02:00
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states
2016-04-08 18:01:45 +02:00
system.cpu.dcache.ReadReq_hits::cpu.data 1188 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1188 # number of ReadReq hits
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
2016-04-08 18:01:45 +02:00
system.cpu.dcache.demand_hits::cpu.data 1910 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 1910 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 1910 # number of overall hits
system.cpu.dcache.overall_hits::total 1910 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 167 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 167 # number of ReadReq misses
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_misses::cpu.data 191 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 191 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
2016-04-08 18:01:45 +02:00
system.cpu.dcache.demand_misses::cpu.data 358 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 358 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 358 # number of overall misses
system.cpu.dcache.overall_misses::total 358 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 10679500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 10679500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 7608000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 7608000 # number of WriteReq miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 125000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 125000 # number of LoadLockedReq miss cycles
2016-04-08 18:01:45 +02:00
system.cpu.dcache.demand_miss_latency::cpu.data 18287500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 18287500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 18287500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 18287500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1355 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1355 # number of ReadReq accesses(hits+misses)
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
2016-04-08 18:01:45 +02:00
system.cpu.dcache.demand_accesses::cpu.data 2268 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2268 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2268 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2268 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.123247 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.123247 # miss rate for ReadReq accesses
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.209200 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.209200 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses
2016-04-08 18:01:45 +02:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.157848 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.157848 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.157848 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.157848 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63949.101796 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 63949.101796 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39832.460733 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 39832.460733 # average WriteReq miss latency
2015-11-06 09:26:50 +01:00
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62500 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62500 # average LoadLockedReq miss latency
2016-04-08 18:01:45 +02:00
system.cpu.dcache.demand_avg_miss_latency::cpu.data 51082.402235 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 51082.402235 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 51082.402235 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 51082.402235 # average overall miss latency
2014-12-23 15:31:20 +01:00
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2016-04-08 18:01:45 +02:00
system.cpu.dcache.blocked_cycles::no_targets 818 # number of cycles access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2016-04-08 18:01:45 +02:00
system.cpu.dcache.avg_blocked_cycles::no_targets 45.444444 # average number of cycles each access was blocked
2015-11-06 09:26:50 +01:00
system.cpu.dcache.writebacks::writebacks 1 # number of writebacks
system.cpu.dcache.writebacks::total 1 # number of writebacks
2016-04-08 18:01:45 +02:00
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 64 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 150 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 150 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
2016-04-08 18:01:45 +02:00
system.cpu.dcache.demand_mshr_hits::cpu.data 214 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 214 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 214 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 214 # number of overall MSHR hits
2015-11-06 09:26:50 +01:00
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 103 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.dcache.demand_mshr_misses::cpu.data 144 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses
2016-04-08 18:01:45 +02:00
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6934000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6934000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2433000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2433000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9367000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 9367000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9367000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 9367000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076015 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076015 # mshr miss rate for ReadReq accesses
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses
2016-04-08 18:01:45 +02:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063492 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.063492 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063492 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.063492 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67320.388350 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67320.388350 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59341.463415 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59341.463415 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65048.611111 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 65048.611111 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65048.611111 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 65048.611111 # average overall mshr miss latency
2016-06-06 18:16:44 +02:00
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states
2016-04-08 18:01:45 +02:00
system.cpu.icache.tags.replacements 44 # number of replacements
system.cpu.icache.tags.tagsinuse 137.890102 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 3540 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 299 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 11.839465 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-04-08 18:01:45 +02:00
system.cpu.icache.tags.occ_blocks::cpu.inst 137.890102 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.269317 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.269317 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 255 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 157 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id
2016-04-08 18:01:45 +02:00
system.cpu.icache.tags.occ_task_id_percent::1024 0.498047 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 8101 # Number of tag accesses
system.cpu.icache.tags.data_accesses 8101 # Number of data accesses
2016-06-06 18:16:44 +02:00
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states
2016-04-08 18:01:45 +02:00
system.cpu.icache.ReadReq_hits::cpu.inst 3540 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 3540 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 3540 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 3540 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 3540 # number of overall hits
system.cpu.icache.overall_hits::total 3540 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 361 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 361 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 361 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 361 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 361 # number of overall misses
system.cpu.icache.overall_misses::total 361 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 22435492 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 22435492 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 22435492 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 22435492 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 22435492 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 22435492 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 3901 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 3901 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 3901 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 3901 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 3901 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 3901 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092540 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.092540 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.092540 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.092540 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.092540 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.092540 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62148.177285 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 62148.177285 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 62148.177285 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 62148.177285 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 62148.177285 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 62148.177285 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 8414 # number of cycles access was blocked
2015-03-02 11:04:20 +01:00
system.cpu.icache.blocked_cycles::no_targets 33 # number of cycles access was blocked
2016-04-08 18:01:45 +02:00
system.cpu.icache.blocked::no_mshrs 95 # number of cycles access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
2016-04-08 18:01:45 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 88.568421 # average number of cycles each access was blocked
2015-03-02 11:04:20 +01:00
system.cpu.icache.avg_blocked_cycles::no_targets 33 # average number of cycles each access was blocked
2016-04-08 18:01:45 +02:00
system.cpu.icache.writebacks::writebacks 44 # number of writebacks
system.cpu.icache.writebacks::total 44 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 62 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 62 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 62 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 62 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 299 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 299 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 299 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 299 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 299 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19775992 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 19775992 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19775992 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 19775992 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19775992 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 19775992 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076647 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.076647 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.076647 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66140.441472 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66140.441472 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66140.441472 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 66140.441472 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66140.441472 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 66140.441472 # average overall mshr miss latency
2016-06-06 18:16:44 +02:00
system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
2016-06-06 18:16:44 +02:00
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.replacements 0 # number of replacements
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.tags.tagsinuse 19.806308 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 11 # Total number of references to valid blocks.
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.sampled_refs 48 # Sample count of references to valid blocks.
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.tags.avg_refs 0.229167 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.tags.occ_blocks::writebacks 10.572819 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.233490 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.000645 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000564 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.001209 # Average percentage of cache occupancy
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.tags.occ_task_id_blocks::1022 16 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32 # Occupied blocks per task id
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.tags.occ_task_id_percent::1022 0.000977 # Percentage of cache occupancy per task id
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.001953 # Percentage of cache occupancy per task id
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.tags.tag_accesses 7675 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 7675 # Number of data accesses
2016-06-06 18:16:44 +02:00
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.WritebackClean_hits::writebacks 33 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 33 # number of WritebackClean hits
2014-09-20 23:18:53 +02:00
system.cpu.l2cache.ReadExReq_hits::cpu.data 11 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 11 # number of ReadExReq hits
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 8 # number of ReadCleanReq hits
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 2 # number of ReadSharedReq hits
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.demand_hits::cpu.inst 8 # number of demand (read+write) hits
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_hits::cpu.data 13 # number of demand (read+write) hits
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.demand_hits::total 21 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 8 # number of overall hits
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_hits::cpu.data 13 # number of overall hits
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.overall_hits::total 21 # number of overall hits
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 30 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 30 # number of ReadExReq misses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 291 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 291 # number of ReadCleanReq misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 101 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 101 # number of ReadSharedReq misses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.demand_misses::cpu.inst 291 # number of demand (read+write) misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_misses::cpu.data 131 # number of demand (read+write) misses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.demand_misses::total 422 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 291 # number of overall misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_misses::cpu.data 131 # number of overall misses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.overall_misses::total 422 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2299000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 2299000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 19417500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 19417500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6760500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 6760500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 19417500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 9059500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 28477000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 19417500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 9059500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 28477000 # number of overall miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.WritebackClean_accesses::writebacks 33 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 33 # number of WritebackClean accesses(hits+misses)
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses)
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 299 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 299 # number of ReadCleanReq accesses(hits+misses)
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 103 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 103 # number of ReadSharedReq accesses(hits+misses)
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.demand_accesses::cpu.inst 299 # number of demand (read+write) accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_accesses::cpu.data 144 # number of demand (read+write) accesses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.demand_accesses::total 443 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 299 # number of overall (read+write) accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_accesses::cpu.data 144 # number of overall (read+write) accesses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.overall_accesses::total 443 # number of overall (read+write) accesses
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.731707 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.731707 # miss rate for ReadExReq accesses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.973244 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.973244 # miss rate for ReadCleanReq accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.980583 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.980583 # miss rate for ReadSharedReq accesses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.973244 # miss rate for demand accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_miss_rate::cpu.data 0.909722 # miss rate for demand accesses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.demand_miss_rate::total 0.952596 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.973244 # miss rate for overall accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_miss_rate::cpu.data 0.909722 # miss rate for overall accesses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.overall_miss_rate::total 0.952596 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76633.333333 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76633.333333 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 66726.804124 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 66726.804124 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 66935.643564 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 66935.643564 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66726.804124 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69156.488550 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 67481.042654 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66726.804124 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69156.488550 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 67481.042654 # average overall miss latency
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2013-01-07 19:05:54 +01:00
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
2013-01-07 19:05:54 +01:00
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2013-01-07 19:05:54 +01:00
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 5 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 5 # number of ReadSharedReq MSHR hits
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 53 # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total 53 # number of HardPFReq MSHR misses
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 30 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 30 # number of ReadExReq MSHR misses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 290 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 290 # number of ReadCleanReq MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 96 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 96 # number of ReadSharedReq MSHR misses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.demand_mshr_misses::cpu.inst 290 # number of demand (read+write) MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_mshr_misses::cpu.data 126 # number of demand (read+write) MSHR misses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.demand_mshr_misses::total 416 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 290 # number of overall MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_mshr_misses::cpu.data 126 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 53 # number of overall MSHR misses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1908926 # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1908926 # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2119000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2119000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 17622000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 17622000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5892000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5892000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17622000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8011000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 25633000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17622000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8011000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1908926 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 27541926 # number of overall MSHR miss cycles
2014-09-20 23:18:53 +02:00
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.731707 # mshr miss rate for ReadExReq accesses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.969900 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.969900 # mshr miss rate for ReadCleanReq accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.932039 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.932039 # mshr miss rate for ReadSharedReq accesses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.969900 # mshr miss rate for demand accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.875000 # mshr miss rate for demand accesses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::total 0.939052 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.969900 # mshr miss rate for overall accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.875000 # mshr miss rate for overall accesses
2014-09-20 23:18:53 +02:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.overall_mshr_miss_rate::total 1.058691 # mshr miss rate for overall accesses
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 36017.471698 # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 36017.471698 # average HardPFReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70633.333333 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70633.333333 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 60765.517241 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 60765.517241 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61375 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61375 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60765.517241 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63579.365079 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61617.788462 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60765.517241 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63579.365079 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 36017.471698 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58724.788913 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 488 # Total number of requests made to the snoop filter.
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoop_filter.hit_single_requests 74 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2016-04-08 18:01:45 +02:00
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 12 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 411 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 370 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 41 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-06-06 18:16:44 +02:00
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states
2016-04-08 18:01:45 +02:00
system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 45 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 385 # Transaction distribution
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.trans_dist::HardPFReq 69 # Transaction distribution
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution
2016-04-08 18:01:45 +02:00
system.cpu.toL2Bus.trans_dist::ReadCleanReq 299 # Transaction distribution
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution
2016-04-08 18:01:45 +02:00
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 642 # Packet count per connected master and slave (bytes)
2016-02-10 10:08:27 +01:00
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 288 # Packet count per connected master and slave (bytes)
2016-04-08 18:01:45 +02:00
system.cpu.toL2Bus.pkt_count::total 930 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21952 # Cumulative packet size per connected master and slave (bytes)
2016-02-10 10:08:27 +01:00
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9216 # Cumulative packet size per connected master and slave (bytes)
2016-04-08 18:01:45 +02:00
system.cpu.toL2Bus.pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 454 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 897 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.549610 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.582523 # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-04-08 18:01:45 +02:00
system.cpu.toL2Bus.snoop_fanout::0 445 49.61% 49.61% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 411 45.82% 95.43% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 41 4.57% 100.00% # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2016-04-08 18:01:45 +02:00
system.cpu.toL2Bus.snoop_fanout::total 897 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 289000 # Layer occupancy (ticks)
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%)
2016-04-08 18:01:45 +02:00
system.cpu.toL2Bus.respLayer0.occupancy 448999 # Layer occupancy (ticks)
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 216995 # Layer occupancy (ticks)
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%)
2016-06-06 18:16:44 +02:00
system.membus.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states
2016-04-08 18:01:45 +02:00
system.membus.trans_dist::ReadResp 412 # Transaction distribution
2014-12-23 15:31:20 +01:00
system.membus.trans_dist::ReadExReq 30 # Transaction distribution
system.membus.trans_dist::ReadExResp 30 # Transaction distribution
2016-04-08 18:01:45 +02:00
system.membus.trans_dist::ReadSharedReq 413 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 885 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 885 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28288 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 28288 # Cumulative packet size per connected master and slave (bytes)
2014-12-23 15:31:20 +01:00
system.membus.snoops 0 # Total snoops (count)
2016-04-08 18:01:45 +02:00
system.membus.snoop_fanout::samples 443 # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-04-08 18:01:45 +02:00
system.membus.snoop_fanout::0 443 100.00% 100.00% # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
2016-04-08 18:01:45 +02:00
system.membus.snoop_fanout::total 443 # Request fanout histogram
system.membus.reqLayer0.occupancy 561444 # Layer occupancy (ticks)
2015-11-06 09:26:50 +01:00
system.membus.reqLayer0.utilization 3.0 # Layer utilization (%)
2016-04-08 18:01:45 +02:00
system.membus.respLayer1.occupancy 2329257 # Layer occupancy (ticks)
2015-11-06 09:26:50 +01:00
system.membus.respLayer1.utilization 12.4 # Layer utilization (%)
2011-01-18 23:30:06 +01:00
---------- End Simulation Statistics ----------
