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gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt

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Add Alpha Linux version of "hello world" test. --HG-- extra : convert_revision : 22cd31c58f18fd92bd61ee4b4a218926f7290045
2006-08-21 04:48:30 +02:00
---------- Begin Simulation Statistics ----------
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
sim_seconds 0.000033 # Number of seconds simulated
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
sim_ticks 32544500 # Number of ticks simulated
final_tick 32544500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
host_inst_rate 643051 # Simulator instruction rate (inst/s)
host_op_rate 642147 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 3266208350 # Simulator tick rate (ticks/s)
host_mem_usage 291356 # Number of bytes of host memory used
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
host_seconds 0.01 # Real time elapsed on the host
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory
system.physmem.bytes_read::total 28544 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory
system.physmem.num_reads::total 446 # Number of read requests responded to by this memory
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.bw_read::cpu.inst 546697599 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 330378405 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 877076004 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 546697599 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 546697599 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 546697599 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 330378405 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 877076004 # Total bandwidth to/from this memory (bytes/s)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
tests: update tests for TLB unification
2009-04-09 07:21:30 +02:00
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.dtb.read_hits 1183 # DTB read hits
Stats: Update the stats. --HG-- extra : convert_revision : 888b6e3bcd432a9318d4b8741a8b274c6f37f1a8
2007-08-27 05:27:53 +02:00
system.cpu.dtb.read_misses 7 # DTB read misses
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.dtb.read_acv 0 # DTB read access violations
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.dtb.read_accesses 1190 # DTB read accesses
This brings M5 closer to modernity - the kernel being advertised is newer so it won't die on binaries compiled with newer glibc's, and enables use of TLS-toolchain built binaries for ALPHA_SE by putting auxiliary vectors on the stack. There are some comments in the code to help. Finally, stats changes for ALPHA are from slight perturbations to the initial stack frame, all minimal diffs.
2008-12-05 18:09:29 +01:00
system.cpu.dtb.write_hits 865 # DTB write hits
Stats: Update the stats. --HG-- extra : convert_revision : 888b6e3bcd432a9318d4b8741a8b274c6f37f1a8
2007-08-27 05:27:53 +02:00
system.cpu.dtb.write_misses 3 # DTB write misses
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 868 # DTB write accesses
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.dtb.data_hits 2048 # DTB hits
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.dtb.data_misses 10 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.dtb.data_accesses 2058 # DTB accesses
system.cpu.itb.fetch_hits 6401 # ITB hits
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.itb.fetch_accesses 6418 # ITB accesses
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.numCycles 65089 # number of cpu cycles simulated
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.committedInsts 6390 # Number of instructions committed
system.cpu.committedOps 6390 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_func_calls 251 # number of times a function call or return occured
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls
system.cpu.num_int_insts 6317 # number of integer instructions
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.num_fp_insts 10 # number of float instructions
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.num_int_register_reads 8285 # number of times the integer registers were read
system.cpu.num_int_register_writes 4568 # number of times the integer registers were written
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.num_mem_refs 2058 # number of memory refs
system.cpu.num_load_insts 1190 # Number of load instructions
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.num_busy_cycles 65089 # Number of busy cycles
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
stats: updates due to branch predictor warming
2014-02-16 18:40:34 +01:00
system.cpu.Branches 1050 # Number of branches fetched
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction
system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction
system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction
system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction
system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 6400 # Class of executed instruction
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 103.757933 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1880 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 11.190476 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 103.757933 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.025332 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.025332 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.041016 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 4264 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 4264 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 1880 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 1880 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 1880 # number of overall hits
system.cpu.dcache.overall_hits::total 1880 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses
system.cpu.dcache.overall_misses::total 168 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5225000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 5225000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4015000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 4015000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 9240000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 9240000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 9240000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 9240000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 2048 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2048 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2048 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2048 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080304 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.080304 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.082031 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.082031 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.082031 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.082031 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5082500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5082500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3905500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3905500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8988000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 8988000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8988000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 8988000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.replacements 0 # number of replacements
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.tags.tagsinuse 127.992738 # Cycle average of tags in use
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.total_refs 6122 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 21.942652 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.tags.occ_blocks::cpu.inst 127.992738 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.062496 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.062496 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 279 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.136230 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 13081 # Number of tag accesses
system.cpu.icache.tags.data_accesses 13081 # Number of data accesses
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.icache.ReadReq_hits::cpu.inst 6122 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 6122 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 6122 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 6122 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 6122 # number of overall hits
system.cpu.icache.overall_hits::total 6122 # number of overall hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 279 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 279 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 279 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 279 # number of overall misses
system.cpu.icache.overall_misses::total 279 # number of overall misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.ReadReq_miss_latency::cpu.inst 15303500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 15303500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 15303500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 15303500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 15303500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 15303500 # number of overall miss cycles
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.icache.ReadReq_accesses::cpu.inst 6401 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 6401 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 6401 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 6401 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 6401 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 6401 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043587 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.043587 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.043587 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.043587 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.043587 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.043587 # miss rate for overall accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54851.254480 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 54851.254480 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54851.254480 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 54851.254480 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54851.254480 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 54851.254480 # average overall miss latency
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
Add Alpha Linux version of "hello world" test. --HG-- extra : convert_revision : 22cd31c58f18fd92bd61ee4b4a218926f7290045
2006-08-21 04:48:30 +02:00
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 279 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 279 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 279 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14885000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 14885000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14885000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 14885000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14885000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 14885000 # number of overall MSHR miss cycles
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043587 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.043587 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.043587 # mshr miss rate for overall accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53351.254480 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53351.254480 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53351.254480 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 53351.254480 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53351.254480 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53351.254480 # average overall mshr miss latency
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.replacements 0 # number of replacements
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.tags.tagsinuse 184.488660 # Cycle average of tags in use
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.002681 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.tags.occ_blocks::cpu.inst 128.011543 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 56.477117 # Average occupied blocks per requestor
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003907 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001724 # Average percentage of cache occupancy
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.occ_percent::total 0.005630 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.l2cache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011383 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 4022 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 4022 # Number of data accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
system.cpu.l2cache.overall_hits::total 1 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 278 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 95 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 373 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 168 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 446 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses
system.cpu.l2cache.overall_misses::total 446 # number of overall misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14595500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4987500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 19583000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3832500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 3832500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 14595500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 8820000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 23415500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 14595500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 8820000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 23415500 # number of overall miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_accesses::cpu.inst 279 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 374 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 279 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 447 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 279 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 168 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 447 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996416 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadReq_miss_rate::total 0.997326 # miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996416 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.demand_miss_rate::total 0.997763 # miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996416 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.overall_miss_rate::total 0.997763 # miss rate for overall accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.798561 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.340483 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52501.121076 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52501.121076 # average overall miss latency
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
Add Alpha Linux version of "hello world" test. --HG-- extra : convert_revision : 22cd31c58f18fd92bd61ee4b4a218926f7290045
2006-08-21 04:48:30 +02:00
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 373 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11259000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3847500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15106500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2956500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2956500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11259000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6804000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 18063000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11259000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6804000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 18063000 # number of overall MSHR miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997326 # mshr miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::total 0.997763 # mshr miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997763 # mshr miss rate for overall accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.trans_dist::ReadReq 374 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 558 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 894 # Packet count per connected master and slave (bytes)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17856 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 28608 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 447 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 447 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 447 # Request fanout histogram
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 418500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 252000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.trans_dist::ReadReq 373 # Transaction distribution
system.membus.trans_dist::ReadResp 373 # Transaction distribution
system.membus.trans_dist::ReadExReq 73 # Transaction distribution
system.membus.trans_dist::ReadExResp 73 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 446 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 446 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 446 # Request fanout histogram
system.membus.reqLayer0.occupancy 446500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
system.membus.respLayer1.occupancy 2230500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 6.9 # Layer utilization (%)
Add Alpha Linux version of "hello world" test. --HG-- extra : convert_revision : 22cd31c58f18fd92bd61ee4b4a218926f7290045
2006-08-21 04:48:30 +02:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink