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Add Alpha Linux version of "hello world" test.

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--HG--
extra : convert_revision : 22cd31c58f18fd92bd61ee4b4a218926f7290045
This commit is contained in:
Steve Reinhardt 2006-08-20 22:48:30 -04:00
parent eb1f1336b3
commit 07994c2367
14 changed files with 1110 additions and 0 deletions
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98
tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini Normal file
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[root]
type=Root
children=system
checkpoint=
clock=1000000000000
max_tick=0
output_file=cout
progress_interval=0
[debug]
break_cycles=
[exetrace]
intel_format=false
pc_symbol=true
print_cpseq=false
print_cycle=true
print_data=true
print_effaddr=true
print_fetchseq=false
print_iregs=false
print_opclass=true
print_thread=true
speculative=true
trace_system=client
[serialize]
count=10
cycle=0
dir=cpt.%012d
period=0
[stats]
descriptions=true
dump_cycle=0
dump_period=0
dump_reset=false
ignore_events=
mysql_db=
mysql_host=
mysql_password=
mysql_user=
project_name=test
simulation_name=test
simulation_sample=0
text_compat=true
text_file=m5stats.txt
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
[system.cpu]
type=AtomicSimpleCPU
children=workload
clock=1
defer_registration=false
function_trace=false
function_trace_start=0
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
mem=system.physmem
simulate_stalls=false
system=system
width=1
workload=system.cpu.workload
[system.cpu.workload]
type=LiveProcess
cmd=hello
env=
executable=tests/test-progs/hello/bin/alpha/linux/hello
input=cin
output=cout
system=system
[system.membus]
type=Bus
bus_id=0
[system.physmem]
type=PhysicalMemory
file=
latency=1
range=0:134217727
[trace]
bufsize=0
dump_on_exit=false
file=cout
flags=
ignore=
start=0

93
tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out Normal file
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[root]
type=Root
clock=1000000000000
max_tick=0
progress_interval=0
output_file=cout
[system.physmem]
type=PhysicalMemory
file=
range=[0,134217727]
latency=1
[system]
type=System
physmem=system.physmem
mem_mode=atomic
[system.membus]
type=Bus
bus_id=0
[system.cpu.workload]
type=LiveProcess
cmd=hello
executable=tests/test-progs/hello/bin/alpha/linux/hello
input=cin
output=cout
env=
system=system
[system.cpu]
type=AtomicSimpleCPU
max_insts_any_thread=0
max_insts_all_threads=0
max_loads_any_thread=0
max_loads_all_threads=0
mem=system.physmem
system=system
workload=system.cpu.workload
clock=1
defer_registration=false
width=1
function_trace=false
function_trace_start=0
simulate_stalls=false
[trace]
flags=
start=0
bufsize=0
file=cout
dump_on_exit=false
ignore=
[stats]
descriptions=true
project_name=test
simulation_name=test
simulation_sample=0
text_file=m5stats.txt
text_compat=true
mysql_db=
mysql_user=
mysql_password=
mysql_host=
events_start=-1
dump_reset=false
dump_cycle=0
dump_period=0
ignore_events=
[random]
seed=1
[exetrace]
speculative=true
print_cycle=true
print_opclass=true
print_thread=true
print_effaddr=true
print_data=true
print_iregs=false
print_fetchseq=false
print_cpseq=false
print_reg_delta=false
pc_symbol=true
intel_format=false
trace_system=client
[debug]
break_cycles=

18
tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt Normal file
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---------- Begin Simulation Statistics ----------
host_inst_rate 58510 # Simulator instruction rate (inst/s)
host_mem_usage 146720 # Number of bytes of host memory used
host_seconds 0.04 # Real time elapsed on the host
host_tick_rate 57971 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2578 # Number of instructions simulated
sim_seconds 0.000000 # Number of seconds simulated
sim_ticks 2577 # Number of ticks simulated
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 2578 # number of cpu cycles simulated
system.cpu.num_insts 2578 # Number of instructions executed
system.cpu.num_refs 710 # Number of memory references
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
---------- End Simulation Statistics ----------

3
tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr Normal file
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warn: Entering event queue @ 0. Starting simulation...
warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff8
warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...)

13
tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout Normal file
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Hello world!
M5 Simulator System
Copyright (c) 2001-2006
The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 18 2006 00:06:43
M5 started Fri Aug 18 00:12:48 2006
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic
Exiting @ tick 2577 because target called exit()

214
tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini Normal file
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[root]
type=Root
children=system
checkpoint=
clock=1000000000000
max_tick=0
output_file=cout
progress_interval=0
[debug]
break_cycles=
[exetrace]
intel_format=false
pc_symbol=true
print_cpseq=false
print_cycle=true
print_data=true
print_effaddr=true
print_fetchseq=false
print_iregs=false
print_opclass=true
print_thread=true
speculative=true
trace_system=client
[serialize]
count=10
cycle=0
dir=cpt.%012d
period=0
[stats]
descriptions=true
dump_cycle=0
dump_period=0
dump_reset=false
ignore_events=
mysql_db=
mysql_host=
mysql_password=
mysql_user=
project_name=test
simulation_name=test
simulation_sample=0
text_compat=true
text_file=m5stats.txt
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
[system.cpu]
type=TimingSimpleCPU
children=dcache icache l2cache toL2Bus workload
clock=1
defer_registration=false
function_trace=false
function_trace_start=0
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
mem=system.cpu.dcache
system=system
workload=system.cpu.workload
[system.cpu.dcache]
type=BaseCache
adaptive_compression=false
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
do_copy=false
hash_delay=1
hit_latency=1
latency=1
lifo=false
max_miss_count=0
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=262144
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
[system.cpu.icache]
type=BaseCache
adaptive_compression=false
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
do_copy=false
hash_delay=1
hit_latency=1
latency=1
lifo=false
max_miss_count=0
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=131072
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
[system.cpu.l2cache]
type=BaseCache
adaptive_compression=false
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
do_copy=false
hash_delay=1
hit_latency=1
latency=1
lifo=false
max_miss_count=0
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=2097152
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
[system.cpu.toL2Bus]
type=Bus
bus_id=0
[system.cpu.workload]
type=LiveProcess
cmd=hello
env=
executable=tests/test-progs/hello/bin/alpha/linux/hello
input=cin
output=cout
system=system
[system.membus]
type=Bus
bus_id=0
[system.physmem]
type=PhysicalMemory
file=
latency=1
range=0:134217727
[trace]
bufsize=0
dump_on_exit=false
file=cout
flags=
ignore=
start=0

214
tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out Normal file
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[root]
type=Root
clock=1000000000000
max_tick=0
progress_interval=0
output_file=cout
[system.physmem]
type=PhysicalMemory
file=
range=[0,134217727]
latency=1
[system]
type=System
physmem=system.physmem
mem_mode=atomic
[system.membus]
type=Bus
bus_id=0
[system.cpu.dcache]
type=BaseCache
size=262144
assoc=2
block_size=64
latency=1
mshrs=10
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
do_copy=false
protocol=null
trace_addr=0
hash_delay=1
repl=null
compressed_bus=false
store_compressed=false
adaptive_compression=false
compression_latency=0
block_size=64
max_miss_count=0
addr_range=[0,18446744073709551615]
split=false
split_size=0
lifo=false
two_queue=false
prefetch_miss=false
prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.workload]
type=LiveProcess
cmd=hello
executable=tests/test-progs/hello/bin/alpha/linux/hello
input=cin
output=cout
env=
system=system
[system.cpu]
type=TimingSimpleCPU
max_insts_any_thread=0
max_insts_all_threads=0
max_loads_any_thread=0
max_loads_all_threads=0
mem=system.cpu.dcache
system=system
workload=system.cpu.workload
clock=1
defer_registration=false
// width not specified
function_trace=false
function_trace_start=0
// simulate_stalls not specified
[system.cpu.toL2Bus]
type=Bus
bus_id=0
[system.cpu.icache]
type=BaseCache
size=131072
assoc=2
block_size=64
latency=1
mshrs=10
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
do_copy=false
protocol=null
trace_addr=0
hash_delay=1
repl=null
compressed_bus=false
store_compressed=false
adaptive_compression=false
compression_latency=0
block_size=64
max_miss_count=0
addr_range=[0,18446744073709551615]
split=false
split_size=0
lifo=false
two_queue=false
prefetch_miss=false
prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.l2cache]
type=BaseCache
size=2097152
assoc=2
block_size=64
latency=1
mshrs=10
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
do_copy=false
protocol=null
trace_addr=0
hash_delay=1
repl=null
compressed_bus=false
store_compressed=false
adaptive_compression=false
compression_latency=0
block_size=64
max_miss_count=0
addr_range=[0,18446744073709551615]
split=false
split_size=0
lifo=false
two_queue=false
prefetch_miss=false
prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[trace]
flags=
start=0
bufsize=0
file=cout
dump_on_exit=false
ignore=
[stats]
descriptions=true
project_name=test
simulation_name=test
simulation_sample=0
text_file=m5stats.txt
text_compat=true
mysql_db=
mysql_user=
mysql_password=
mysql_host=
events_start=-1
dump_reset=false
dump_cycle=0
dump_period=0
ignore_events=
[random]
seed=1
[exetrace]
speculative=true
print_cycle=true
print_opclass=true
print_thread=true
print_effaddr=true
print_data=true
print_iregs=false
print_fetchseq=false
print_cpseq=false
print_reg_delta=false
pc_symbol=true
intel_format=false
trace_system=client
[debug]
break_cycles=

213
tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt Normal file
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---------- Begin Simulation Statistics ----------
host_inst_rate 37119 # Simulator instruction rate (inst/s)
host_mem_usage 158176 # Number of bytes of host memory used
host_seconds 0.07 # Real time elapsed on the host
host_tick_rate 54058 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2578 # Number of instructions simulated
sim_seconds 0.000000 # Number of seconds simulated
sim_ticks 3777 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 416 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 2918912699678311424 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 361 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 160540198482307121152 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.132212 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 110 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.132212 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 4476343852030456320 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 267 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 120861284004822319104 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.091837 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 27 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 54 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.091837 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 27 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 7.658537 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 710 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 3431725396184505344 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency
system.cpu.dcache.demand_hits 628 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 281401482487129440256 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.115493 # miss rate for demand accesses
system.cpu.dcache.demand_misses 82 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 164 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.115493 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 82 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 710 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 3431725396184505344 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 628 # number of overall hits
system.cpu.dcache.overall_miss_latency 281401482487129440256 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.115493 # miss rate for overall accesses
system.cpu.dcache.overall_misses 82 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 164 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.115493 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 82 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 53.009529 # Cycle average of tags in use
system.cpu.dcache.total_refs 628 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_accesses 2579 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 3447887748754160128 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 2416 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 562005703046928072704 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.063203 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 163 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 326 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.063203 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 163 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 14.822086 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 2579 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 3447887748754160128 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency
system.cpu.icache.demand_hits 2416 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 562005703046928072704 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.063203 # miss rate for demand accesses
system.cpu.icache.demand_misses 163 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 326 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.063203 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 163 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 2579 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 3447887748754160128 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 2416 # number of overall hits
system.cpu.icache.overall_miss_latency 562005703046928072704 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.063203 # miss rate for overall accesses
system.cpu.icache.overall_misses 163 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 326 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.063203 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 163 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 93.126257 # Cycle average of tags in use
system.cpu.icache.total_refs 2416 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadReq_accesses 245 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 2 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_miss_latency 490 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 245 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 245 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 245 # number of ReadReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 245 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 2 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 490 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 245 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 245 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 245 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 2 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 0 # number of overall hits
system.cpu.l2cache.overall_miss_latency 490 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 245 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 245 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 245 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 245 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 146.200635 # Cycle average of tags in use
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 0 # number of cpu cycles simulated
system.cpu.num_insts 2578 # Number of instructions executed
system.cpu.num_refs 710 # Number of memory references
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
---------- End Simulation Statistics ----------

3
tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr Normal file
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@ -0,0 +1,3 @@
warn: Entering event queue @ 0. Starting simulation...
warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff8
warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...)

13
tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout Normal file
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@ -0,0 +1,13 @@
Hello world!
M5 Simulator System
Copyright (c) 2001-2006
The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 18 2006 00:06:43
M5 started Sun Aug 20 01:42:05 2006
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing
Exiting @ tick 3777 because target called exit()

98
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini Normal file
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@ -0,0 +1,98 @@
[root]
type=Root
children=system
checkpoint=
clock=1000000000000
max_tick=0
output_file=cout
progress_interval=0
[debug]
break_cycles=
[exetrace]
intel_format=false
pc_symbol=true
print_cpseq=false
print_cycle=true
print_data=true
print_effaddr=true
print_fetchseq=false
print_iregs=false
print_opclass=true
print_thread=true
speculative=true
trace_system=client
[serialize]
count=10
cycle=0
dir=cpt.%012d
period=0
[stats]
descriptions=true
dump_cycle=0
dump_period=0
dump_reset=false
ignore_events=
mysql_db=
mysql_host=
mysql_password=
mysql_user=
project_name=test
simulation_name=test
simulation_sample=0
text_compat=true
text_file=m5stats.txt
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
[system.cpu]
type=AtomicSimpleCPU
children=workload
clock=1
defer_registration=false
function_trace=false
function_trace_start=0
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
mem=system.physmem
simulate_stalls=false
system=system
width=1
workload=system.cpu.workload
[system.cpu.workload]
type=LiveProcess
cmd=hello
env=
executable=tests/test-progs/hello/bin/alpha/tru64/hello
input=cin
output=cout
system=system
[system.membus]
type=Bus
bus_id=0
[system.physmem]
type=PhysicalMemory
file=
latency=1
range=0:134217727
[trace]
bufsize=0
dump_on_exit=false
file=cout
flags=
ignore=
start=0

93
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out Normal file
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@ -0,0 +1,93 @@
[root]
type=Root
clock=1000000000000
max_tick=0
progress_interval=0
output_file=cout
[system.physmem]
type=PhysicalMemory
file=
range=[0,134217727]
latency=1
[system]
type=System
physmem=system.physmem
mem_mode=atomic
[system.membus]
type=Bus
bus_id=0
[system.cpu.workload]
type=LiveProcess
cmd=hello
executable=tests/test-progs/hello/bin/alpha/tru64/hello
input=cin
output=cout
env=
system=system
[system.cpu]
type=AtomicSimpleCPU
max_insts_any_thread=0
max_insts_all_threads=0
max_loads_any_thread=0
max_loads_all_threads=0
mem=system.physmem
system=system
workload=system.cpu.workload
clock=1
defer_registration=false
width=1
function_trace=false
function_trace_start=0
simulate_stalls=false
[trace]
flags=
start=0
bufsize=0
file=cout
dump_on_exit=false
ignore=
[stats]
descriptions=true
project_name=test
simulation_name=test
simulation_sample=0
text_file=m5stats.txt
text_compat=true
mysql_db=
mysql_user=
mysql_password=
mysql_host=
events_start=-1
dump_reset=false
dump_cycle=0
dump_period=0
ignore_events=
[random]
seed=1
[exetrace]
speculative=true
print_cycle=true
print_opclass=true
print_thread=true
print_effaddr=true
print_data=true
print_iregs=false
print_fetchseq=false
print_cpseq=false
print_reg_delta=false
pc_symbol=true
intel_format=false
trace_system=client
[debug]
break_cycles=

BIN
tests/test-progs/hello/bin/alpha/linux/hello Executable file
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Binary file not shown.

37
tests/test-progs/hello/src/hello.c Normal file
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@ -0,0 +1,37 @@
/*
* Copyright (c) 2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Steve Reinhardt
*/
#include <stdio.h>
int main()
{
printf("Hello world!\n");
}