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gem5/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt

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stats: update 20.parser o3 now that it works. realview-o3 works too.
2011-04-25 23:18:08 +02:00
---------- Begin Simulation Statistics ----------
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
sim_seconds 0.458346 # Number of seconds simulated
sim_ticks 458345683000 # Number of ticks simulated
final_tick 458345683000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
stats: update 20.parser o3 now that it works. realview-o3 works too.
2011-04-25 23:18:08 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
host_inst_rate 77949 # Simulator instruction rate (inst/s)
host_op_rate 144137 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 43207948 # Simulator tick rate (ticks/s)
host_mem_usage 382980 # Number of bytes of host memory used
host_seconds 10607.90 # Real time elapsed on the host
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
sim_insts 826877109 # Number of instructions simulated
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
sim_ops 1528988701 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.bytes_read::cpu.inst 201344 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 24476224 # Number of bytes read from this memory
system.physmem.bytes_read::total 24677568 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 201344 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 201344 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 18790080 # Number of bytes written to this memory
system.physmem.bytes_written::total 18790080 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 3146 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 382441 # Number of read requests responded to by this memory
system.physmem.num_reads::total 385587 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 293595 # Number of write requests responded to by this memory
system.physmem.num_writes::total 293595 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 439284 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 53401232 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 53840516 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 439284 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 439284 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 40995434 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 40995434 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 40995434 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 439284 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 53401232 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 94835949 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 385587 # Number of read requests accepted
system.physmem.writeReqs 293595 # Number of write requests accepted
system.physmem.readBursts 385587 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 293595 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 24655680 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 21888 # Total number of bytes read from write queue
system.physmem.bytesWritten 18787904 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 24677568 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 18790080 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 342 # Number of DRAM read bursts serviced by the write queue
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.neitherReadNorWriteReqs 137451 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 23999 # Per bank write bursts
system.physmem.perBankRdBursts::1 26321 # Per bank write bursts
system.physmem.perBankRdBursts::2 24635 # Per bank write bursts
system.physmem.perBankRdBursts::3 24488 # Per bank write bursts
system.physmem.perBankRdBursts::4 23208 # Per bank write bursts
system.physmem.perBankRdBursts::5 23662 # Per bank write bursts
system.physmem.perBankRdBursts::6 24431 # Per bank write bursts
system.physmem.perBankRdBursts::7 24245 # Per bank write bursts
system.physmem.perBankRdBursts::8 23683 # Per bank write bursts
system.physmem.perBankRdBursts::9 23822 # Per bank write bursts
system.physmem.perBankRdBursts::10 24823 # Per bank write bursts
system.physmem.perBankRdBursts::11 24044 # Per bank write bursts
system.physmem.perBankRdBursts::12 23228 # Per bank write bursts
system.physmem.perBankRdBursts::13 22920 # Per bank write bursts
system.physmem.perBankRdBursts::14 23793 # Per bank write bursts
system.physmem.perBankRdBursts::15 23943 # Per bank write bursts
system.physmem.perBankWrBursts::0 18539 # Per bank write bursts
system.physmem.perBankWrBursts::1 19811 # Per bank write bursts
system.physmem.perBankWrBursts::2 18919 # Per bank write bursts
system.physmem.perBankWrBursts::3 18907 # Per bank write bursts
system.physmem.perBankWrBursts::4 18016 # Per bank write bursts
system.physmem.perBankWrBursts::5 18404 # Per bank write bursts
stats: updates due to branch predictor warming
2014-02-16 18:40:34 +01:00
system.physmem.perBankWrBursts::6 18977 # Per bank write bursts
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.perBankWrBursts::7 18938 # Per bank write bursts
system.physmem.perBankWrBursts::8 18573 # Per bank write bursts
system.physmem.perBankWrBursts::9 18106 # Per bank write bursts
system.physmem.perBankWrBursts::10 18839 # Per bank write bursts
system.physmem.perBankWrBursts::11 17716 # Per bank write bursts
stats: updates due to branch predictor warming
2014-02-16 18:40:34 +01:00
system.physmem.perBankWrBursts::12 17343 # Per bank write bursts
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.perBankWrBursts::13 16932 # Per bank write bursts
system.physmem.perBankWrBursts::14 17725 # Per bank write bursts
system.physmem.perBankWrBursts::15 17816 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.totGap 458345657000 # Total gap between requests
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.readPktSize::6 385587 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.writePktSize::6 293595 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 380584 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 4329 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 291 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 30 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 6249 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 6906 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 8122 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 15790 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 16374 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 16588 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 16668 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 16965 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 16912 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 16903 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 21550 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 17962 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 17787 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 22491 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 17603 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 17344 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 17191 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 16827 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 1360 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 517 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 374 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 342 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 329 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 344 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 307 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 311 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 306 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 285 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 286 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 273 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 272 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 274 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 257 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 261 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 248 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 239 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 236 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 235 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 96485 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 354.073856 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 206.339683 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 360.153261 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 30862 31.99% 31.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 25245 26.16% 58.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 9104 9.44% 67.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 4981 5.16% 72.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 3508 3.64% 76.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 2549 2.64% 79.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1904 1.97% 81.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1721 1.78% 82.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 16611 17.22% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 96485 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 16638 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 23.153564 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 214.001392 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 16625 99.92% 99.92% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 8 0.05% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-3071 3 0.02% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::25600-26623 1 0.01% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 16638 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 16638 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 17.644008 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 17.412925 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 3.984420 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 15809 95.02% 95.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 568 3.41% 98.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 13 0.08% 98.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 7 0.04% 98.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 5 0.03% 98.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 61 0.37% 98.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 106 0.64% 99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 27 0.16% 99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 20 0.12% 99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 3 0.02% 99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 1 0.01% 99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 6 0.04% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 1 0.01% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 1 0.01% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 1 0.01% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91 2 0.01% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 1 0.01% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 2 0.01% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 2 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 1 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 1 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 16638 # Writes before turning the bus around for reads
system.physmem.totQLat 2817376000 # Total ticks spent queuing
system.physmem.totMemAccLat 11128592250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 1926225000 # Total ticks spent in databus transfers
system.physmem.totBankLat 6384991250 # Total ticks spent accessing banks
system.physmem.avgQLat 7313.21 # Average queueing delay per DRAM burst
system.physmem.avgBankLat 16573.85 # Average bank access latency per DRAM burst
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.avgMemAccLat 28887.05 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 53.79 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 40.99 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 53.84 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 41.00 # Average system write bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.busUtil 0.74 # Data bus utilization in percentage
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.busUtilRead 0.42 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.32 # Data bus utilization in percentage for writes
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
system.physmem.avgWrQLen 22.28 # Average write queue length when enqueuing
system.physmem.readRowHits 317177 # Number of row buffer hits during reads
system.physmem.writeRowHits 216322 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.33 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 73.68 # Row buffer hit rate for writes
system.physmem.avgGap 674849.54 # Average gap between requests
system.physmem.pageHitRate 78.59 # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent 5.94 # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput 94835949 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 178789 # Transaction distribution
system.membus.trans_dist::ReadResp 178789 # Transaction distribution
system.membus.trans_dist::Writeback 293595 # Transaction distribution
system.membus.trans_dist::UpgradeReq 137451 # Transaction distribution
system.membus.trans_dist::UpgradeResp 137451 # Transaction distribution
system.membus.trans_dist::ReadExReq 206798 # Transaction distribution
system.membus.trans_dist::ReadExResp 206798 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1339671 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1339671 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1339671 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43467648 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43467648 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 43467648 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 43467648 # Total data (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.membus.reqLayer0.occupancy 3393086500 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer0.utilization 0.7 # Layer utilization (%)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.membus.respLayer1.occupancy 3901807065 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.9 # Layer utilization (%)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.branchPred.lookups 205603387 # Number of BP lookups
system.cpu.branchPred.condPredicted 205603387 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 9902113 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 117080162 # Number of BTB lookups
system.cpu.branchPred.BTBHits 114702381 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.branchPred.BTBHitPct 97.969100 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 25060949 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 1802781 # Number of incorrect RAS predictions.
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.workload.num_syscalls 551 # Number of system calls
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.numCycles 916852867 # number of cpu cycles simulated
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.fetch.icacheStallCycles 167425421 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 1131697501 # Number of instructions fetch has processed
system.cpu.fetch.Branches 205603387 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 139763330 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 352285469 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 71105811 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 304521969 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 48109 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 252946 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 61 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 162022121 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 2522560 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 885484431 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.378017 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.324314 # Number of instructions fetched each cycle (Total)
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.fetch.rateDist::0 537271116 60.68% 60.68% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 23397088 2.64% 63.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 25262126 2.85% 66.17% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 27864383 3.15% 69.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 17763945 2.01% 71.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 22926561 2.59% 73.91% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 29429676 3.32% 77.24% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 26640012 3.01% 80.24% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 174929524 19.76% 100.00% # Number of instructions fetched each cycle (Total)
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.fetch.rateDist::total 885484431 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.224249 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.234328 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 222585266 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 259638923 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 295357907 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 46951879 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 60950456 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 2071410922 # Number of instructions handled by decode
stats: updates due to branch predictor warming
2014-02-16 18:40:34 +01:00
system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.rename.SquashCycles 60950456 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 256114538 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 114960463 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 17780 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 306643544 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 146797650 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 2035254884 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 19108 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 24985336 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 106570240 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 2138126742 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 5150804980 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 3273565222 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 40421 # Number of floating rename lookups
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.rename.UndoneMaps 524085888 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 1238 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 1169 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 346813798 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 495843290 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 194454992 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 195400842 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 54863800 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 1975546158 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 13200 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 1772179882 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 484148 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 441719386 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 735183548 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 12648 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 885484431 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.001368 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.882860 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.iq.issued_per_cycle::0 268514596 30.32% 30.32% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 152316057 17.20% 47.53% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 137257157 15.50% 63.03% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 131678995 14.87% 77.90% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 91673992 10.35% 88.25% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 56016548 6.33% 94.58% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 34412328 3.89% 98.46% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 11858214 1.34% 99.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 1756544 0.20% 100.00% # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.iq.issued_per_cycle::total 885484431 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.iq.fu_full::IntAlu 4914226 32.32% 32.32% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 32.32% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 32.32% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.32% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.32% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.32% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 32.32% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.32% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.32% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.32% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.32% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.32% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.32% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.32% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.32% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 32.32% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.32% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 32.32% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.32% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.32% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.32% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.32% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.32% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.32% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.32% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.32% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.32% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.32% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.32% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 7684512 50.55% 82.87% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 2604414 17.13% 100.00% # attempts to use FU when none available
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.iq.FU_type_0::No_OpClass 2627261 0.15% 0.15% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1165804408 65.78% 65.93% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 352994 0.02% 65.95% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 3880826 0.22% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 67 0.00% 66.17% # Type of FU issued
x86, regressions: updates stats This is due to op class, function call, walker patches.
2013-05-21 18:41:27 +02:00
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.17% # Type of FU issued
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.iq.FU_type_0::MemRead 429279214 24.22% 90.39% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 170235112 9.61% 100.00% # Type of FU issued
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.iq.FU_type_0::total 1772179882 # Type of FU issued
system.cpu.iq.rate 1.932895 # Inst issue rate
system.cpu.iq.fu_busy_cnt 15203152 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.008579 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 4445517936 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 2417485915 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1744947174 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 13559 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 50440 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 3261 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 1784749273 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 6500 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 172700004 # Number of loads that had data forwarded from stores
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.iew.lsq.thread0.squashedLoads 111742246 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 386565 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 329489 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 45294806 # Number of stores squashed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.iew.lsq.thread0.rescheduledLoads 14850 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 595 # Number of times an access to memory failed due to the cache being blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.iew.iewSquashCycles 60950456 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 66921774 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 7152270 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 1975559358 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 792714 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 495844403 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 194454992 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 3102 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 4466928 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 83631 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 329489 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 5907148 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 4425214 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 10332362 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1753055321 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 424140880 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 19124561 # Number of squashed instructions skipped in execute
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.iew.exec_refs 590933103 # number of memory reference insts executed
system.cpu.iew.exec_branches 167483673 # Number of branches executed
system.cpu.iew.exec_stores 166792223 # Number of stores executed
system.cpu.iew.exec_rate 1.912036 # Inst execution rate
system.cpu.iew.wb_sent 1749807321 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1744950435 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1324909698 # num instructions producing a value
system.cpu.iew.wb_consumers 1945755632 # num instructions consuming a value
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.iew.wb_rate 1.903196 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.680923 # average fanout of values written-back
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.commit.commitSquashedInsts 446599399 # The number of squashed insts skipped by commit
x86 regressions: stats update due to new x87 instructions
2012-12-30 19:45:52 +01:00
system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.commit.branchMispredicts 9930890 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 824533975 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.854367 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.435928 # Number of insts commited each cycle
stats: update 20.parser o3 now that it works. realview-o3 works too.
2011-04-25 23:18:08 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.commit.committed_per_cycle::0 332362619 40.31% 40.31% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 193345604 23.45% 63.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 63386723 7.69% 71.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 92493757 11.22% 82.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 24926721 3.02% 85.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 27481357 3.33% 89.02% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 9323499 1.13% 90.15% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 11375843 1.38% 91.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 69837852 8.47% 100.00% # Number of insts commited each cycle
stats: update 20.parser o3 now that it works. realview-o3 works too.
2011-04-25 23:18:08 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.commit.committed_per_cycle::total 824533975 # Number of insts commited each cycle
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.commit.committedInsts 826877109 # Number of instructions committed
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.commit.refs 533262343 # Number of memory references committed
system.cpu.commit.loads 384102157 # Number of loads committed
stats: update 20.parser o3 now that it works. realview-o3 works too.
2011-04-25 23:18:08 +02:00
system.cpu.commit.membars 0 # Number of memory barriers committed
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.commit.branches 149758583 # Number of branches committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
test: update stats Update stats for recent changes. Mostly minor changes in register access stats due to addition of new cc register type and slightly different (and more accurate) classification of int vs. fp register accesses.
2013-10-16 16:44:12 +02:00
system.cpu.commit.int_insts 1526605509 # Number of committed integer instructions.
x86, regressions: updates stats This is due to op class, function call, walker patches.
2013-05-21 18:41:27 +02:00
system.cpu.commit.function_calls 17673145 # Number of function calls committed.
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.commit.bw_lim_events 69837852 # number cycles where commit BW limit reached
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.rob.rob_reads 2730284223 # The number of ROB reads
system.cpu.rob.rob_writes 4012285085 # The number of ROB writes
system.cpu.timesIdled 3361589 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 31368436 # Total number of cycles that the CPU has spent unscheduled due to idling
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.committedInsts 826877109 # Number of Instructions Simulated
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.cpi 1.108814 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.108814 # CPI: Total CPI of All Threads
system.cpu.ipc 0.901865 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.901865 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 2716343034 # number of integer regfile reads
system.cpu.int_regfile_writes 1420512883 # number of integer regfile writes
system.cpu.fp_regfile_reads 3304 # number of floating regfile reads
system.cpu.fp_regfile_writes 92 # number of floating regfile writes
system.cpu.cc_regfile_reads 597249207 # number of cc regfile reads
system.cpu.cc_regfile_writes 405429285 # number of cc regfile writes
system.cpu.misc_regfile_reads 964722506 # number of misc regfile reads
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.toL2Bus.throughput 699635153 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 1908088 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 1908087 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 2330726 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 138856 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 138856 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 771730 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 771730 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 152619 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7676496 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 7829115 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 437120 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311344320 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total 311781440 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 311781440 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 8893312 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 4908984370 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.toL2Bus.respLayer0.occupancy 219136241 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.toL2Bus.respLayer1.occupancy 3952027365 # Layer occupancy (ticks)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.icache.tags.replacements 5320 # number of replacements
system.cpu.icache.tags.tagsinuse 1037.745275 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 161872406 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 6896 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 23473.376740 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.icache.tags.occ_blocks::cpu.inst 1037.745275 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.506712 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.506712 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1576 # Occupied blocks per task id
stats: updates due to branch predictor warming
2014-02-16 18:40:34 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 238 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1228 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.769531 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 324190030 # Number of tag accesses
system.cpu.icache.tags.data_accesses 324190030 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 161874355 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 161874355 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 161874355 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 161874355 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 161874355 # number of overall hits
system.cpu.icache.overall_hits::total 161874355 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 147766 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 147766 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 147766 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 147766 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 147766 # number of overall misses
system.cpu.icache.overall_misses::total 147766 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 941588486 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 941588486 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 941588486 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 941588486 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 941588486 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 941588486 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 162022121 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 162022121 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 162022121 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 162022121 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 162022121 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 162022121 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000912 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000912 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000912 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000912 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000912 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000912 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6372.159265 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 6372.159265 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 6372.159265 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 6372.159265 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 6372.159265 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 6372.159265 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 953 # number of cycles access was blocked
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 119.125000 # average number of cycles each access was blocked
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1977 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 1977 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 1977 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 1977 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 1977 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 1977 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 145789 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 145789 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 145789 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 145789 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 145789 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 145789 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 560897259 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 560897259 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 560897259 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 560897259 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 560897259 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 560897259 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000900 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000900 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000900 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000900 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000900 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000900 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3847.322219 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3847.322219 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3847.322219 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 3847.322219 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3847.322219 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 3847.322219 # average overall mshr miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.l2cache.tags.replacements 352905 # number of replacements
system.cpu.l2cache.tags.tagsinuse 29664.192610 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 3697555 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 385281 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 9.597034 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 198720708500 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 21111.841089 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 223.120798 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 8329.230723 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.644282 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006809 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.254188 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.905279 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32376 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 246 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 11697 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 20354 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.988037 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 41242263 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 41242263 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 3684 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 1586656 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1590340 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 2330726 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 2330726 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 1427 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 1427 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 564910 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 564910 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 3684 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 2151566 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2155250 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 3684 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 2151566 # number of overall hits
system.cpu.l2cache.overall_hits::total 2155250 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 3147 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 175643 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 178790 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 137429 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 137429 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 206820 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 206820 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 3147 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 382463 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 385610 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 3147 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 382463 # number of overall misses
system.cpu.l2cache.overall_misses::total 385610 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 236007500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 12735446955 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 12971454455 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 6722711 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 6722711 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14644727978 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 14644727978 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 236007500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 27380174933 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 27616182433 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 236007500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 27380174933 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 27616182433 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 6831 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1762299 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1769130 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 2330726 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 2330726 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 138856 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 138856 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 771730 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 771730 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 6831 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 2534029 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2540860 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 6831 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 2534029 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2540860 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.460694 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099667 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.101061 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989723 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989723 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.267995 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.267995 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.460694 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.150931 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.151764 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.460694 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.150931 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.151764 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74994.439148 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72507.569075 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 72551.342105 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 48.917703 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 48.917703 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70809.051243 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70809.051243 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74994.439148 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71589.081644 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 71616.873092 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74994.439148 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71589.081644 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 71616.873092 # average overall miss latency
x86 regressions: stats update due to new x87 instructions
2012-12-30 19:45:52 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.l2cache.writebacks::writebacks 293595 # number of writebacks
system.cpu.l2cache.writebacks::total 293595 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3147 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175643 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 178790 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 137429 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 137429 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206820 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 206820 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3147 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 382463 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 385610 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3147 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 382463 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 385610 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 196679500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10498248955 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10694928455 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1378003511 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1378003511 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12022304022 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12022304022 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 196679500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22520552977 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 22717232477 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 196679500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22520552977 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 22717232477 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.460694 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099667 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101061 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.989723 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.989723 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.267995 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.267995 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.460694 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150931 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.151764 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.460694 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150931 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.151764 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62497.457896 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59770.380573 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59818.381649 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10027.021306 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10027.021306 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58129.310618 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58129.310618 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62497.457896 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58882.958553 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58912.456827 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62497.457896 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58882.958553 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58912.456827 # average overall mshr miss latency
x86 regressions: stats update due to new x87 instructions
2012-12-30 19:45:52 +01:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.dcache.tags.replacements 2529933 # number of replacements
system.cpu.dcache.tags.tagsinuse 4088.224261 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 395924693 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 2534029 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 156.243158 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 1796857250 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4088.224261 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.998102 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.998102 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 753 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 3301 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.dcache.tags.tag_accesses 800965525 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 800965525 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 247184750 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 247184750 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 148232864 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 148232864 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 395417614 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 395417614 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 395417614 # number of overall hits
system.cpu.dcache.overall_hits::total 395417614 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 2870796 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 2870796 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 927338 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 927338 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 3798134 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 3798134 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 3798134 # number of overall misses
system.cpu.dcache.overall_misses::total 3798134 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 57044971459 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 57044971459 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 26405527365 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 26405527365 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 83450498824 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 83450498824 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 83450498824 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 83450498824 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 250055546 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 250055546 # number of ReadReq accesses(hits+misses)
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.dcache.demand_accesses::cpu.data 399215748 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 399215748 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 399215748 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 399215748 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011481 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.011481 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006217 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.006217 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.009514 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.009514 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.009514 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.009514 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19870.785475 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 19870.785475 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28474.544734 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 28474.544734 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 21971.446722 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 21971.446722 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 21971.446722 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 21971.446722 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 6569 # number of cycles access was blocked
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.dcache.blocked::no_mshrs 666 # number of cycles access was blocked
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.863363 # average number of cycles each access was blocked
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.dcache.writebacks::writebacks 2330726 # number of writebacks
system.cpu.dcache.writebacks::total 2330726 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1108238 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 1108238 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 17013 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 17013 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1125251 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1125251 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1125251 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1125251 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762558 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1762558 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 910325 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 910325 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2672883 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2672883 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2672883 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2672883 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30399879250 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 30399879250 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 24280652885 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 24280652885 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 54680532135 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 54680532135 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 54680532135 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 54680532135 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007049 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007049 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006103 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006103 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006695 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.006695 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006695 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.006695 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17247.590859 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17247.590859 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26672.510241 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26672.510241 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20457.510536 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20457.510536 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20457.510536 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20457.510536 # average overall mshr miss latency
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: update 20.parser o3 now that it works. realview-o3 works too.
2011-04-25 23:18:08 +02:00
---------- End Simulation Statistics ----------
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