gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini

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2010-11-08 20:58:25 +01:00
[root]
type=Root
children=system
eventq_index=0
full_system=true
sim_quantum=0
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time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
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[system]
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
atags_addr=134217728
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boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
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default_p_state=UNDEFINED
dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
exit_on_work_items=false
flags_addr=469827632
gic_cpu_addr=738205696
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have_large_asid_64=false
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have_lpae=true
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have_security=false
have_virtualization=false
highest_el_is_64=false
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init_param=0
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kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
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load_addr_mask=268435455
load_offset=2147483648
machine_type=VExpress_EMM
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mem_mode=atomic
mem_ranges=2147483648:2415919103
memories=system.physmem system.realview.nvmem system.realview.vram
mmap_using_noreserve=false
multi_proc=true
multi_thread=false
num_work_ids=16
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p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
panic_on_oops=true
panic_on_panic=true
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phys_addr_range_64=40
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power_model=Null
readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
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reset_addr_64=0
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symbolfile=
thermal_components=
thermal_model=Null
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work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[1]
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[system.bridge]
type=Bridge
clk_domain=system.clk_domain
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default_p_state=UNDEFINED
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delay=50000
eventq_index=0
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p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
req_size=16
resp_size=16
master=system.iobus.slave[0]
slave=system.membus.master[0]
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[system.cf0]
type=IdeDisk
children=image
delay=1000000
driveID=master
eventq_index=0
image=system.cf0.image
[system.cf0.image]
type=CowDiskImage
children=child
child=system.cf0.image.child
eventq_index=0
image_file=
read_only=false
table_size=65536
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
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image_file=/arm/projectscratch/randd/systems/dist/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
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[system.cpu]
type=AtomicSimpleCPU
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children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
branchPred=Null
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checker=Null
clk_domain=system.cpu_clk_domain
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cpu_id=0
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default_p_state=UNDEFINED
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do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
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dstage2_mmu=system.cpu.dstage2_mmu
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dtb=system.cpu.dtb
eventq_index=0
fastmem=false
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function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
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istage2_mmu=system.cpu.istage2_mmu
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itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
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p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
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profile=0
progress_interval=0
simpoint_start_insts=
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simulate_data_stalls=false
simulate_inst_stalls=false
socket_id=0
switched_out=false
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system=system
tracer=system.cpu.tracer
width=1
workload=
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dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
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assoc=4
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
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default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
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max_miss_count=0
mshrs=4
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p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
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prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
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size=32768
system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
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write_buffers=8
writeback_clean=false
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cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
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[system.cpu.dcache.tags]
type=LRU
assoc=4
block_size=64
clk_domain=system.cpu_clk_domain
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default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
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p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
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[system.cpu.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
sys=system
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tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
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default_p_state=UNDEFINED
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eventq_index=0
is_stage2=true
num_squash_per_cycle=2
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p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
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sys=system
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[system.cpu.dtb]
type=ArmTLB
children=walker
eventq_index=0
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is_stage2=false
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size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
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default_p_state=UNDEFINED
eventq_index=0
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is_stage2=false
num_squash_per_cycle=2
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p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
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sys=system
port=system.cpu.toL2Bus.slave[3]
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[system.cpu.icache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
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assoc=1
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
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default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=true
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max_miss_count=0
mshrs=4
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p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
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prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
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size=32768
system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
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write_buffers=8
writeback_clean=true
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cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
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[system.cpu.icache.tags]
type=LRU
assoc=1
block_size=64
clk_domain=system.cpu_clk_domain
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default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
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p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
2010-11-08 20:58:25 +01:00
[system.cpu.interrupts]
type=ArmInterrupts
eventq_index=0
2010-11-08 20:58:25 +01:00
[system.cpu.isa]
type=ArmISA
decoderFlavour=Generic
eventq_index=0
fpsid=1090793632
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id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
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id_aa64pfr0_el1=34
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id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
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id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
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id_mmfr3=34611729
id_pfr0=49
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id_pfr1=4113
midr=1091551472
pmu=Null
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system=system
[system.cpu.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
sys=system
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tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.istage2_mmu.stage2_tlb.walker
[system.cpu.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
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default_p_state=UNDEFINED
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eventq_index=0
is_stage2=true
num_squash_per_cycle=2
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p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
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sys=system
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[system.cpu.itb]
type=ArmTLB
children=walker
eventq_index=0
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is_stage2=false
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size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
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default_p_state=UNDEFINED
eventq_index=0
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is_stage2=false
num_squash_per_cycle=2
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p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
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sys=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
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default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
sequential_access=false
size=4194304
system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[2]
[system.cpu.l2cache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
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default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
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p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=4194304
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
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default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
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p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=false
2016-07-21 18:19:18 +02:00
power_model=Null
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
2010-11-08 20:58:25 +01:00
[system.cpu.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
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[system.cpu.tracer]
type=ExeTracer
eventq_index=0
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[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
2010-11-08 20:58:25 +01:00
[system.intrctrl]
type=IntrControl
eventq_index=0
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sys=system
[system.iobus]
type=NoncoherentXBar
clk_domain=system.clk_domain
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default_p_state=UNDEFINED
eventq_index=0
forward_latency=1
frontend_latency=2
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p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
response_latency=2
use_default_range=false
width=16
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
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[system.iocache]
type=Cache
children=tags
addr_ranges=2147483648:2415919103
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assoc=8
clk_domain=system.clk_domain
clusivity=mostly_incl
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default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=50
is_read_only=false
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max_miss_count=0
mshrs=20
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
2010-11-08 20:58:25 +01:00
prefetch_on_access=false
prefetcher=Null
response_latency=50
sequential_access=false
2010-11-08 20:58:25 +01:00
size=1024
system=system
tags=system.iocache.tags
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tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.iobus.master[25]
mem_side=system.membus.slave[3]
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[system.iocache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.clk_domain
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default_p_state=UNDEFINED
eventq_index=0
hit_latency=50
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p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=1024
2010-11-08 20:58:25 +01:00
[system.membus]
type=CoherentXBar
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children=badaddr_responder
clk_domain=system.clk_domain
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default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
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p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
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power_model=Null
response_latency=2
snoop_filter=Null
snoop_response_latency=4
system=system
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use_default_range=false
width=16
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default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
2010-11-08 20:58:25 +01:00
[system.membus.badaddr_responder]
type=IsaFake
clk_domain=system.clk_domain
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default_p_state=UNDEFINED
eventq_index=0
fake_mem=false
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
2010-11-08 20:58:25 +01:00
pio_addr=0
pio_latency=100000
2010-11-08 20:58:25 +01:00
pio_size=8
2016-07-21 18:19:18 +02:00
power_model=Null
2010-11-08 20:58:25 +01:00
ret_bad_addr=true
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=warn
pio=system.membus.default
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
2016-07-21 18:19:18 +02:00
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
latency=30000
latency_var=0
2010-11-08 20:58:25 +01:00
null=false
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
range=2147483648:2415919103
port=system.membus.master[5]
2010-11-08 20:58:25 +01:00
[system.realview]
type=RealView
children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
eventq_index=0
2010-11-08 20:58:25 +01:00
intrctrl=system.intrctrl
system=system
[system.realview.aaci_fake]
type=AmbaFake
amba_id=0
clk_domain=system.clk_domain
2016-07-21 18:19:18 +02:00
default_p_state=UNDEFINED
eventq_index=0
2010-11-08 20:58:25 +01:00
ignore_access=false
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=470024192
pio_latency=100000
2016-07-21 18:19:18 +02:00
power_model=Null
2010-11-08 20:58:25 +01:00
system=system
pio=system.iobus.master[18]
2010-11-08 20:58:25 +01:00
[system.realview.cf_ctrl]
type=IdeController
BAR0=471465984
BAR0LegacyIO=true
BAR0Size=256
BAR1=471466240
BAR1LegacyIO=true
BAR1Size=4096
BAR2=1
BAR2LegacyIO=false
BAR2Size=8
BAR3=1
BAR3LegacyIO=false
BAR3Size=4
BAR4=1
BAR4LegacyIO=false
BAR4Size=16
BAR5=1
BAR5LegacyIO=false
BAR5Size=0
BIST=0
CacheLineSize=0
CapabilityPtr=0
CardbusCIS=0
ClassCode=1
Command=1
DeviceID=28945
ExpansionROM=0
HeaderType=0
InterruptLine=31
InterruptPin=1
LatencyTimer=0
LegacyIOBase=0
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
MSICAPMsgAddr=0
MSICAPMsgCtrl=0
MSICAPMsgData=0
MSICAPMsgUpperAddr=0
MSICAPNextCapability=0
MSICAPPendingBits=0
MSIXCAPBaseOffset=0
MSIXCAPCapId=0
MSIXCAPNextCapability=0
MSIXMsgCtrl=0
MSIXPbaOffset=0
MSIXTableOffset=0
MaximumLatency=0
MinimumGrant=0
PMCAPBaseOffset=0
PMCAPCapId=0
PMCAPCapabilities=0
PMCAPCtrlStatus=0
PMCAPNextCapability=0
PXCAPBaseOffset=0
PXCAPCapId=0
PXCAPCapabilities=0
PXCAPDevCap2=0
PXCAPDevCapabilities=0
PXCAPDevCtrl=0
PXCAPDevCtrl2=0
PXCAPDevStatus=0
PXCAPLinkCap=0
PXCAPLinkCtrl=0
PXCAPLinkStatus=0
PXCAPNextCapability=0
ProgIF=133
Revision=0
Status=640
SubClassCode=1
SubsystemID=0
SubsystemVendorID=0
VendorID=32902
clk_domain=system.clk_domain
config_latency=20000
ctrl_offset=2
2016-07-21 18:19:18 +02:00
default_p_state=UNDEFINED
disks=
eventq_index=0
host=system.realview.pci_host
io_shift=2
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pci_bus=2
pci_dev=0
pci_func=0
pio_latency=30000
2016-07-21 18:19:18 +02:00
power_model=Null
system=system
dma=system.iobus.slave[2]
pio=system.iobus.master[9]
[system.realview.clcd]
type=Pl111
amba_id=1315089
clk_domain=system.clk_domain
2016-07-21 18:19:18 +02:00
default_p_state=UNDEFINED
enable_capture=true
eventq_index=0
gic=system.realview.gic
int_num=46
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=471793664
pio_latency=10000
pixel_clock=41667
2016-07-21 18:19:18 +02:00
power_model=Null
2010-11-08 20:58:25 +01:00
system=system
vnc=system.vncserver
dma=system.iobus.slave[1]
pio=system.iobus.master[5]
2010-11-08 20:58:25 +01:00
[system.realview.dcc]
type=SubSystem
children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
eventq_index=0
thermal_domain=Null
[system.realview.dcc.osc_cpu]
type=RealViewOsc
dcc=0
device=0
eventq_index=0
freq=16667
parent=system.realview.realview_io
position=0
site=1
voltage_domain=system.voltage_domain
[system.realview.dcc.osc_ddr]
type=RealViewOsc
dcc=0
device=8
eventq_index=0
freq=25000
parent=system.realview.realview_io
position=0
site=1
voltage_domain=system.voltage_domain
[system.realview.dcc.osc_hsbm]
type=RealViewOsc
dcc=0
device=4
eventq_index=0
freq=25000
parent=system.realview.realview_io
position=0
site=1
voltage_domain=system.voltage_domain
[system.realview.dcc.osc_pxl]
type=RealViewOsc
dcc=0
device=5
eventq_index=0
freq=42105
parent=system.realview.realview_io
position=0
site=1
voltage_domain=system.voltage_domain
[system.realview.dcc.osc_smb]
type=RealViewOsc
dcc=0
device=6
eventq_index=0
freq=20000
parent=system.realview.realview_io
position=0
site=1
voltage_domain=system.voltage_domain
[system.realview.dcc.osc_sys]
type=RealViewOsc
dcc=0
device=7
eventq_index=0
freq=16667
parent=system.realview.realview_io
position=0
site=1
voltage_domain=system.voltage_domain
[system.realview.energy_ctrl]
type=EnergyCtrl
clk_domain=system.clk_domain
2016-07-21 18:19:18 +02:00
default_p_state=UNDEFINED
dvfs_handler=system.dvfs_handler
eventq_index=0
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=470286336
pio_latency=100000
2016-07-21 18:19:18 +02:00
power_model=Null
2010-11-08 20:58:25 +01:00
system=system
pio=system.iobus.master[22]
2010-11-08 20:58:25 +01:00
[system.realview.ethernet]
type=IGbE
BAR0=0
BAR0LegacyIO=false
BAR0Size=131072
BAR1=0
BAR1LegacyIO=false
BAR1Size=0
BAR2=0
BAR2LegacyIO=false
BAR2Size=0
BAR3=0
BAR3LegacyIO=false
BAR3Size=0
BAR4=0
BAR4LegacyIO=false
BAR4Size=0
BAR5=0
BAR5LegacyIO=false
BAR5Size=0
BIST=0
CacheLineSize=0
CapabilityPtr=0
CardbusCIS=0
ClassCode=2
Command=0
DeviceID=4213
ExpansionROM=0
HeaderType=0
InterruptLine=1
InterruptPin=1
LatencyTimer=0
LegacyIOBase=0
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
MSICAPMsgAddr=0
MSICAPMsgCtrl=0
MSICAPMsgData=0
MSICAPMsgUpperAddr=0
MSICAPNextCapability=0
MSICAPPendingBits=0
MSIXCAPBaseOffset=0
MSIXCAPCapId=0
MSIXCAPNextCapability=0
MSIXMsgCtrl=0
MSIXPbaOffset=0
MSIXTableOffset=0
MaximumLatency=0
MinimumGrant=255
PMCAPBaseOffset=0
PMCAPCapId=0
PMCAPCapabilities=0
PMCAPCtrlStatus=0
PMCAPNextCapability=0
PXCAPBaseOffset=0
PXCAPCapId=0
PXCAPCapabilities=0
PXCAPDevCap2=0
PXCAPDevCapabilities=0
PXCAPDevCtrl=0
PXCAPDevCtrl2=0
PXCAPDevStatus=0
PXCAPLinkCap=0
PXCAPLinkCtrl=0
PXCAPLinkStatus=0
PXCAPNextCapability=0
ProgIF=0
Revision=0
Status=0
SubClassCode=0
SubsystemID=4104
SubsystemVendorID=32902
VendorID=32902
clk_domain=system.clk_domain
config_latency=20000
2016-07-21 18:19:18 +02:00
default_p_state=UNDEFINED
eventq_index=0
fetch_comp_delay=10000
fetch_delay=10000
hardware_address=00:90:00:00:00:01
host=system.realview.pci_host
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pci_bus=0
pci_dev=0
pci_func=0
phy_epid=896
phy_pid=680
pio_latency=30000
2016-07-21 18:19:18 +02:00
power_model=Null
rx_desc_cache_size=64
rx_fifo_size=393216
rx_write_delay=0
system=system
tx_desc_cache_size=64
tx_fifo_size=393216
tx_read_delay=0
wb_comp_delay=10000
wb_delay=10000
dma=system.iobus.slave[4]
pio=system.iobus.master[24]
[system.realview.generic_timer]
type=GenericTimer
eventq_index=0
gic=system.realview.gic
int_phys=29
int_virt=27
2010-11-08 20:58:25 +01:00
system=system
[system.realview.gic]
type=Pl390
clk_domain=system.clk_domain
cpu_addr=738205696
2010-11-08 20:58:25 +01:00
cpu_pio_delay=10000
2016-07-21 18:19:18 +02:00
default_p_state=UNDEFINED
dist_addr=738201600
2010-11-08 20:58:25 +01:00
dist_pio_delay=10000
eventq_index=0
2016-06-02 15:14:36 +02:00
gem5_extensions=true
int_latency=10000
2010-11-08 20:58:25 +01:00
it_lines=128
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
2010-11-08 20:58:25 +01:00
platform=system.realview
2016-07-21 18:19:18 +02:00
power_model=Null
2010-11-08 20:58:25 +01:00
system=system
pio=system.membus.master[2]
2010-11-08 20:58:25 +01:00
[system.realview.hdlcd]
type=HDLcd
amba_id=1314816
clk_domain=system.clk_domain
2016-07-21 18:19:18 +02:00
default_p_state=UNDEFINED
enable_capture=true
eventq_index=0
gic=system.realview.gic
int_num=117
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=721420288
pio_latency=10000
pixel_buffer_size=2048
pixel_chunk=32
2016-07-21 18:19:18 +02:00
power_model=Null
pxl_clk=system.realview.dcc.osc_pxl
2010-11-08 20:58:25 +01:00
system=system
vnc=system.vncserver
workaround_dma_line_count=true
workaround_swap_rb=true
dma=system.membus.slave[0]
pio=system.iobus.master[6]
2010-11-08 20:58:25 +01:00
[system.realview.ide]
type=IdeController
BAR0=1
BAR0LegacyIO=false
BAR0Size=8
BAR1=1
BAR1LegacyIO=false
BAR1Size=4
BAR2=1
BAR2LegacyIO=false
BAR2Size=8
BAR3=1
BAR3LegacyIO=false
BAR3Size=4
BAR4=1
BAR4LegacyIO=false
BAR4Size=16
BAR5=1
BAR5LegacyIO=false
BAR5Size=0
BIST=0
CacheLineSize=0
CapabilityPtr=0
CardbusCIS=0
ClassCode=1
Command=0
DeviceID=28945
ExpansionROM=0
HeaderType=0
InterruptLine=2
InterruptPin=2
LatencyTimer=0
LegacyIOBase=0
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
MSICAPMsgAddr=0
MSICAPMsgCtrl=0
MSICAPMsgData=0
MSICAPMsgUpperAddr=0
MSICAPNextCapability=0
MSICAPPendingBits=0
MSIXCAPBaseOffset=0
MSIXCAPCapId=0
MSIXCAPNextCapability=0
MSIXMsgCtrl=0
MSIXPbaOffset=0
MSIXTableOffset=0
MaximumLatency=0
MinimumGrant=0
PMCAPBaseOffset=0
PMCAPCapId=0
PMCAPCapabilities=0
PMCAPCtrlStatus=0
PMCAPNextCapability=0
PXCAPBaseOffset=0
PXCAPCapId=0
PXCAPCapabilities=0
PXCAPDevCap2=0
PXCAPDevCapabilities=0
PXCAPDevCtrl=0
PXCAPDevCtrl2=0
PXCAPDevStatus=0
PXCAPLinkCap=0
PXCAPLinkCtrl=0
PXCAPLinkStatus=0
PXCAPNextCapability=0
ProgIF=133
Revision=0
Status=640
SubClassCode=1
SubsystemID=0
SubsystemVendorID=0
VendorID=32902
clk_domain=system.clk_domain
config_latency=20000
ctrl_offset=0
2016-07-21 18:19:18 +02:00
default_p_state=UNDEFINED
disks=system.cf0
eventq_index=0
host=system.realview.pci_host
io_shift=0
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pci_bus=0
pci_dev=1
pci_func=0
pio_latency=30000
2016-07-21 18:19:18 +02:00
power_model=Null
2010-11-08 20:58:25 +01:00
system=system
dma=system.iobus.slave[3]
pio=system.iobus.master[23]
2010-11-08 20:58:25 +01:00
[system.realview.kmi0]
type=Pl050
amba_id=1314896
clk_domain=system.clk_domain
2016-07-21 18:19:18 +02:00
default_p_state=UNDEFINED
eventq_index=0
gic=system.realview.gic
int_delay=1000000
int_num=44
is_mouse=false
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=470155264
pio_latency=100000
2016-07-21 18:19:18 +02:00
power_model=Null
2010-11-08 20:58:25 +01:00
system=system
vnc=system.vncserver
pio=system.iobus.master[7]
2010-11-08 20:58:25 +01:00
[system.realview.kmi1]
type=Pl050
amba_id=1314896
clk_domain=system.clk_domain
2016-07-21 18:19:18 +02:00
default_p_state=UNDEFINED
eventq_index=0
gic=system.realview.gic
int_delay=1000000
int_num=45
is_mouse=true
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=470220800
pio_latency=100000
2016-07-21 18:19:18 +02:00
power_model=Null
2010-11-08 20:58:25 +01:00
system=system
vnc=system.vncserver
pio=system.iobus.master[8]
2010-11-08 20:58:25 +01:00
[system.realview.l2x0_fake]
type=IsaFake
clk_domain=system.clk_domain
2016-07-21 18:19:18 +02:00
default_p_state=UNDEFINED
eventq_index=0
fake_mem=false
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=739246080
pio_latency=100000
2010-11-08 20:58:25 +01:00
pio_size=4095
2016-07-21 18:19:18 +02:00
power_model=Null
2010-11-08 20:58:25 +01:00
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[12]
[system.realview.lan_fake]
type=IsaFake
clk_domain=system.clk_domain
2016-07-21 18:19:18 +02:00
default_p_state=UNDEFINED
eventq_index=0
fake_mem=false
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=436207616
pio_latency=100000
pio_size=65535
2016-07-21 18:19:18 +02:00
power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[19]
2010-11-08 20:58:25 +01:00
[system.realview.local_cpu_timer]
type=CpuLocalTimer
clk_domain=system.clk_domain
2016-07-21 18:19:18 +02:00
default_p_state=UNDEFINED
eventq_index=0
gic=system.realview.gic
int_num_timer=29
int_num_watchdog=30
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=738721792
pio_latency=100000
2016-07-21 18:19:18 +02:00
power_model=Null
system=system
pio=system.membus.master[4]
[system.realview.mcc]
type=SubSystem
children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
eventq_index=0
thermal_domain=Null
[system.realview.mcc.osc_clcd]
type=RealViewOsc
dcc=0
device=1
eventq_index=0
freq=42105
parent=system.realview.realview_io
position=0
site=0
voltage_domain=system.voltage_domain
[system.realview.mcc.osc_mcc]
type=RealViewOsc
dcc=0
device=0
eventq_index=0
freq=20000
parent=system.realview.realview_io
position=0
site=0
voltage_domain=system.voltage_domain
[system.realview.mcc.osc_peripheral]
type=RealViewOsc
dcc=0
device=2
eventq_index=0
freq=41667
parent=system.realview.realview_io
position=0
site=0
voltage_domain=system.voltage_domain
[system.realview.mcc.osc_system_bus]
type=RealViewOsc
dcc=0
device=4
eventq_index=0
freq=41667
parent=system.realview.realview_io
position=0
site=0
voltage_domain=system.voltage_domain
[system.realview.mcc.temp_crtl]
type=RealViewTemperatureSensor
dcc=0
device=0
eventq_index=0
parent=system.realview.realview_io
position=0
site=0
system=system
2010-11-08 20:58:25 +01:00
[system.realview.mmc_fake]
type=AmbaFake
amba_id=0
clk_domain=system.clk_domain
2016-07-21 18:19:18 +02:00
default_p_state=UNDEFINED
eventq_index=0
2010-11-08 20:58:25 +01:00
ignore_access=false
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=470089728
pio_latency=100000
2016-07-21 18:19:18 +02:00
power_model=Null
2010-11-08 20:58:25 +01:00
system=system
pio=system.iobus.master[21]
[system.realview.nvmem]
type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=false
2016-07-21 18:19:18 +02:00
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
latency=30000
latency_var=0
null=false
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
range=0:67108863
port=system.membus.master[1]
2010-11-08 20:58:25 +01:00
[system.realview.pci_host]
type=GenericPciHost
clk_domain=system.clk_domain
conf_base=805306368
conf_device_bits=16
conf_size=268435456
2016-07-21 18:19:18 +02:00
default_p_state=UNDEFINED
eventq_index=0
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pci_dma_base=0
pci_mem_base=0
pci_pio_base=0
platform=system.realview
2016-07-21 18:19:18 +02:00
power_model=Null
system=system
pio=system.iobus.master[2]
2010-11-08 20:58:25 +01:00
[system.realview.realview_io]
type=RealViewCtrl
clk_domain=system.clk_domain
2016-07-21 18:19:18 +02:00
default_p_state=UNDEFINED
eventq_index=0
idreg=35979264
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=469827584
pio_latency=100000
2016-07-21 18:19:18 +02:00
power_model=Null
proc_id0=335544320
proc_id1=335544320
2010-11-08 20:58:25 +01:00
system=system
pio=system.iobus.master[1]
2010-11-08 20:58:25 +01:00
[system.realview.rtc]
type=PL031
amba_id=3412017
clk_domain=system.clk_domain
2016-07-21 18:19:18 +02:00
default_p_state=UNDEFINED
eventq_index=0
gic=system.realview.gic
int_delay=100000
int_num=36
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=471269376
pio_latency=100000
2016-07-21 18:19:18 +02:00
power_model=Null
2010-11-08 20:58:25 +01:00
system=system
time=Thu Jan 1 00:00:00 2009
pio=system.iobus.master[10]
2010-11-08 20:58:25 +01:00
[system.realview.sp810_fake]
type=AmbaFake
amba_id=0
clk_domain=system.clk_domain
2016-07-21 18:19:18 +02:00
default_p_state=UNDEFINED
eventq_index=0
2010-11-08 20:58:25 +01:00
ignore_access=true
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=469893120
pio_latency=100000
2016-07-21 18:19:18 +02:00
power_model=Null
2010-11-08 20:58:25 +01:00
system=system
pio=system.iobus.master[16]
2010-11-08 20:58:25 +01:00
[system.realview.timer0]
type=Sp804
amba_id=1316868
clk_domain=system.clk_domain
2010-11-08 20:58:25 +01:00
clock0=1000000
clock1=1000000
2016-07-21 18:19:18 +02:00
default_p_state=UNDEFINED
eventq_index=0
2010-11-08 20:58:25 +01:00
gic=system.realview.gic
int_num0=34
int_num1=34
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=470876160
pio_latency=100000
2016-07-21 18:19:18 +02:00
power_model=Null
2010-11-08 20:58:25 +01:00
system=system
pio=system.iobus.master[3]
2010-11-08 20:58:25 +01:00
[system.realview.timer1]
type=Sp804
amba_id=1316868
clk_domain=system.clk_domain
2010-11-08 20:58:25 +01:00
clock0=1000000
clock1=1000000
2016-07-21 18:19:18 +02:00
default_p_state=UNDEFINED
eventq_index=0
2010-11-08 20:58:25 +01:00
gic=system.realview.gic
int_num0=35
int_num1=35
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=470941696
pio_latency=100000
2016-07-21 18:19:18 +02:00
power_model=Null
2010-11-08 20:58:25 +01:00
system=system
pio=system.iobus.master[4]
2010-11-08 20:58:25 +01:00
[system.realview.uart]
type=Pl011
clk_domain=system.clk_domain
2016-07-21 18:19:18 +02:00
default_p_state=UNDEFINED
2010-11-08 20:58:25 +01:00
end_on_eot=false
eventq_index=0
2010-11-08 20:58:25 +01:00
gic=system.realview.gic
int_delay=100000
int_num=37
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=470351872
pio_latency=100000
2010-11-08 20:58:25 +01:00
platform=system.realview
2016-07-21 18:19:18 +02:00
power_model=Null
2010-11-08 20:58:25 +01:00
system=system
terminal=system.terminal
pio=system.iobus.master[0]
2010-11-08 20:58:25 +01:00
[system.realview.uart1_fake]
type=AmbaFake
amba_id=0
clk_domain=system.clk_domain
2016-07-21 18:19:18 +02:00
default_p_state=UNDEFINED
eventq_index=0
2010-11-08 20:58:25 +01:00
ignore_access=false
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=470417408
pio_latency=100000
2016-07-21 18:19:18 +02:00
power_model=Null
2010-11-08 20:58:25 +01:00
system=system
pio=system.iobus.master[13]
2010-11-08 20:58:25 +01:00
[system.realview.uart2_fake]
type=AmbaFake
amba_id=0
clk_domain=system.clk_domain
2016-07-21 18:19:18 +02:00
default_p_state=UNDEFINED
eventq_index=0
2010-11-08 20:58:25 +01:00
ignore_access=false
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=470482944
pio_latency=100000
2016-07-21 18:19:18 +02:00
power_model=Null
2010-11-08 20:58:25 +01:00
system=system
pio=system.iobus.master[14]
2010-11-08 20:58:25 +01:00
[system.realview.uart3_fake]
type=AmbaFake
amba_id=0
clk_domain=system.clk_domain
2016-07-21 18:19:18 +02:00
default_p_state=UNDEFINED
eventq_index=0
2010-11-08 20:58:25 +01:00
ignore_access=false
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=470548480
pio_latency=100000
2016-07-21 18:19:18 +02:00
power_model=Null
2010-11-08 20:58:25 +01:00
system=system
pio=system.iobus.master[15]
[system.realview.usb_fake]
type=IsaFake
clk_domain=system.clk_domain
2016-07-21 18:19:18 +02:00
default_p_state=UNDEFINED
eventq_index=0
fake_mem=false
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=452984832
pio_latency=100000
pio_size=131071
2016-07-21 18:19:18 +02:00
power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[20]
[system.realview.vgic]
type=VGic
clk_domain=system.clk_domain
2016-07-21 18:19:18 +02:00
default_p_state=UNDEFINED
eventq_index=0
gic=system.realview.gic
hv_addr=738213888
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_delay=10000
platform=system.realview
2016-07-21 18:19:18 +02:00
power_model=Null
ppint=25
system=system
vcpu_addr=738222080
pio=system.membus.master[3]
[system.realview.vram]
type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=false
2016-07-21 18:19:18 +02:00
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
latency=30000
latency_var=0
null=false
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
range=402653184:436207615
port=system.iobus.master[11]
2010-11-08 20:58:25 +01:00
[system.realview.watchdog_fake]
type=AmbaFake
amba_id=0
clk_domain=system.clk_domain
2016-07-21 18:19:18 +02:00
default_p_state=UNDEFINED
eventq_index=0
2010-11-08 20:58:25 +01:00
ignore_access=false
2016-07-21 18:19:18 +02:00
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=470745088
pio_latency=100000
2016-07-21 18:19:18 +02:00
power_model=Null
2010-11-08 20:58:25 +01:00
system=system
pio=system.iobus.master[17]
2010-11-08 20:58:25 +01:00
[system.terminal]
type=Terminal
eventq_index=0
2010-11-08 20:58:25 +01:00
intr_control=system.intrctrl
number=0
output=true
port=3456
[system.vncserver]
type=VncServer
eventq_index=0
frame_capture=false
number=0
port=5900
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000