2011-01-18 23:30:06 +01:00
---------- Begin Simulation Statistics ----------
2016-04-09 18:13:40 +02:00
sim_seconds 0.111754 # Number of seconds simulated
sim_ticks 111753553500 # Number of ticks simulated
final_tick 111753553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2011-01-18 23:30:06 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
2016-04-21 10:48:24 +02:00
host_inst_rate 153930 # Simulator instruction rate (inst/s)
host_op_rate 184810 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 63003104 # Simulator tick rate (ticks/s)
host_mem_usage 292088 # Number of bytes of host memory used
host_seconds 1773.78 # Real time elapsed on the host
2015-04-30 21:17:43 +02:00
sim_insts 273037220 # Number of instructions simulated
sim_ops 327811602 # Number of ops (including micro ops) simulated
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2016-04-09 18:13:40 +02:00
system.physmem.bytes_read::cpu.inst 620544 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 4626112 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher 168832 # Number of bytes read from this memory
system.physmem.bytes_read::total 5415488 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 620544 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 620544 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 9696 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 72283 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher 2638 # Number of read requests responded to by this memory
system.physmem.num_reads::total 84617 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 5552790 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 41395659 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher 1510753 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 48459202 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 5552790 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 5552790 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 5552790 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 41395659 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher 1510753 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 48459202 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 84617 # Number of read requests accepted
2013-11-01 16:56:34 +01:00
system.physmem.writeReqs 0 # Number of write requests accepted
2016-04-09 18:13:40 +02:00
system.physmem.readBursts 84617 # Number of DRAM read bursts, including those serviced by the write queue
2013-11-01 16:56:34 +01:00
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
2016-04-09 18:13:40 +02:00
system.physmem.bytesReadDRAM 5415488 # Total number of bytes read from DRAM
2013-11-01 16:56:34 +01:00
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
2016-04-09 18:13:40 +02:00
system.physmem.bytesReadSys 5415488 # Total read bytes from the system interface side
2013-11-01 16:56:34 +01:00
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
2016-02-10 10:08:27 +01:00
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
2016-04-09 18:13:40 +02:00
system.physmem.perBankRdBursts::0 956 # Per bank write bursts
2015-11-06 09:26:50 +01:00
system.physmem.perBankRdBursts::1 811 # Per bank write bursts
2016-04-09 18:13:40 +02:00
system.physmem.perBankRdBursts::2 834 # Per bank write bursts
system.physmem.perBankRdBursts::3 2907 # Per bank write bursts
system.physmem.perBankRdBursts::4 10637 # Per bank write bursts
system.physmem.perBankRdBursts::5 59817 # Per bank write bursts
system.physmem.perBankRdBursts::6 152 # Per bank write bursts
system.physmem.perBankRdBursts::7 259 # Per bank write bursts
system.physmem.perBankRdBursts::8 225 # Per bank write bursts
system.physmem.perBankRdBursts::9 303 # Per bank write bursts
system.physmem.perBankRdBursts::10 3870 # Per bank write bursts
2015-11-06 09:26:50 +01:00
system.physmem.perBankRdBursts::11 811 # Per bank write bursts
2016-04-09 18:13:40 +02:00
system.physmem.perBankRdBursts::12 1141 # Per bank write bursts
2015-11-06 09:26:50 +01:00
system.physmem.perBankRdBursts::13 693 # Per bank write bursts
2016-04-09 18:13:40 +02:00
system.physmem.perBankRdBursts::14 638 # Per bank write bursts
system.physmem.perBankRdBursts::15 563 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
2016-04-09 18:13:40 +02:00
system.physmem.totGap 111753395000 # Total gap between requests
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2016-04-09 18:13:40 +02:00
system.physmem.readPktSize::6 84617 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
2016-04-09 18:13:40 +02:00
system.physmem.rdQLenPdf::0 64967 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 17796 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 465 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 298 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 226 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 208 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 173 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 172 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 172 # What read queue length does an incoming req see
2015-11-06 09:26:50 +01:00
system.physmem.rdQLenPdf::9 53 # What read queue length does an incoming req see
2016-04-09 18:13:40 +02:00
system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see
2015-11-06 09:26:50 +01:00
system.physmem.rdQLenPdf::11 21 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 22 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 18 # What read queue length does an incoming req see
2015-07-30 09:42:27 +02:00
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
2015-07-03 16:15:03 +02:00
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
2016-04-09 18:13:40 +02:00
system.physmem.bytesPerActivate::samples 21291 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 254.217463 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 213.921670 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 155.515771 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 2572 12.08% 12.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 7102 33.36% 45.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 8141 38.24% 83.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 1445 6.79% 90.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 1060 4.98% 95.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 699 3.28% 98.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 33 0.15% 98.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 27 0.13% 99.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 212 1.00% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 21291 # Bytes accessed per row activation
system.physmem.totQLat 818886094 # Total ticks spent queuing
system.physmem.totMemAccLat 2405454844 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 423085000 # Total ticks spent in databus transfers
system.physmem.avgQLat 9677.56 # Average queueing delay per DRAM burst
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2016-04-09 18:13:40 +02:00
system.physmem.avgMemAccLat 28427.56 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 48.46 # Average DRAM read bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
2016-04-09 18:13:40 +02:00
system.physmem.avgRdBWSys 48.46 # Average system read bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2016-04-09 18:13:40 +02:00
system.physmem.busUtil 0.38 # Data bus utilization in percentage
system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads
2013-11-01 16:56:34 +01:00
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
2015-11-06 09:26:50 +01:00
system.physmem.avgRdQLen 1.36 # Average read queue length when enqueuing
2013-11-01 16:56:34 +01:00
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
2016-04-09 18:13:40 +02:00
system.physmem.readRowHits 63316 # Number of row buffer hits during reads
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
2016-04-09 18:13:40 +02:00
system.physmem.readRowHitRate 74.83 # Row buffer hit rate for reads
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
2016-04-09 18:13:40 +02:00
system.physmem.avgGap 1320696.73 # Average gap between requests
system.physmem.pageHitRate 74.83 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 137093040 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 74802750 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 595467600 # Energy for read commands per rank (pJ)
2014-12-23 15:31:20 +01:00
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
2016-04-09 18:13:40 +02:00
system.physmem_0.refreshEnergy 7298853120 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 61580578995 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 13031079750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 82717875255 # Total energy per rank (pJ)
system.physmem_0.averagePower 740.214288 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 21327892271 # Time in different power states
system.physmem_0.memoryStateTime::REF 3731520000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
2016-04-09 18:13:40 +02:00
system.physmem_0.memoryStateTime::ACT 86689152979 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
2016-04-09 18:13:40 +02:00
system.physmem_1.actEnergy 23821560 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 12997875 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 64092600 # Energy for read commands per rank (pJ)
2014-12-23 15:31:20 +01:00
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
2016-04-09 18:13:40 +02:00
system.physmem_1.refreshEnergy 7298853120 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 10878672015 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 57506417250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 75784854420 # Total energy per rank (pJ)
system.physmem_1.averagePower 678.173227 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 95612479879 # Time in different power states
system.physmem_1.memoryStateTime::REF 3731520000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
2016-04-09 18:13:40 +02:00
system.physmem_1.memoryStateTime::ACT 12405217621 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
2016-04-09 18:13:40 +02:00
system.cpu.branchPred.lookups 35971731 # Number of BP lookups
system.cpu.branchPred.condPredicted 19265386 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 984189 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 17894968 # Number of BTB lookups
system.cpu.branchPred.BTBHits 13923402 # Number of BTB hits
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2016-04-09 18:13:40 +02:00
system.cpu.branchPred.BTBHitPct 77.806241 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 6951964 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 4431 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 2517343 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 2473442 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 43901 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 128855 # Number of mispredicted indirect branches.
2014-12-23 15:31:20 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2011-01-18 23:30:06 +01:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
2011-05-23 17:59:13 +02:00
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2011-05-23 17:59:13 +02:00
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 191 # Number of system calls
2016-04-09 18:13:40 +02:00
system.cpu.numCycles 223507108 # number of cpu cycles simulated
2011-05-23 17:59:13 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
2016-04-09 18:13:40 +02:00
system.cpu.fetch.icacheStallCycles 12083599 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 309381854 # Number of instructions fetch has processed
system.cpu.fetch.Branches 35971731 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 23348808 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 209499863 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1989645 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 1258 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 93 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 2666 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 82203342 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 33398 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 222582301 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.671920 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.267628 # Number of instructions fetched each cycle (Total)
2011-01-18 23:30:06 +01:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2016-04-09 18:13:40 +02:00
system.cpu.fetch.rateDist::0 62373241 28.02% 28.02% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 40203334 18.06% 46.08% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 28080746 12.62% 58.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 91924980 41.30% 100.00% # Number of instructions fetched each cycle (Total)
2011-01-18 23:30:06 +01:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
2014-09-20 23:18:53 +02:00
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
2016-04-09 18:13:40 +02:00
system.cpu.fetch.rateDist::total 222582301 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.160942 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.384215 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 26238985 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 73050782 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 98117127 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 24314460 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 860947 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 6686817 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 134221 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 348541423 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 3410145 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 860947 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 42548430 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 23450678 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 285531 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 105165670 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 50271045 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 344601348 # Number of instructions processed by rename
system.cpu.rename.SquashedInsts 1453656 # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents 7084396 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 85832 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 7483674 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 23725025 # Number of times rename has blocked due to SQ full
system.cpu.rename.FullRegisterEvents 3279176 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 394880845 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 2465405554 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 335914250 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 192916662 # Number of floating rename lookups
2014-09-20 23:18:53 +02:00
system.cpu.rename.CommittedMaps 372230051 # Number of HB maps that are committed
2016-04-09 18:13:40 +02:00
system.cpu.rename.UndoneMaps 22650794 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 11588 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 11554 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 57533645 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 89989968 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 84391268 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1975718 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 1902358 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 343283622 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 22608 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 339469619 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 966789 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 15494628 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 40533427 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 488 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 222582301 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.525142 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.109331 # Number of insts issued each cycle
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2016-04-09 18:13:40 +02:00
system.cpu.iq.issued_per_cycle::0 42440680 19.07% 19.07% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 76122495 34.20% 53.27% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 59389973 26.68% 79.95% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 34692267 15.59% 95.54% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 9226095 4.15% 99.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 678749 0.30% 99.99% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 32042 0.01% 100.00% # Number of insts issued each cycle
2014-09-20 23:18:53 +02:00
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
2014-09-20 23:18:53 +02:00
system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle
2016-04-09 18:13:40 +02:00
system.cpu.iq.issued_per_cycle::total 222582301 # Number of insts issued each cycle
2011-04-20 03:45:23 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2016-04-09 18:13:40 +02:00
system.cpu.iq.fu_full::IntAlu 9228112 7.75% 7.75% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 7358 0.01% 7.75% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 7.75% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.75% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.75% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.75% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 7.75% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.75% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 7.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 7.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 237798 0.20% 7.95% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.95% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 147681 0.12% 8.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 70485 0.06% 8.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 67886 0.06% 8.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 638269 0.54% 8.73% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 297789 0.25% 8.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 542439 0.46% 9.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.44% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 51542568 43.28% 52.71% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 56315471 47.29% 100.00% # attempts to use FU when none available
2011-04-20 03:45:23 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2011-05-23 17:59:13 +02:00
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
2016-04-09 18:13:40 +02:00
system.cpu.iq.FU_type_0::IntAlu 108184507 31.87% 31.87% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 2148145 0.63% 32.50% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.50% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.50% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.50% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.50% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.50% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.50% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 6792731 2.00% 34.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 8635726 2.54% 37.05% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 3210403 0.95% 37.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 1592905 0.47% 38.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 20864008 6.15% 44.61% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 7178651 2.11% 46.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 7141492 2.10% 48.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 175295 0.05% 48.88% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 90027492 26.52% 75.40% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 83518264 24.60% 100.00% # Type of FU issued
2011-05-23 17:59:13 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2016-04-09 18:13:40 +02:00
system.cpu.iq.FU_type_0::total 339469619 # Type of FU issued
system.cpu.iq.rate 1.518831 # Inst issue rate
system.cpu.iq.fu_busy_cnt 119095856 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.350829 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 738018306 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 235153924 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 219171367 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 283565878 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 123658767 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 116921576 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 293614389 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 164951086 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 5389138 # Number of loads that had data forwarded from stores
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2016-04-09 18:13:40 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 4257693 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 7295 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 11836 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 2015651 # Number of stores squashed
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2016-04-09 18:13:40 +02:00
system.cpu.iew.lsq.thread0.rescheduledLoads 126905 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 613909 # Number of times an access to memory failed due to the cache being blocked
2011-05-23 17:59:13 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2016-04-09 18:13:40 +02:00
system.cpu.iew.iewSquashCycles 860947 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 1344821 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 736472 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 343307622 # Number of instructions dispatched to IQ
2014-09-20 23:18:53 +02:00
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
2016-04-09 18:13:40 +02:00
system.cpu.iew.iewDispLoadInsts 89989968 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 84391268 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 11575 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 7371 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 729404 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 11836 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 437891 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 454375 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 892266 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 337441545 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 89439870 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 2028074 # Number of squashed instructions skipped in execute
2011-05-23 17:59:13 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
2016-04-09 18:13:40 +02:00
system.cpu.iew.exec_nop 1392 # number of nop insts executed
system.cpu.iew.exec_refs 172567373 # number of memory reference insts executed
system.cpu.iew.exec_branches 31555849 # Number of branches executed
system.cpu.iew.exec_stores 83127503 # Number of stores executed
system.cpu.iew.exec_rate 1.509758 # Inst execution rate
system.cpu.iew.wb_sent 336239137 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 336092943 # cumulative count of insts written-back
system.cpu.iew.wb_producers 151867680 # num instructions producing a value
system.cpu.iew.wb_consumers 263704827 # num instructions consuming a value
system.cpu.iew.wb_rate 1.503724 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.575900 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 14172678 # The number of squashed insts skipped by commit
2013-01-08 14:54:16 +01:00
system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards
2016-04-09 18:13:40 +02:00
system.cpu.commit.branchMispredicts 850314 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 220392023 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.487405 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.078236 # Number of insts commited each cycle
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2016-04-09 18:13:40 +02:00
system.cpu.commit.committed_per_cycle::0 89247998 40.50% 40.50% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 67546822 30.65% 71.14% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 20918501 9.49% 80.64% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 13253983 6.01% 86.65% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 8642695 3.92% 90.57% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 4496391 2.04% 92.61% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 3033426 1.38% 93.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 2604506 1.18% 95.17% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 10647701 4.83% 100.00% # Number of insts commited each cycle
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2016-04-09 18:13:40 +02:00
system.cpu.commit.committed_per_cycle::total 220392023 # Number of insts commited each cycle
2015-04-30 21:17:43 +02:00
system.cpu.commit.committedInsts 273037832 # Number of instructions committed
system.cpu.commit.committedOps 327812214 # Number of ops (including micro ops) committed
2011-05-23 17:59:13 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
2014-09-20 23:18:53 +02:00
system.cpu.commit.refs 168107892 # Number of memory references committed
system.cpu.commit.loads 85732275 # Number of loads committed
2011-05-23 17:59:13 +02:00
system.cpu.commit.membars 11033 # Number of memory barriers committed
2015-04-30 21:17:43 +02:00
system.cpu.commit.branches 30563526 # Number of branches committed
2011-05-23 17:59:13 +02:00
system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions.
2014-09-20 23:18:53 +02:00
system.cpu.commit.int_insts 258331704 # Number of committed integer instructions.
system.cpu.commit.function_calls 6225114 # Number of function calls committed.
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2015-04-30 21:17:43 +02:00
system.cpu.commit.op_class_0::IntAlu 104312487 31.82% 31.82% # Class of committed instruction
2014-09-20 23:18:53 +02:00
system.cpu.commit.op_class_0::IntMult 2145917 0.65% 32.48% # Class of committed instruction
2014-09-03 13:42:59 +02:00
system.cpu.commit.op_class_0::IntDiv 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 6594343 2.01% 34.49% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 34.49% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 7943502 2.42% 36.91% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 3118180 0.95% 37.86% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 1563217 0.48% 38.34% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 19652356 6.00% 44.33% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 7136937 2.18% 46.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction
2014-09-20 23:18:53 +02:00
system.cpu.commit.op_class_0::MemRead 85732275 26.15% 74.87% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Class of committed instruction
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2015-04-30 21:17:43 +02:00
system.cpu.commit.op_class_0::total 327812214 # Class of committed instruction
2016-04-09 18:13:40 +02:00
system.cpu.commit.bw_lim_events 10647701 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 551726691 # The number of ROB reads
system.cpu.rob.rob_writes 686162246 # The number of ROB writes
system.cpu.timesIdled 18335 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 924807 # Total number of cycles that the CPU has spent unscheduled due to idling
2015-04-30 21:17:43 +02:00
system.cpu.committedInsts 273037220 # Number of Instructions Simulated
system.cpu.committedOps 327811602 # Number of Ops (including micro ops) Simulated
2016-04-09 18:13:40 +02:00
system.cpu.cpi 0.818596 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.818596 # CPI: Total CPI of All Threads
system.cpu.ipc 1.221604 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.221604 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 325161919 # number of integer regfile reads
system.cpu.int_regfile_writes 134094717 # number of integer regfile writes
system.cpu.fp_regfile_reads 186641875 # number of floating regfile reads
system.cpu.fp_regfile_writes 131668024 # number of floating regfile writes
system.cpu.cc_regfile_reads 1279432977 # number of cc regfile reads
system.cpu.cc_regfile_writes 80060950 # number of cc regfile writes
system.cpu.misc_regfile_reads 1175447344 # number of misc regfile reads
2013-01-08 14:54:16 +01:00
system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes
2016-04-09 18:13:40 +02:00
system.cpu.dcache.tags.replacements 1542955 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.836799 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 162076726 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1543467 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 105.008222 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 85416000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.836799 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999681 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999681 # Average percentage of cache occupancy
2014-09-20 23:18:53 +02:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-04-09 18:13:40 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id
2014-09-20 23:18:53 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-04-09 18:13:40 +02:00
system.cpu.dcache.tags.tag_accesses 333528119 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 333528119 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 81065236 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 81065236 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 80920030 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 80920030 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 69611 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 69611 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 10906 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 10906 # number of LoadLockedReq hits
2013-01-08 14:54:16 +01:00
system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
2016-04-09 18:13:40 +02:00
system.cpu.dcache.demand_hits::cpu.data 161985266 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 161985266 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 162054877 # number of overall hits
system.cpu.dcache.overall_hits::total 162054877 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 2782957 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 2782957 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1132669 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1132669 # number of WriteReq misses
2015-03-02 11:04:20 +01:00
system.cpu.dcache.SoftPFReq_misses::cpu.data 18 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 18 # number of SoftPFReq misses
2016-04-09 18:13:40 +02:00
system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 3915626 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 3915626 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 3915644 # number of overall misses
system.cpu.dcache.overall_misses::total 3915644 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 31092984500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 31092984500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 9127104911 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 9127104911 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 182000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 182000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 40220089411 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 40220089411 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 40220089411 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 40220089411 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 83848193 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 83848193 # number of ReadReq accesses(hits+misses)
2014-09-20 23:18:53 +02:00
system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses)
2016-04-09 18:13:40 +02:00
system.cpu.dcache.SoftPFReq_accesses::cpu.data 69629 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 69629 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10910 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 10910 # number of LoadLockedReq accesses(hits+misses)
2013-01-08 14:54:16 +01:00
system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
2016-04-09 18:13:40 +02:00
system.cpu.dcache.demand_accesses::cpu.data 165900892 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 165900892 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 165970521 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 165970521 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033190 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.033190 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013804 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.013804 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000259 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.000259 # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000367 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000367 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.023602 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.023602 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.023592 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.023592 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11172.642804 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 11172.642804 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8058.051303 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 8058.051303 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 45500 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 45500 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 10271.688208 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 10271.688208 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 10271.640990 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 10271.640990 # average overall miss latency
2014-12-23 15:31:20 +01:00
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2016-04-09 18:13:40 +02:00
system.cpu.dcache.blocked_cycles::no_targets 1079488 # number of cycles access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
2016-04-09 18:13:40 +02:00
system.cpu.dcache.blocked::no_targets 136770 # number of cycles access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2016-04-09 18:13:40 +02:00
system.cpu.dcache.avg_blocked_cycles::no_targets 7.892725 # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 1542955 # number of writebacks
system.cpu.dcache.writebacks::total 1542955 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1460236 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 1460236 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 911920 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 911920 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 2372156 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 2372156 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 2372156 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 2372156 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1322721 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1322721 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220749 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 220749 # number of WriteReq MSHR misses
2014-09-20 23:18:53 +02:00
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 11 # number of SoftPFReq MSHR misses
2016-04-09 18:13:40 +02:00
system.cpu.dcache.demand_mshr_misses::cpu.data 1543470 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1543470 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1543481 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1543481 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15298451500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 15298451500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1831859691 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1831859691 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 695500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 695500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17130311191 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 17130311191 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17131006691 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 17131006691 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015775 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015775 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002690 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002690 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000158 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000158 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009304 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.009304 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009300 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.009300 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11565.894471 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11565.894471 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8298.382738 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8298.382738 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 63227.272727 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 63227.272727 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11098.570877 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11098.570877 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11098.942385 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11098.942385 # average overall mshr miss latency
system.cpu.icache.tags.replacements 726201 # number of replacements
system.cpu.icache.tags.tagsinuse 511.803602 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 81470529 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 726713 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 112.108259 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 331355500 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 511.803602 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.999616 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.999616 # Average percentage of cache occupancy
2014-12-23 15:31:20 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-04-09 18:13:40 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 242 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id
2015-03-02 11:04:20 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::4 69 # Occupied blocks per task id
2014-12-23 15:31:20 +01:00
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-04-09 18:13:40 +02:00
system.cpu.icache.tags.tag_accesses 165133375 # Number of tag accesses
system.cpu.icache.tags.data_accesses 165133375 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 81470529 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 81470529 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 81470529 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 81470529 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 81470529 # number of overall hits
system.cpu.icache.overall_hits::total 81470529 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 732796 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 732796 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 732796 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 732796 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 732796 # number of overall misses
system.cpu.icache.overall_misses::total 732796 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 6565806949 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 6565806949 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 6565806949 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 6565806949 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 6565806949 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 6565806949 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 82203325 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 82203325 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 82203325 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 82203325 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 82203325 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 82203325 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008914 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.008914 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.008914 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.008914 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.008914 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.008914 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8959.938303 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 8959.938303 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 8959.938303 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 8959.938303 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 8959.938303 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 8959.938303 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 64284 # number of cycles access was blocked
2015-07-03 16:15:03 +02:00
system.cpu.icache.blocked_cycles::no_targets 94 # number of cycles access was blocked
2016-04-09 18:13:40 +02:00
system.cpu.icache.blocked::no_mshrs 3051 # number of cycles access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked
2016-04-09 18:13:40 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 21.069813 # average number of cycles each access was blocked
2015-07-03 16:15:03 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets 31.333333 # average number of cycles each access was blocked
2016-04-09 18:13:40 +02:00
system.cpu.icache.writebacks::writebacks 726201 # number of writebacks
system.cpu.icache.writebacks::total 726201 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 6071 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 6071 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 6071 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 6071 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 6071 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 6071 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 726725 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 726725 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 726725 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 726725 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 726725 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 726725 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6109081458 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 6109081458 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6109081458 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 6109081458 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6109081458 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 6109081458 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008841 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008841 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008841 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.008841 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008841 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.008841 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8406.318013 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8406.318013 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8406.318013 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 8406.318013 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8406.318013 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 8406.318013 # average overall mshr miss latency
system.cpu.l2cache.prefetcher.num_hwpf_issued 402434 # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified 402547 # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit 102 # number of redundant prefetches already in prefetch queue
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.prefetcher.pfSpanPage 28085 # number of prefetches not generated due to page crossing
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.tags.replacements 0 # number of replacements
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.tags.tagsinuse 5603.177963 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 3041133 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 6750 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 450.538222 # Average number of references to valid blocks.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.tags.occ_blocks::writebacks 5495.535708 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 107.642255 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.335421 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.006570 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.341991 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022 497 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 6253 # Occupied blocks per task id
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1022::0 16 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1 22 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::2 344 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1022::3 2 # Occupied blocks per task id
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.tags.age_task_id_blocks_1022::4 113 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 146 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 912 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 72 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 5048 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022 0.030334 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.381653 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 69530063 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 69530063 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 968360 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 968360 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 1046226 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 1046226 # number of WritebackClean hits
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.ReadExReq_hits::cpu.data 219964 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 219964 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 716938 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 716938 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1251135 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 1251135 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 716938 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 1471099 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2188037 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 716938 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 1471099 # number of overall hits
system.cpu.l2cache.overall_hits::total 2188037 # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 781 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 781 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 9708 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 9708 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 71587 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 71587 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 9708 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 72368 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 82076 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 9708 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 72368 # number of overall misses
system.cpu.l2cache.overall_misses::total 82076 # number of overall misses
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 40000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 40000 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56104500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 56104500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 688634000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 688634000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5061315000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 5061315000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 688634000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 5117419500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 5806053500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 688634000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 5117419500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 5806053500 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 968360 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 968360 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 1046226 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 1046226 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 14 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 14 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 220745 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 220745 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 726646 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 726646 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1322722 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 1322722 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 726646 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1543467 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2270113 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 726646 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1543467 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2270113 # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.928571 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.928571 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003538 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.003538 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.013360 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.013360 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.054121 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.054121 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.013360 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.046887 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.036155 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.013360 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.046887 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.036155 # miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 3076.923077 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 3076.923077 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71836.747759 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71836.747759 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 70934.693037 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 70934.693037 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 70701.593865 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 70701.593865 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70934.693037 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70713.844517 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 70739.966616 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70934.693037 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70713.844517 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 70739.966616 # average overall miss latency
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 51 # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total 51 # number of ReadExReq MSHR hits
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 12 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 12 # number of ReadCleanReq MSHR hits
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 34 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 34 # number of ReadSharedReq MSHR hits
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.demand_mshr_hits::cpu.data 85 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 97 # number of demand (read+write) MSHR hits
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.overall_mshr_hits::cpu.data 85 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 97 # number of overall MSHR hits
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 51651 # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total 51651 # number of HardPFReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 730 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 730 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 9696 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 9696 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 71553 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 71553 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 9696 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 72283 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 81979 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 9696 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 72283 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 51651 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 133630 # number of overall MSHR misses
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 178131300 # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 178131300 # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 187000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 187000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 50303500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 50303500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 629910500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 629910500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4630072500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4630072500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 629910500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4680376000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 5310286500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 629910500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4680376000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 178131300 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 5488417800 # number of overall MSHR miss cycles
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.928571 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.928571 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003307 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003307 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.013343 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.013343 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.054095 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.054095 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.013343 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.046832 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.036112 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.013343 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.046832 # mshr miss rate for overall accesses
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.overall_mshr_miss_rate::total 0.058865 # mshr miss rate for overall accesses
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3448.748330 # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3448.748330 # average HardPFReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14384.615385 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14384.615385 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68908.904110 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68908.904110 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64966.016914 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64966.016914 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64708.293153 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64708.293153 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64966.016914 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64750.715936 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64776.180485 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64966.016914 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64750.715936 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3448.748330 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41071.748859 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 4539362 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2269187 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254586 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 130262 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 52910 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 77352 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 2049447 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 968360 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 1300796 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 81249 # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq 53022 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 14 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 14 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 220745 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 220745 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 726725 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1322722 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2179572 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4629917 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 6809489 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 92982208 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 197531008 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 290513216 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 134350 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 2404477 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.192237 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.468638 # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-04-09 18:13:40 +02:00
system.cpu.toL2Bus.snoop_fanout::0 2019600 83.99% 83.99% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 307525 12.79% 96.78% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 77352 3.22% 100.00% # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2016-04-09 18:13:40 +02:00
system.cpu.toL2Bus.snoop_fanout::total 2404477 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 4538837000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 4.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1090392888 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 2315538337 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%)
system.membus.trans_dist::ReadResp 83887 # Transaction distribution
system.membus.trans_dist::UpgradeReq 13 # Transaction distribution
system.membus.trans_dist::ReadExReq 730 # Transaction distribution
system.membus.trans_dist::ReadExResp 730 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 83887 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 169247 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 169247 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 5415488 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 5415488 # Cumulative packet size per connected master and slave (bytes)
2014-12-23 15:31:20 +01:00
system.membus.snoops 0 # Total snoops (count)
2016-04-09 18:13:40 +02:00
system.membus.snoop_fanout::samples 84630 # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-04-09 18:13:40 +02:00
system.membus.snoop_fanout::0 84630 100.00% 100.00% # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
2016-04-09 18:13:40 +02:00
system.membus.snoop_fanout::total 84630 # Request fanout histogram
system.membus.reqLayer0.occupancy 108151910 # Layer occupancy (ticks)
2015-11-06 09:26:50 +01:00
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
2016-04-09 18:13:40 +02:00
system.membus.respLayer1.occupancy 445724357 # Layer occupancy (ticks)
2015-11-06 09:26:50 +01:00
system.membus.respLayer1.utilization 0.4 # Layer utilization (%)
2011-01-18 23:30:06 +01:00
---------- End Simulation Statistics ----------
