gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.526127                       # Number of seconds simulated
sim_ticks                                2526126762000                       # Number of ticks simulated
final_tick                               2526126762000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  60304                       # Simulator instruction rate (inst/s)
host_op_rate                                    77594                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2525902204                       # Simulator tick rate (ticks/s)
host_mem_usage                                 424400                       # Number of bytes of host memory used
host_seconds                                  1000.09                       # Real time elapsed on the host
sim_insts                                    60309150                       # Number of instructions simulated
sim_ops                                      77600646                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::realview.clcd    119537664                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker         2752                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst            797888                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           9093912                       # Number of bytes read from this memory
system.physmem.bytes_read::total            129432344                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       797888                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          797888                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      3783552                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data        3016072                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6799624                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd      14942208                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker           43                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              12467                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             142128                       # Number of read requests responded to by this memory
system.physmem.num_reads::total              15096848                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           59118                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data            754018                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               813136                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        47320533                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker           1089                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             51                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               315854                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              3599943                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                51237470                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          315854                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             315854                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1497768                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data             1193951                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2691719                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1497768                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       47320533                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker          1089                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            51                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              315854                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             4793894                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               53929189                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                      15096848                       # Number of read requests accepted
system.physmem.writeReqs                       813136                       # Number of write requests accepted
system.physmem.readBursts                    15096848                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     813136                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                963809856                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                   2388416                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   6900096                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                 129432344                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                6799624                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                    37319                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                  705316                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs           4693                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0              943581                       # Per bank write bursts
system.physmem.perBankRdBursts::1              943177                       # Per bank write bursts
system.physmem.perBankRdBursts::2              939217                       # Per bank write bursts
system.physmem.perBankRdBursts::3              939246                       # Per bank write bursts
system.physmem.perBankRdBursts::4              943119                       # Per bank write bursts
system.physmem.perBankRdBursts::5              943143                       # Per bank write bursts
system.physmem.perBankRdBursts::6              939192                       # Per bank write bursts
system.physmem.perBankRdBursts::7              938854                       # Per bank write bursts
system.physmem.perBankRdBursts::8              943994                       # Per bank write bursts
system.physmem.perBankRdBursts::9              943547                       # Per bank write bursts
system.physmem.perBankRdBursts::10             939009                       # Per bank write bursts
system.physmem.perBankRdBursts::11             937977                       # Per bank write bursts
system.physmem.perBankRdBursts::12             943925                       # Per bank write bursts
system.physmem.perBankRdBursts::13             943586                       # Per bank write bursts
system.physmem.perBankRdBursts::14             939160                       # Per bank write bursts
system.physmem.perBankRdBursts::15             938802                       # Per bank write bursts
system.physmem.perBankWrBursts::0                6706                       # Per bank write bursts
system.physmem.perBankWrBursts::1                6463                       # Per bank write bursts
system.physmem.perBankWrBursts::2                6599                       # Per bank write bursts
system.physmem.perBankWrBursts::3                6631                       # Per bank write bursts
system.physmem.perBankWrBursts::4                6542                       # Per bank write bursts
system.physmem.perBankWrBursts::5                6795                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6787                       # Per bank write bursts
system.physmem.perBankWrBursts::7                6728                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7129                       # Per bank write bursts
system.physmem.perBankWrBursts::9                6879                       # Per bank write bursts
system.physmem.perBankWrBursts::10               6534                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6185                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7139                       # Per bank write bursts
system.physmem.perBankWrBursts::13               6761                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7032                       # Per bank write bursts
system.physmem.perBankWrBursts::15               6904                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    2526125654500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                      38                       # Read request sizes (log2)
system.physmem.readPktSize::3                14942208                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  154602                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                 754018                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  59118                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                   1175583                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                   1121241                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                   1077080                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                   3628602                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                   2607512                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                   2594359                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                   2599949                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     53287                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     57711                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                     21124                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                    20900                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                    20768                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                    20512                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                    20375                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                    20258                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                    20166                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                       91                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        7                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      4767                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      5448                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      4894                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      5081                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      5199                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      4872                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      4884                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      4873                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      4830                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      4808                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     4806                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     4793                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     4788                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     4799                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     4794                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     4795                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     4787                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4809                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     4821                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     4801                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     4805                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5153                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                      137                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                       65                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                       11                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        85983                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean    11289.547748                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean    1006.032615                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev   16787.302098                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-71          23431     27.25%     27.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-135        14045     16.33%     43.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-199         2670      3.11%     46.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-263         2200      2.56%     49.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-327         1296      1.51%     50.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-391         1149      1.34%     52.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-455          926      1.08%     53.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-519          910      1.06%     54.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-583          583      0.68%     54.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-647          573      0.67%     55.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-711          527      0.61%     56.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-775          540      0.63%     56.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-839          283      0.33%     57.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-903          315      0.37%     57.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-967          148      0.17%     57.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1031          512      0.60%     58.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1095          103      0.12%     58.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1159          143      0.17%     58.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1223           77      0.09%     58.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1287          250      0.29%     58.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1351           57      0.07%     59.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1415          507      0.59%     59.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1479           36      0.04%     59.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1543          193      0.22%     59.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1607           17      0.02%     59.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1671          103      0.12%     60.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1735           18      0.02%     60.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1799           71      0.08%     60.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1863           17      0.02%     60.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1927           58      0.07%     60.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1991           16      0.02%     60.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2055          468      0.54%     60.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2119           10      0.01%     60.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2183           32      0.04%     60.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2247           13      0.02%     60.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2311          249      0.29%     61.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2375            8      0.01%     61.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2439           28      0.03%     61.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2503            7      0.01%     61.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2567           30      0.03%     61.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2631            8      0.01%     61.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2695           18      0.02%     61.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2759            6      0.01%     61.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2823          116      0.13%     61.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2887           10      0.01%     61.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2951           18      0.02%     61.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3015            4      0.00%     61.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3079          420      0.49%     61.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3143            7      0.01%     61.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3207           24      0.03%     61.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3271            6      0.01%     61.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3335           25      0.03%     61.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3399            6      0.01%     61.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3463           21      0.02%     62.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3527            6      0.01%     62.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3591          157      0.18%     62.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3655            5      0.01%     62.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3719           17      0.02%     62.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3783            9      0.01%     62.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3847           20      0.02%     62.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3911           11      0.01%     62.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3975           15      0.02%     62.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4039           13      0.02%     62.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4103          363      0.42%     62.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4167            9      0.01%     62.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4231           13      0.02%     62.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4295            7      0.01%     62.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4359          108      0.13%     62.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4423           18      0.02%     62.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4487           14      0.02%     62.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4551           12      0.01%     62.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4615          161      0.19%     63.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4679            8      0.01%     63.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4743           15      0.02%     63.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4807            2      0.00%     63.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4871           23      0.03%     63.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4935            6      0.01%     63.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4999           14      0.02%     63.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5063            4      0.00%     63.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5127          356      0.41%     63.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5191            5      0.01%     63.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5255           11      0.01%     63.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5319           11      0.01%     63.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5383          163      0.19%     63.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5447            2      0.00%     63.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5511           16      0.02%     63.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568-5575            2      0.00%     63.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5639           50      0.06%     63.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5703            6      0.01%     63.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760-5767           13      0.02%     63.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5824-5831            4      0.00%     63.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5895          197      0.23%     64.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952-5959            3      0.00%     64.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6023            9      0.01%     64.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6087            7      0.01%     64.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6151          223      0.26%     64.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6215            4      0.00%     64.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6279           13      0.02%     64.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6336-6343            5      0.01%     64.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6407          140      0.16%     64.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6471            2      0.00%     64.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6535            8      0.01%     64.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6599            2      0.00%     64.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6663           88      0.10%     64.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6727            2      0.00%     64.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6791           14      0.02%     64.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6855            3      0.00%     64.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6919          158      0.18%     64.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6976-6983            6      0.01%     64.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7047           14      0.02%     64.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7104-7111            1      0.00%     64.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7175          345      0.40%     65.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7232-7239            1      0.00%     65.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7296-7303            5      0.01%     65.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7360-7367            8      0.01%     65.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7431           13      0.02%     65.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7488-7495            4      0.00%     65.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7559           18      0.02%     65.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7616-7623            6      0.01%     65.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7687          141      0.16%     65.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7744-7751            2      0.00%     65.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7815            6      0.01%     65.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7943           41      0.05%     65.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8007            2      0.00%     65.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8071           10      0.01%     65.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8199          399      0.46%     66.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8256-8263            1      0.00%     66.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8448-8455           36      0.04%     66.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8576-8583            2      0.00%     66.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8704-8711          130      0.15%     66.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8896-8903            2      0.00%     66.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8960-8967            5      0.01%     66.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9088-9095            1      0.00%     66.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9216-9223          341      0.40%     66.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9344-9351            3      0.00%     66.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9472-9479          145      0.17%     66.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9536-9543            1      0.00%     66.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9600-9607            2      0.00%     66.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9728-9735           78      0.09%     67.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9792-9799            2      0.00%     67.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9856-9863            3      0.00%     67.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9984-9991          133      0.15%     67.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10048-10055            2      0.00%     67.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10112-10119            3      0.00%     67.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10240-10247          212      0.25%     67.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10368-10375            2      0.00%     67.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10496-10503          150      0.17%     67.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10688-10695            1      0.00%     67.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10752-10759           41      0.05%     67.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10880-10887            1      0.00%     67.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10944-10951            2      0.00%     67.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11008-11015          153      0.18%     67.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11136-11143            4      0.00%     67.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11264-11271          349      0.41%     68.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11520-11527            8      0.01%     68.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11648-11655            3      0.00%     68.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11776-11783          141      0.16%     68.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11904-11911            3      0.00%     68.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11968-11975            1      0.00%     68.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12032-12039           94      0.11%     68.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12096-12103            2      0.00%     68.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12160-12167            4      0.00%     68.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12288-12295          334      0.39%     68.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12352-12359            1      0.00%     68.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12544-12551           13      0.02%     68.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12672-12679            3      0.00%     68.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12736-12743            1      0.00%     68.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12800-12807          141      0.16%     69.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12864-12871            1      0.00%     69.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12992-12999            1      0.00%     69.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13056-13063            6      0.01%     69.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13120-13127            1      0.00%     69.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13184-13191            2      0.00%     69.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13312-13319          399      0.46%     69.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13376-13383            1      0.00%     69.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13440-13447            1      0.00%     69.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13568-13575           94      0.11%     69.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13760-13767            2      0.00%     69.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13824-13831            2      0.00%     69.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13952-13959            3      0.00%     69.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14016-14023            1      0.00%     69.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14080-14087          214      0.25%     69.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14144-14151            2      0.00%     69.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14208-14215            4      0.00%     69.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14272-14279            1      0.00%     69.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14336-14343          420      0.49%     70.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14592-14599            5      0.01%     70.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14720-14727            1      0.00%     70.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14848-14855           22      0.03%     70.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14976-14983            1      0.00%     70.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15104-15111          141      0.16%     70.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15168-15175            1      0.00%     70.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15232-15239            1      0.00%     70.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15360-15367          335      0.39%     71.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15424-15431            1      0.00%     71.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15488-15495            1      0.00%     71.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15552-15559            1      0.00%     71.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15616-15623           80      0.09%     71.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15808-15815            2      0.00%     71.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15872-15879            5      0.01%     71.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15936-15943            2      0.00%     71.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16000-16007            2      0.00%     71.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16064-16071            1      0.00%     71.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16128-16135          143      0.17%     71.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16256-16263            6      0.01%     71.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16384-16391          673      0.78%     72.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16512-16519            1      0.00%     72.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16640-16647          144      0.17%     72.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16896-16903            7      0.01%     72.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16960-16967            2      0.00%     72.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17024-17031            1      0.00%     72.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17152-17159           81      0.09%     72.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17280-17287            2      0.00%     72.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17408-17415          336      0.39%     72.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17536-17543            2      0.00%     72.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17664-17671          135      0.16%     72.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17728-17735            1      0.00%     72.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17792-17799            4      0.00%     72.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17920-17927           25      0.03%     72.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18048-18055            1      0.00%     72.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18112-18119            1      0.00%     72.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18176-18183            6      0.01%     72.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18240-18247            1      0.00%     72.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18304-18311            2      0.00%     72.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18432-18439          419      0.49%     73.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18560-18567            2      0.00%     73.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18688-18695          214      0.25%     73.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18752-18759            1      0.00%     73.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18944-18951            4      0.00%     73.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19072-19079            1      0.00%     73.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19200-19207           97      0.11%     73.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19264-19271            2      0.00%     73.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19328-19335            2      0.00%     73.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19456-19463          391      0.45%     74.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19584-19591            1      0.00%     74.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19712-19719           10      0.01%     74.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19840-19847            3      0.00%     74.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19904-19911            1      0.00%     74.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19968-19975          139      0.16%     74.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20032-20039            1      0.00%     74.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20160-20167            2      0.00%     74.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20224-20231           13      0.02%     74.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20352-20359            4      0.00%     74.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20480-20487          331      0.38%     74.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20608-20615            1      0.00%     74.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20672-20679            1      0.00%     74.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20736-20743           94      0.11%     75.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20800-20807            1      0.00%     75.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20864-20871            1      0.00%     75.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20928-20935            2      0.00%     75.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20992-20999          142      0.17%     75.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21120-21127            2      0.00%     75.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21184-21191            1      0.00%     75.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21248-21255           13      0.02%     75.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21376-21383            2      0.00%     75.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21504-21511          343      0.40%     75.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21632-21639            3      0.00%     75.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21696-21703            1      0.00%     75.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21760-21767          150      0.17%     75.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21888-21895            1      0.00%     75.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21952-21959            1      0.00%     75.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22016-22023           38      0.04%     75.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22080-22087            1      0.00%     75.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22144-22151            3      0.00%     75.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22272-22279          148      0.17%     76.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22400-22407            2      0.00%     76.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22464-22471            1      0.00%     76.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22528-22535          208      0.24%     76.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22656-22663            1      0.00%     76.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22720-22727            2      0.00%     76.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22784-22791          129      0.15%     76.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22848-22855            1      0.00%     76.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23040-23047           76      0.09%     76.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23104-23111            1      0.00%     76.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23168-23175            2      0.00%     76.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23296-23303          148      0.17%     76.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23424-23431            1      0.00%     76.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23488-23495            1      0.00%     76.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23552-23559          338      0.39%     77.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23808-23815           10      0.01%     77.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23936-23943            2      0.00%     77.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24064-24071          128      0.15%     77.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24128-24135            1      0.00%     77.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24256-24263            2      0.00%     77.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24320-24327           34      0.04%     77.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24448-24455            4      0.00%     77.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24512-24519            1      0.00%     77.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24576-24583          281      0.33%     77.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24640-24647            2      0.00%     77.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24704-24711            3      0.00%     77.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24768-24775            1      0.00%     77.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24832-24839           36      0.04%     77.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24960-24967            1      0.00%     77.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25088-25095          132      0.15%     77.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25152-25159            1      0.00%     77.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25216-25223            1      0.00%     77.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25344-25351            9      0.01%     77.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25472-25479            2      0.00%     77.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25536-25543            1      0.00%     77.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25600-25607          331      0.38%     78.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25728-25735            1      0.00%     78.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25792-25799            1      0.00%     78.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25856-25863          146      0.17%     78.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25920-25927            1      0.00%     78.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25984-25991            1      0.00%     78.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26112-26119           78      0.09%     78.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26176-26183            1      0.00%     78.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26240-26247            2      0.00%     78.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26304-26311            1      0.00%     78.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26368-26375          128      0.15%     78.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26432-26439            1      0.00%     78.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26496-26503            6      0.01%     78.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26560-26567            1      0.00%     78.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26624-26631          207      0.24%     78.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26688-26695            1      0.00%     78.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26752-26759            3      0.00%     78.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26816-26823            1      0.00%     78.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26880-26887          146      0.17%     79.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26944-26951            3      0.00%     79.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27008-27015            1      0.00%     79.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27136-27143           38      0.04%     79.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27264-27271            1      0.00%     79.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27392-27399          151      0.18%     79.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27456-27463            1      0.00%     79.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27520-27527            3      0.00%     79.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27584-27591            2      0.00%     79.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27648-27655          337      0.39%     79.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27712-27719            1      0.00%     79.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27840-27847            2      0.00%     79.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27904-27911           13      0.02%     79.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27968-27975            1      0.00%     79.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28032-28039            1      0.00%     79.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28160-28167          141      0.16%     79.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28224-28231            1      0.00%     79.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28288-28295            1      0.00%     79.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28416-28423           97      0.11%     79.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28544-28551            5      0.01%     79.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28608-28615            4      0.00%     79.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28672-28679          328      0.38%     80.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28800-28807            1      0.00%     80.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28864-28871            1      0.00%     80.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28928-28935           12      0.01%     80.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29056-29063            2      0.00%     80.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29120-29127            1      0.00%     80.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29184-29191          141      0.16%     80.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29312-29319            1      0.00%     80.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29440-29447            7      0.01%     80.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29568-29575            3      0.00%     80.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29696-29703          399      0.46%     81.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29824-29831            1      0.00%     81.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29888-29895            2      0.00%     81.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29952-29959           90      0.10%     81.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30144-30151            2      0.00%     81.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30208-30215            5      0.01%     81.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30336-30343            1      0.00%     81.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30400-30407            1      0.00%     81.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30464-30471          214      0.25%     81.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30528-30535            1      0.00%     81.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30592-30599            3      0.00%     81.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30656-30663            1      0.00%     81.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30720-30727          415      0.48%     81.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30848-30855            2      0.00%     81.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30976-30983            5      0.01%     81.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31040-31047            1      0.00%     81.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31104-31111            1      0.00%     81.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31168-31175            3      0.00%     81.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31232-31239           21      0.02%     81.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31360-31367            2      0.00%     81.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31424-31431            1      0.00%     81.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31488-31495          138      0.16%     82.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31616-31623            3      0.00%     82.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31744-31751          338      0.39%     82.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31872-31879            2      0.00%     82.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31936-31943            1      0.00%     82.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32000-32007           78      0.09%     82.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32192-32199            1      0.00%     82.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32256-32263            9      0.01%     82.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32384-32391            1      0.00%     82.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32448-32455            2      0.00%     82.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32512-32519          145      0.17%     82.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32576-32583            1      0.00%     82.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32640-32647            1      0.00%     82.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32768-32775          671      0.78%     83.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32960-32967            1      0.00%     83.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33024-33031          141      0.16%     83.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33152-33159            1      0.00%     83.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33280-33287            7      0.01%     83.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33344-33351            1      0.00%     83.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33408-33415            4      0.00%     83.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33536-33543           85      0.10%     83.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33600-33607            2      0.00%     83.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33664-33671            1      0.00%     83.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33728-33735            1      0.00%     83.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33792-33799          348      0.40%     84.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34048-34055          136      0.16%     84.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34304-34311           21      0.02%     84.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34368-34375            1      0.00%     84.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34432-34439            3      0.00%     84.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34496-34503            2      0.00%     84.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34560-34567            8      0.01%     84.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34688-34695            2      0.00%     84.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34816-34823          412      0.48%     84.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35072-35079          212      0.25%     85.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35328-35335            5      0.01%     85.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35456-35463            3      0.00%     85.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35584-35591           91      0.11%     85.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35840-35847          392      0.46%     85.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35904-35911            1      0.00%     85.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35968-35975            2      0.00%     85.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36096-36103            8      0.01%     85.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36352-36359          140      0.16%     85.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36480-36487            4      0.00%     85.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36544-36551            1      0.00%     85.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36608-36615           12      0.01%     85.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36864-36871          327      0.38%     86.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36928-36935            1      0.00%     86.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37120-37127           90      0.10%     86.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37248-37255            1      0.00%     86.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37312-37319            1      0.00%     86.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37376-37383          141      0.16%     86.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37440-37447            1      0.00%     86.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37504-37511            3      0.00%     86.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37632-37639           10      0.01%     86.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37696-37703            1      0.00%     86.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37760-37767            1      0.00%     86.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37888-37895          334      0.39%     86.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37952-37959            1      0.00%     86.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38080-38087            1      0.00%     86.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38144-38151          149      0.17%     87.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38272-38279            1      0.00%     87.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38400-38407           37      0.04%     87.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38528-38535            2      0.00%     87.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38592-38599            1      0.00%     87.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38656-38663          150      0.17%     87.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38784-38791            1      0.00%     87.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38848-38855            1      0.00%     87.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38912-38919          205      0.24%     87.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39168-39175          127      0.15%     87.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39424-39431           76      0.09%     87.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39552-39559            2      0.00%     87.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39616-39623            1      0.00%     87.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39680-39687          146      0.17%     88.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39936-39943          330      0.38%     88.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40000-40007            1      0.00%     88.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40064-40071            1      0.00%     88.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40192-40199            7      0.01%     88.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40384-40391            1      0.00%     88.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40448-40455          132      0.15%     88.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40576-40583            4      0.00%     88.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40704-40711           37      0.04%     88.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40896-40903            1      0.00%     88.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40960-40967          277      0.32%     88.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41088-41095            1      0.00%     88.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41152-41159            1      0.00%     88.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41216-41223           34      0.04%     88.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41472-41479          128      0.15%     89.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41600-41607            1      0.00%     89.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41728-41735           10      0.01%     89.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41856-41863            1      0.00%     89.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41920-41927            1      0.00%     89.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41984-41991          332      0.39%     89.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42240-42247          142      0.17%     89.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42368-42375            1      0.00%     89.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42432-42439            1      0.00%     89.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42496-42503           76      0.09%     89.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42624-42631            2      0.00%     89.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42688-42695            1      0.00%     89.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42752-42759          131      0.15%     89.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42816-42823            1      0.00%     89.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42880-42887            2      0.00%     89.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43008-43015          208      0.24%     90.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43264-43271          145      0.17%     90.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43392-43399            1      0.00%     90.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43456-43463            1      0.00%     90.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43520-43527           36      0.04%     90.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43648-43655            2      0.00%     90.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43776-43783          152      0.18%     90.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43840-43847            1      0.00%     90.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44032-44039          340      0.40%     90.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44160-44167            1      0.00%     90.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44224-44231            1      0.00%     90.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44288-44295            8      0.01%     91.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44416-44423            2      0.00%     91.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44544-44551          144      0.17%     91.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44608-44615            2      0.00%     91.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44672-44679            2      0.00%     91.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44800-44807           94      0.11%     91.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45056-45063          328      0.38%     91.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45184-45191            3      0.00%     91.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45312-45319           12      0.01%     91.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45376-45383            1      0.00%     91.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45568-45575          141      0.16%     91.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45632-45639            1      0.00%     91.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45696-45703            1      0.00%     91.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45760-45767            1      0.00%     91.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45824-45831           11      0.01%     91.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45952-45959            1      0.00%     91.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46080-46087          393      0.46%     92.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46272-46279            1      0.00%     92.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46336-46343           91      0.11%     92.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46464-46471            1      0.00%     92.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46528-46535            1      0.00%     92.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46592-46599            4      0.00%     92.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46720-46727            2      0.00%     92.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46848-46855          211      0.25%     92.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47040-47047            2      0.00%     92.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47104-47111          416      0.48%     93.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47168-47175            1      0.00%     93.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47232-47239            1      0.00%     93.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47296-47303            1      0.00%     93.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47360-47367            4      0.00%     93.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47488-47495            2      0.00%     93.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47552-47559            1      0.00%     93.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47616-47623           32      0.04%     93.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47744-47751            1      0.00%     93.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47808-47815            2      0.00%     93.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47872-47879          141      0.16%     93.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47936-47943            1      0.00%     93.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48128-48135          335      0.39%     93.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48192-48199            1      0.00%     93.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48384-48391           74      0.09%     93.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48512-48519            1      0.00%     93.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48640-48647            4      0.00%     93.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48768-48775           71      0.08%     93.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48896-48903          140      0.16%     94.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48960-48967            4      0.00%     94.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49024-49031            2      0.00%     94.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49088-49095            1      0.00%     94.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49152-49159         5017      5.83%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49280-49287            1      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49408-49415            1      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49600-49607            1      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49792-49799            1      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50240-50247            1      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50304-50311            3      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50368-50375            1      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50432-50439            2      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50560-50567            2      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50624-50631            1      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50688-50695            4      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50752-50759            1      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50880-50887            2      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51008-51015            3      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51072-51079            1      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51136-51143            1      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51200-51207            1      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51328-51335            2      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51392-51399            1      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51456-51463            2      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51520-51527            1      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51968-51975            2      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          85983                       # Bytes accessed per row activation
system.physmem.totQLat                   365185132750                       # Total ticks spent queuing
system.physmem.totMemAccLat              457949856500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                  75297645000                       # Total ticks spent in databus transfers
system.physmem.totBankLat                 17467078750                       # Total ticks spent accessing banks
system.physmem.avgQLat                       24249.44                       # Average queueing delay per DRAM burst
system.physmem.avgBankLat                     1159.87                       # Average bank access latency per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  30409.31                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         381.54                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.73                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       51.24                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.69                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           3.00                       # Data bus utilization in percentage
system.physmem.busUtilRead                       2.98                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         0.18                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        14.56                       # Average write queue length when enqueuing
system.physmem.readRowHits                   14988012                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     93348                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   99.53                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  86.58                       # Row buffer hit rate for writes
system.physmem.avgGap                       158776.13                       # Average gap between requests
system.physmem.pageHitRate                      99.43                       # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent               2.53                       # Percentage of time for which DRAM has all the banks in precharge state
system.realview.nvmem.bytes_read::cpu.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              1                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst            25                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               25                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst           25                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           25                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst           25                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              25                       # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput                     54878485                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq            16149469                       # Transaction distribution
system.membus.trans_dist::ReadResp           16149469                       # Transaction distribution
system.membus.trans_dist::WriteReq             763349                       # Transaction distribution
system.membus.trans_dist::WriteResp            763349                       # Transaction distribution
system.membus.trans_dist::Writeback             59118                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4690                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            4693                       # Transaction distribution
system.membus.trans_dist::ReadExReq            131452                       # Transaction distribution
system.membus.trans_dist::ReadExResp           131452                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave      2383044                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port            2                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         3760                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio            2                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1885820                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4272628                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     29884416                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total     29884416                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total               34157044                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave      2390454                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port           64                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         7520                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio            4                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16694304                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     19092346                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    119537664                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total    119537664                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total           138630010                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus              138630010                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy          1486866000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
system.membus.reqLayer1.occupancy                1000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             3686500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer4.occupancy                1500                       # Layer occupancy (ticks)
system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer6.occupancy         17361359500                       # Layer occupancy (ticks)
system.membus.reqLayer6.utilization               0.7                       # Layer utilization (%)
system.membus.respLayer1.occupancy         4731205438                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
system.membus.respLayer2.occupancy        33737720957                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              1.3                       # Layer utilization (%)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.iobus.throughput                      48266825                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq             16125556                       # Transaction distribution
system.iobus.trans_dist::ReadResp            16125556                       # Transaction distribution
system.iobus.trans_dist::WriteReq                8174                       # Transaction distribution
system.iobus.trans_dist::WriteResp               8174                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        30038                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         7936                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio          516                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio         1024                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          746                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio      2342380                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total      2383044                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     29884416                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total     29884416                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                32267460                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        39333                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        15872                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio         1032                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         2048                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio          397                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio      2331126                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total      2390454                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side    119537664                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total    119537664                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total            121928118                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus               121928118                       # Total data (bytes)
system.iobus.reqLayer0.occupancy             21111000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy              3973000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               516000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy               518000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                27000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy               445000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy           1172909000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer12.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy         14942208000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.6                       # Layer utilization (%)
system.iobus.respLayer0.occupancy          2374870000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.1                       # Layer utilization (%)
system.iobus.respLayer1.occupancy         40922322043                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               1.6                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.branchPred.lookups                14743416                       # Number of BP lookups
system.cpu.branchPred.condPredicted          11827380                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            704687                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups              9504018                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                 7655579                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             80.550973                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1397368                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect              72480                       # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                     51180405                       # DTB read hits
system.cpu.dtb.read_misses                      65067                       # DTB read misses
system.cpu.dtb.write_hits                    11700451                       # DTB write hits
system.cpu.dtb.write_misses                     15748                       # DTB write misses
system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                     3477                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                      2401                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                    399                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                      1377                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                 51245472                       # DTB read accesses
system.cpu.dtb.write_accesses                11716199                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                          62880856                       # DTB hits
system.cpu.dtb.misses                           80815                       # DTB misses
system.cpu.dtb.accesses                      62961671                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.inst_hits                     11521970                       # ITB inst hits
system.cpu.itb.inst_misses                      11115                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            2                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                     2502                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                      2960                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                 11533085                       # ITB inst accesses
system.cpu.itb.hits                          11521970                       # DTB hits
system.cpu.itb.misses                           11115                       # DTB misses
system.cpu.itb.accesses                      11533085                       # DTB accesses
system.cpu.numCycles                        477047952                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           29756603                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                       90277136                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    14743416                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches            9052947                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      20141800                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 4650225                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                     121200                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.BlockedCycles               98195863                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                 2631                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles         87675                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles      2688966                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles          386                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  11518528                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                709932                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                    5147                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          154198551                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              0.729959                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.081572                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                134072201     86.95%     86.95% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  1305405      0.85%     87.79% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  1710070      1.11%     88.90% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  2294026      1.49%     90.39% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  2104673      1.36%     91.76% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  1102818      0.72%     92.47% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  2555300      1.66%     94.13% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                   746086      0.48%     94.61% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                  8307972      5.39%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            154198551                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.030906                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.189241                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 31769851                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             100064901                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  18067338                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               1262749                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                3033712                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              1957542                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                172175                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              107250920                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                570386                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                3033712                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 33504513                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                38619180                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       55176666                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  17578446                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               6286034                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              102244327                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                   450                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                 980082                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               4063460                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents              782                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           106315700                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             473686161                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        432563323                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups             10440                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              78727135                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 27588564                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts            1170552                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts        1076872                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  12591466                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             19711121                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            13300191                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1936389                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          2436828                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                   95079446                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             1983827                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 122895781                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            165904                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        18895197                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     47144933                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         501515                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     154198551                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.796997                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.515893                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           109876529     71.26%     71.26% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            14361592      9.31%     80.57% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             6875815      4.46%     85.03% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             5666847      3.68%     88.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            12323021      7.99%     96.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             2802995      1.82%     98.51% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             1694666      1.10%     99.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              469725      0.30%     99.92% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              127361      0.08%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       154198551                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                   61834      0.70%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      3      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                8368136     94.62%     95.32% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                413820      4.68%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass             28518      0.02%      0.02% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              57946622     47.15%     47.17% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                93414      0.08%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                  24      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc              17      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc           2113      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc           19      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.25% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             52506141     42.72%     89.98% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            12318913     10.02%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              122895781                       # Type of FU issued
system.cpu.iq.rate                           0.257617                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     8843793                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.071962                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          409057037                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         115975062                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses     85458771                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads               23247                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes              12478                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses        10297                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              131698673                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                   12383                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads           624051                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      4056444                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         6518                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        30236                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1568197                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads     34108054                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked        680529                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                3033712                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                30168583                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                433803                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts            97285878                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            203457                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              19711121                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             13300191                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts            1411588                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 113159                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                  3352                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          30236                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         349021                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       270487                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               619508                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             120819447                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              51867420                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           2076334                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                        222605                       # number of nop insts executed
system.cpu.iew.exec_refs                     64079545                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 11817660                       # Number of branches executed
system.cpu.iew.exec_stores                   12212125                       # Number of stores executed
system.cpu.iew.exec_rate                     0.253265                       # Inst execution rate
system.cpu.iew.wb_sent                      119878750                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                      85469068                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  47006672                       # num instructions producing a value
system.cpu.iew.wb_consumers                  87538881                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       0.179162                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.536980                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts        18642428                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         1482312                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            534972                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    151164839                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.514346                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.491788                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    122735782     81.19%     81.19% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     14630083      9.68%     90.87% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      3890528      2.57%     93.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      2132680      1.41%     94.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1607271      1.06%     95.92% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5       973341      0.64%     96.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      1599818      1.06%     97.62% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       715537      0.47%     98.09% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      2879799      1.91%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    151164839                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             60459531                       # Number of instructions committed
system.cpu.commit.committedOps               77751027                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       27386671                       # Number of memory references committed
system.cpu.commit.loads                      15654677                       # Number of loads committed
system.cpu.commit.membars                      403573                       # Number of memory barriers committed
system.cpu.commit.branches                   10306328                       # Number of branches committed
system.cpu.commit.fp_insts                      10212                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  69191102                       # Number of committed integer instructions.
system.cpu.commit.function_calls               991248                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               2879799                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    242830080                       # The number of ROB reads
system.cpu.rob.rob_writes                   195907164                       # The number of ROB writes
system.cpu.timesIdled                         1776346                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                       322849401                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   4575122538                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                    60309150                       # Number of Instructions Simulated
system.cpu.committedOps                      77600646                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total              60309150                       # Number of Instructions Simulated
system.cpu.cpi                               7.910043                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         7.910043                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.126422                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.126422                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                548535745                       # number of integer regfile reads
system.cpu.int_regfile_writes                87515632                       # number of integer regfile writes
system.cpu.fp_regfile_reads                      8349                       # number of floating regfile reads
system.cpu.fp_regfile_writes                     2926                       # number of floating regfile writes
system.cpu.misc_regfile_reads               268179441                       # number of misc regfile reads
system.cpu.misc_regfile_writes                1173225                       # number of misc regfile writes
system.cpu.toL2Bus.throughput                58877700                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq        2658609                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       2658608                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq        763349                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp       763349                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       607534                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         2957                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq           12                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         2969                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       246101                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       246101                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1963183                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5795840                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        30059                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       127673                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           7916755                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     62784704                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     85494778                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        40536                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       211580                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total      148531598                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus         148531598                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus       200936                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy     3128807668                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    1475592252                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    2550083892                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy      19930988                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy      74876053                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu.icache.tags.replacements            981505                       # number of replacements
system.cpu.icache.tags.tagsinuse           511.575357                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            10456797                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs            982017                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             10.648285                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle        6907075250                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   511.575357                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.999171                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.999171                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          132                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          219                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          160                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          12500448                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         12500448                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     10456797                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        10456797                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      10456797                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         10456797                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     10456797                       # number of overall hits
system.cpu.icache.overall_hits::total        10456797                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1061602                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1061602                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1061602                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1061602                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1061602                       # number of overall misses
system.cpu.icache.overall_misses::total       1061602                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  14273209676                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  14273209676                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  14273209676                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  14273209676                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  14273209676                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  14273209676                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     11518399                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     11518399                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     11518399                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     11518399                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     11518399                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     11518399                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.092166                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.092166                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.092166                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.092166                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.092166                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.092166                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13444.972481                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13444.972481                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13444.972481                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13444.972481                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13444.972481                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13444.972481                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         6382                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               332                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    19.222892                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        79552                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        79552                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        79552                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        79552                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        79552                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        79552                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       982050                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       982050                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       982050                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       982050                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       982050                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       982050                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11590658741                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  11590658741                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11590658741                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  11590658741                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11590658741                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  11590658741                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst      8870000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total      8870000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst      8870000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total      8870000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.085259                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.085259                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.085259                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.085259                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.085259                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.085259                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11802.513865                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11802.513865                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11802.513865                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11802.513865                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11802.513865                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11802.513865                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements            64371                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        51367.805522                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            1886658                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           129763                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            14.539260                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle     2490785434500                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 36937.207333                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    28.555690                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.000373                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  8169.178837                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  6232.863288                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.563617                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000436                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.124652                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.095106                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.783811                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023           21                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        65371                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4           20                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          355                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3048                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6928                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55002                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000320                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.997482                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         18785683                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        18785683                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        52852                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        10132                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst       968531                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data       386919                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1418434                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       607534                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       607534                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           40                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           40                       # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            9                       # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total            9                       # number of SCUpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       112876                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       112876                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker        52852                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker        10132                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst       968531                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data       499795                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         1531310                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker        52852                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker        10132                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst       968531                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data       499795                       # number of overall hits
system.cpu.l2cache.overall_hits::total        1531310                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           43                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst        12359                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        10705                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        23109                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         2917                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         2917                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            3                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            3                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       133225                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       133225                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker           43                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            2                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        12359                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       143930                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        156334                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker           43                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            2                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        12359                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       143930                       # number of overall misses
system.cpu.l2cache.overall_misses::total       156334                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      3808750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       158000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    901494000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data    813359500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   1718820250                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       465980                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total       465980                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9840326977                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   9840326977                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      3808750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       158000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    901494000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  10653686477                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  11559147227                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      3808750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       158000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    901494000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  10653686477                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  11559147227                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        52895                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker        10134                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst       980890                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data       397624                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      1441543                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       607534                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       607534                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2957                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         2957                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data           12                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total           12                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       246101                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       246101                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker        52895                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker        10134                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst       980890                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       643725                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      1687644                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker        52895                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker        10134                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       980890                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       643725                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      1687644                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000813                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000197                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.012600                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.026922                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.016031                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.986473                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.986473                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.250000                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.250000                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.541343                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.541343                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000813                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000197                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.012600                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.223589                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.092634                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000813                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000197                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.012600                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.223589                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.092634                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 88575.581395                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        79000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72942.309248                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75979.402149                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 74378.824268                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   159.746315                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   159.746315                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73862.465581                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73862.465581                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 88575.581395                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        79000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72942.309248                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74019.915772                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 73938.792758                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 88575.581395                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        79000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72942.309248                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74019.915772                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 73938.792758                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        59118                       # number of writebacks
system.cpu.l2cache.writebacks::total            59118                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           13                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           67                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           80                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           13                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           67                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           80                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           13                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           67                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           80                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           43                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            2                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        12346                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        10638                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        23029                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2917                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         2917                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            3                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133225                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       133225                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           43                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            2                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        12346                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       143863                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       156254                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           43                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            2                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        12346                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       143863                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       156254                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      3278250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       133500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    745356250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    676470750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1425238750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     29172917                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     29172917                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        30003                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        30003                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8180809023                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8180809023                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      3278250                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       133500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    745356250                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8857279773                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   9606047773                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      3278250                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       133500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    745356250                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8857279773                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   9606047773                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst      6336999                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166942244250                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166948581249                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data  17449661616                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total  17449661616                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst      6336999                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184391905866                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184398242865                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000813                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000197                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.012587                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026754                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.015975                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.986473                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.986473                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.250000                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.250000                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.541343                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.541343                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000813                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000197                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.012587                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.223485                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.092587                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000813                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000197                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.012587                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.223485                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.092587                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76238.372093                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        66750                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60372.286571                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63590.031021                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61888.868383                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61405.960015                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61405.960015                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76238.372093                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        66750                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60372.286571                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61567.461912                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61477.131933                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76238.372093                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        66750                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60372.286571                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61567.461912                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61477.131933                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements            643213                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.993295                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            21506846                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            643725                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             33.409990                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle          42602250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.993295                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999987                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999987                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          196                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          299                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           17                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         101509393                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        101509393                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     13753990                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        13753990                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      7259407                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        7259407                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       242755                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       242755                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       247595                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       247595                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      21013397                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         21013397                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     21013397                       # number of overall hits
system.cpu.dcache.overall_hits::total        21013397                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       736321                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        736321                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      2962815                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      2962815                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        13522                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        13522                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data           12                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total           12                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data      3699136                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        3699136                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      3699136                       # number of overall misses
system.cpu.dcache.overall_misses::total       3699136                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  10001713308                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  10001713308                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 140180267525                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 140180267525                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    184727500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    184727500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       193503                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total       193503                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 150181980833                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 150181980833                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 150181980833                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 150181980833                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     14490311                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     14490311                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     10222222                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     10222222                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       256277                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       256277                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       247607                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       247607                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     24712533                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     24712533                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     24712533                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     24712533                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.050815                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.050815                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.289841                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.289841                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.052763                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.052763                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000048                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000048                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.149687                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.149687                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.149687                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.149687                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13583.360121                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13583.360121                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47313.202993                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 47313.202993                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13661.255731                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13661.255731                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16125.250000                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16125.250000                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 40599.205012                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 40599.205012                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 40599.205012                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 40599.205012                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs        30576                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets        27091                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs              2628                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets             288                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    11.634703                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    94.065972                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       607534                       # number of writebacks
system.cpu.dcache.writebacks::total            607534                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       350801                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       350801                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2713841                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      2713841                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         1334                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total         1334                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      3064642                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      3064642                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      3064642                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      3064642                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       385520                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       385520                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       248974                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       248974                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        12188                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total        12188                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           12                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total           12                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       634494                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       634494                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       634494                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       634494                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   4971012627                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   4971012627                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11323926285                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  11323926285                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    145258250                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    145258250                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       169497                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       169497                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  16294938912                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  16294938912                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  16294938912                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  16294938912                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182335926750                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182335926750                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  26847444003                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  26847444003                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209183370753                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 209183370753                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.026605                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.026605                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024356                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024356                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.047558                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.047558                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000048                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000048                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025675                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.025675                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025675                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.025675                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12894.305424                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12894.305424                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45482.364765                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45482.364765                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11918.136692                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11918.136692                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14124.750000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14124.750000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25681.785662                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 25681.785662                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25681.785662                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 25681.785662                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.iocache.tags.replacements                    0                       # number of replacements
system.iocache.tags.tagsinuse                       0                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
system.iocache.tags.tag_accesses                    0                       # Number of tag accesses
system.iocache.tags.data_accesses                   0                       # Number of data accesses
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1499139103043                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1499139103043                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1499139103043                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1499139103043                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                    83035                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------