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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt

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ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
---------- Begin Simulation Statistics ----------
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
sim_seconds 2.526147 # Number of seconds simulated
sim_ticks 2526146947500 # Number of ticks simulated
final_tick 2526146947500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
host_inst_rate 69975 # Simulator instruction rate (inst/s)
host_op_rate 90038 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2931166527 # Simulator tick rate (ticks/s)
host_mem_usage 424336 # Number of bytes of host memory used
host_seconds 861.82 # Real time elapsed on the host
sim_insts 60306154 # Number of instructions simulated
sim_ops 77597242 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.physmem.bytes_read::cpu.dtb.walker 3328 # Number of bytes read from this memory
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.physmem.bytes_read::cpu.inst 796736 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9093720 # Number of bytes read from this memory
system.physmem.bytes_read::total 129431576 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 796736 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 796736 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3782528 # Number of bytes written to this memory
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.physmem.bytes_written::total 6798600 # Number of bytes written to this memory
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.physmem.num_reads::cpu.dtb.walker 52 # Number of read requests responded to by this memory
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.physmem.num_reads::cpu.inst 12449 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 142125 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15096836 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 59102 # Number of write requests responded to by this memory
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.physmem.num_writes::total 813120 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 47320155 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 1317 # Total read bandwidth from this memory (bytes/s)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.physmem.bw_read::cpu.inst 315396 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3599838 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 51236756 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 315396 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 315396 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1497351 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1193942 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2691292 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1497351 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 47320155 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 1317 # Total bandwidth to/from this memory (bytes/s)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.physmem.bw_total::cpu.inst 315396 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4793780 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 53928049 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 15096836 # Number of read requests accepted
system.physmem.writeReqs 813120 # Number of write requests accepted
system.physmem.readBursts 15096836 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 813120 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 963731584 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 2465920 # Total number of bytes read from write queue
system.physmem.bytesWritten 6899264 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 129431576 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 6798600 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 38530 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 705302 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 4683 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 943582 # Per bank write bursts
system.physmem.perBankRdBursts::1 943071 # Per bank write bursts
system.physmem.perBankRdBursts::2 939289 # Per bank write bursts
system.physmem.perBankRdBursts::3 939279 # Per bank write bursts
system.physmem.perBankRdBursts::4 943119 # Per bank write bursts
system.physmem.perBankRdBursts::5 943242 # Per bank write bursts
system.physmem.perBankRdBursts::6 939090 # Per bank write bursts
system.physmem.perBankRdBursts::7 938633 # Per bank write bursts
system.physmem.perBankRdBursts::8 943981 # Per bank write bursts
system.physmem.perBankRdBursts::9 943506 # Per bank write bursts
system.physmem.perBankRdBursts::10 938534 # Per bank write bursts
system.physmem.perBankRdBursts::11 937721 # Per bank write bursts
system.physmem.perBankRdBursts::12 943933 # Per bank write bursts
system.physmem.perBankRdBursts::13 943406 # Per bank write bursts
system.physmem.perBankRdBursts::14 939034 # Per bank write bursts
system.physmem.perBankRdBursts::15 938886 # Per bank write bursts
system.physmem.perBankWrBursts::0 6687 # Per bank write bursts
system.physmem.perBankWrBursts::1 6452 # Per bank write bursts
system.physmem.perBankWrBursts::2 6617 # Per bank write bursts
system.physmem.perBankWrBursts::3 6618 # Per bank write bursts
system.physmem.perBankWrBursts::4 6551 # Per bank write bursts
system.physmem.perBankWrBursts::5 6799 # Per bank write bursts
system.physmem.perBankWrBursts::6 6798 # Per bank write bursts
system.physmem.perBankWrBursts::7 6724 # Per bank write bursts
system.physmem.perBankWrBursts::8 7121 # Per bank write bursts
system.physmem.perBankWrBursts::9 6870 # Per bank write bursts
system.physmem.perBankWrBursts::10 6536 # Per bank write bursts
system.physmem.perBankWrBursts::11 6184 # Per bank write bursts
system.physmem.perBankWrBursts::12 7152 # Per bank write bursts
system.physmem.perBankWrBursts::13 6752 # Per bank write bursts
system.physmem.perBankWrBursts::14 7039 # Per bank write bursts
system.physmem.perBankWrBursts::15 6901 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.physmem.totGap 2526145872500 # Total gap between requests
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.physmem.readPktSize::2 38 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::3 14942208 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.physmem.readPktSize::6 154590 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 754018 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.physmem.writePktSize::6 59102 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 1174955 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 1121426 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 1077218 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 3628637 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2607777 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2593781 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 2599800 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 53131 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 57465 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 21079 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 20890 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 20765 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 20515 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 20363 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 20256 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 20150 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.wrQLenPdf::0 4766 # What write queue length does an incoming req see
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.physmem.wrQLenPdf::1 5448 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 4902 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 5096 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 5215 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 4875 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 4866 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 4857 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 4818 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 4828 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 4808 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 4790 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 4794 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 4788 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 4798 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 4790 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 4786 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 4809 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 4833 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 4807 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 4795 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 5137 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 126 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 70 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 16 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.physmem.bytesPerActivate::samples 86110 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 11271.974916 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 1003.850407 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 16772.129499 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-71 23407 27.18% 27.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-135 14160 16.44% 43.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-199 2694 3.13% 46.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-263 2155 2.50% 49.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-327 1262 1.47% 50.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-391 1178 1.37% 52.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-455 892 1.04% 53.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-519 1078 1.25% 54.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-583 591 0.69% 55.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-647 609 0.71% 55.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-711 535 0.62% 56.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-775 547 0.64% 57.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-839 279 0.32% 57.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-903 297 0.34% 57.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-967 152 0.18% 57.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1031 456 0.53% 58.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1095 120 0.14% 58.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1159 137 0.16% 58.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1223 61 0.07% 58.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1287 169 0.20% 58.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1351 52 0.06% 59.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1415 508 0.59% 59.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1479 23 0.03% 59.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1543 260 0.30% 59.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1607 13 0.02% 59.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1671 93 0.11% 60.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1735 18 0.02% 60.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1799 141 0.16% 60.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1863 16 0.02% 60.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1927 46 0.05% 60.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1991 16 0.02% 60.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2055 376 0.44% 60.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2119 11 0.01% 60.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2183 34 0.04% 60.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2247 13 0.02% 60.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2311 70 0.08% 60.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2375 7 0.01% 60.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2439 29 0.03% 60.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2503 6 0.01% 60.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2567 165 0.19% 61.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2631 6 0.01% 61.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2695 16 0.02% 61.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2759 8 0.01% 61.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2823 175 0.20% 61.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2887 13 0.02% 61.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2951 17 0.02% 61.45% # Bytes accessed per row activation
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.bytesPerActivate::3008-3015 4 0.00% 61.45% # Bytes accessed per row activation
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.physmem.bytesPerActivate::3072-3079 306 0.36% 61.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3143 11 0.01% 61.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3207 15 0.02% 61.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3271 9 0.01% 61.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3335 94 0.11% 61.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3399 11 0.01% 61.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3463 22 0.03% 61.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3527 5 0.01% 62.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3591 99 0.11% 62.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3655 9 0.01% 62.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3719 12 0.01% 62.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3783 8 0.01% 62.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3847 93 0.11% 62.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3911 7 0.01% 62.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3975 21 0.02% 62.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4039 5 0.01% 62.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4103 365 0.42% 62.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4167 6 0.01% 62.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4231 12 0.01% 62.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4295 7 0.01% 62.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4359 91 0.11% 62.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4423 13 0.02% 62.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4487 7 0.01% 62.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4551 5 0.01% 62.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4615 21 0.02% 62.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4679 3 0.00% 62.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4743 11 0.01% 62.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4807 9 0.01% 62.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4871 161 0.19% 63.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4935 5 0.01% 63.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4999 16 0.02% 63.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5063 7 0.01% 63.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5127 409 0.47% 63.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5191 11 0.01% 63.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5255 9 0.01% 63.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5319 13 0.02% 63.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5383 56 0.07% 63.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5447 5 0.01% 63.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5511 15 0.02% 63.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568-5575 8 0.01% 63.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5639 79 0.09% 63.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5703 2 0.00% 63.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760-5767 10 0.01% 63.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5824-5831 9 0.01% 63.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5895 142 0.16% 64.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952-5959 3 0.00% 64.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6023 18 0.02% 64.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6087 9 0.01% 64.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6151 348 0.40% 64.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6215 6 0.01% 64.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6279 7 0.01% 64.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6336-6343 3 0.00% 64.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6407 23 0.03% 64.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6471 1 0.00% 64.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6535 7 0.01% 64.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6599 4 0.00% 64.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6663 95 0.11% 64.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6791 17 0.02% 64.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6855 3 0.00% 64.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6919 100 0.12% 64.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7047 11 0.01% 64.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7104-7111 7 0.01% 64.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7175 484 0.56% 65.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7232-7239 2 0.00% 65.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7296-7303 7 0.01% 65.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7360-7367 12 0.01% 65.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7431 86 0.10% 65.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7488-7495 3 0.00% 65.50% # Bytes accessed per row activation
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.bytesPerActivate::7552-7559 9 0.01% 65.51% # Bytes accessed per row activation
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.physmem.bytesPerActivate::7616-7623 2 0.00% 65.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7687 27 0.03% 65.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7815 10 0.01% 65.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7872-7879 1 0.00% 65.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7943 155 0.18% 65.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8007 1 0.00% 65.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8071 8 0.01% 65.75% # Bytes accessed per row activation
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.bytesPerActivate::8128-8135 1 0.00% 65.75% # Bytes accessed per row activation
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.physmem.bytesPerActivate::8192-8199 378 0.44% 66.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8256-8263 1 0.00% 66.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8448-8455 152 0.18% 66.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8704-8711 21 0.02% 66.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8832-8839 2 0.00% 66.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8960-8967 72 0.08% 66.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9024-9031 2 0.00% 66.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9088-9095 5 0.01% 66.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9152-9159 1 0.00% 66.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9216-9223 466 0.54% 67.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9344-9351 1 0.00% 67.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9472-9479 96 0.11% 67.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9536-9543 1 0.00% 67.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9728-9735 85 0.10% 67.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9920-9927 1 0.00% 67.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9984-9991 17 0.02% 67.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10112-10119 2 0.00% 67.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10240-10247 345 0.40% 67.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10304-10311 1 0.00% 67.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10368-10375 1 0.00% 67.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10432-10439 1 0.00% 67.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10496-10503 83 0.10% 67.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10752-10759 68 0.08% 67.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10944-10951 1 0.00% 67.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11008-11015 39 0.05% 67.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11136-11143 4 0.00% 67.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11264-11271 396 0.46% 68.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11328-11335 2 0.00% 68.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11456-11463 1 0.00% 68.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11520-11527 156 0.18% 68.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11584-11591 2 0.00% 68.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11776-11783 8 0.01% 68.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11968-11975 1 0.00% 68.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12032-12039 83 0.10% 68.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12160-12167 2 0.00% 68.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12224-12231 1 0.00% 68.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12288-12295 336 0.39% 69.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12352-12359 1 0.00% 69.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12416-12423 1 0.00% 69.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12480-12487 1 0.00% 69.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12544-12551 83 0.10% 69.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12672-12679 2 0.00% 69.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12736-12743 1 0.00% 69.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12800-12807 81 0.09% 69.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12864-12871 1 0.00% 69.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12928-12935 2 0.00% 69.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13056-13063 70 0.08% 69.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13184-13191 3 0.00% 69.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13248-13255 1 0.00% 69.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13312-13319 277 0.32% 69.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13376-13383 1 0.00% 69.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13440-13447 3 0.00% 69.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13568-13575 151 0.18% 69.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13696-13703 1 0.00% 69.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13824-13831 132 0.15% 69.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14080-14087 32 0.04% 70.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14208-14215 2 0.00% 70.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14336-14343 338 0.39% 70.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14464-14471 1 0.00% 70.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14528-14535 1 0.00% 70.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14592-14599 77 0.09% 70.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14720-14727 2 0.00% 70.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14784-14791 1 0.00% 70.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14848-14855 81 0.09% 70.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14912-14919 1 0.00% 70.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15104-15111 72 0.08% 70.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15232-15239 2 0.00% 70.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15360-15367 269 0.31% 71.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15424-15431 2 0.00% 71.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15488-15495 1 0.00% 71.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15616-15623 83 0.10% 71.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15680-15687 1 0.00% 71.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15744-15751 3 0.00% 71.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15808-15815 1 0.00% 71.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15872-15879 157 0.18% 71.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16000-16007 3 0.00% 71.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16128-16135 129 0.15% 71.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16192-16199 1 0.00% 71.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16256-16263 7 0.01% 71.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16320-16327 2 0.00% 71.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16384-16391 524 0.61% 72.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16512-16519 3 0.00% 72.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16640-16647 130 0.15% 72.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16768-16775 2 0.00% 72.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16832-16839 3 0.00% 72.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16896-16903 155 0.18% 72.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16960-16967 3 0.00% 72.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17024-17031 1 0.00% 72.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17152-17159 86 0.10% 72.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17216-17223 1 0.00% 72.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17280-17287 1 0.00% 72.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17344-17351 1 0.00% 72.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17408-17415 268 0.31% 72.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17472-17479 3 0.00% 72.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17536-17543 1 0.00% 72.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17664-17671 70 0.08% 72.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17920-17927 80 0.09% 73.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17984-17991 2 0.00% 73.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18048-18055 2 0.00% 73.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18176-18183 82 0.10% 73.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18240-18247 1 0.00% 73.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18304-18311 2 0.00% 73.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18432-18439 328 0.38% 73.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18560-18567 1 0.00% 73.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18624-18631 1 0.00% 73.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18688-18695 35 0.04% 73.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18816-18823 1 0.00% 73.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18944-18951 133 0.15% 73.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19008-19015 1 0.00% 73.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19072-19079 2 0.00% 73.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19200-19207 154 0.18% 73.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19328-19335 3 0.00% 73.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19392-19399 1 0.00% 73.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19456-19463 281 0.33% 74.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19712-19719 67 0.08% 74.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19840-19847 1 0.00% 74.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19968-19975 79 0.09% 74.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20032-20039 1 0.00% 74.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20160-20167 1 0.00% 74.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20224-20231 87 0.10% 74.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20352-20359 4 0.00% 74.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20416-20423 1 0.00% 74.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20480-20487 327 0.38% 74.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20608-20615 1 0.00% 74.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20736-20743 77 0.09% 74.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20992-20999 10 0.01% 74.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21056-21063 1 0.00% 74.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21120-21127 1 0.00% 74.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21184-21191 2 0.00% 74.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21248-21255 151 0.18% 75.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21376-21383 4 0.00% 75.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21440-21447 1 0.00% 75.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21504-21511 401 0.47% 75.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21568-21575 1 0.00% 75.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21632-21639 1 0.00% 75.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21760-21767 39 0.05% 75.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21824-21831 2 0.00% 75.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21888-21895 1 0.00% 75.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22016-22023 65 0.08% 75.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22144-22151 2 0.00% 75.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22272-22279 85 0.10% 75.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22336-22343 2 0.00% 75.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22400-22407 4 0.00% 75.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22464-22471 1 0.00% 75.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22528-22535 336 0.39% 76.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22592-22599 1 0.00% 76.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22656-22663 1 0.00% 76.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22784-22791 18 0.02% 76.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22912-22919 3 0.00% 76.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23040-23047 81 0.09% 76.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23104-23111 2 0.00% 76.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23168-23175 1 0.00% 76.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23232-23239 2 0.00% 76.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23296-23303 92 0.11% 76.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23360-23367 1 0.00% 76.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23424-23431 4 0.00% 76.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23488-23495 1 0.00% 76.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23552-23559 463 0.54% 77.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23680-23687 1 0.00% 77.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23808-23815 70 0.08% 77.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23936-23943 1 0.00% 77.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24000-24007 1 0.00% 77.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24064-24071 19 0.02% 77.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24192-24199 1 0.00% 77.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24320-24327 148 0.17% 77.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24384-24391 1 0.00% 77.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24448-24455 5 0.01% 77.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24576-24583 262 0.30% 77.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24640-24647 1 0.00% 77.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24704-24711 3 0.00% 77.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24768-24775 2 0.00% 77.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24832-24839 150 0.17% 77.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24896-24903 1 0.00% 77.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24960-24967 2 0.00% 77.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25088-25095 20 0.02% 77.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25152-25159 1 0.00% 77.82% # Bytes accessed per row activation
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.bytesPerActivate::25216-25223 2 0.00% 77.82% # Bytes accessed per row activation
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.physmem.bytesPerActivate::25344-25351 73 0.08% 77.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25472-25479 2 0.00% 77.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25600-25607 464 0.54% 78.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25728-25735 1 0.00% 78.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25792-25799 1 0.00% 78.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25856-25863 93 0.11% 78.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25984-25991 3 0.00% 78.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26048-26055 1 0.00% 78.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26112-26119 84 0.10% 78.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26176-26183 1 0.00% 78.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26240-26247 1 0.00% 78.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26304-26311 1 0.00% 78.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26368-26375 18 0.02% 78.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26432-26439 1 0.00% 78.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26496-26503 5 0.01% 78.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26624-26631 339 0.39% 79.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26880-26887 80 0.09% 79.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27008-27015 3 0.00% 79.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27136-27143 63 0.07% 79.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27200-27207 2 0.00% 79.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27392-27399 47 0.05% 79.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27520-27527 2 0.00% 79.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27584-27591 2 0.00% 79.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27648-27655 394 0.46% 79.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27776-27783 2 0.00% 79.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27840-27847 1 0.00% 79.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27904-27911 150 0.17% 79.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28032-28039 1 0.00% 79.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28096-28103 1 0.00% 79.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28160-28167 8 0.01% 79.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28288-28295 2 0.00% 79.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28352-28359 1 0.00% 79.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28416-28423 82 0.10% 80.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28480-28487 1 0.00% 80.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28544-28551 5 0.01% 80.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28608-28615 1 0.00% 80.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28672-28679 329 0.38% 80.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28736-28743 2 0.00% 80.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28800-28807 3 0.00% 80.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28928-28935 83 0.10% 80.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28992-28999 1 0.00% 80.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29120-29127 2 0.00% 80.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29184-29191 82 0.10% 80.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29248-29255 1 0.00% 80.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29312-29319 2 0.00% 80.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29440-29447 72 0.08% 80.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29504-29511 2 0.00% 80.74% # Bytes accessed per row activation
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.bytesPerActivate::29632-29639 1 0.00% 80.74% # Bytes accessed per row activation
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.physmem.bytesPerActivate::29696-29703 276 0.32% 81.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29824-29831 3 0.00% 81.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29888-29895 1 0.00% 81.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29952-29959 155 0.18% 81.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30016-30023 1 0.00% 81.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30080-30087 2 0.00% 81.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30144-30151 1 0.00% 81.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30208-30215 130 0.15% 81.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30272-30279 1 0.00% 81.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30464-30471 35 0.04% 81.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30592-30599 7 0.01% 81.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30656-30663 2 0.00% 81.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30720-30727 330 0.38% 81.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30784-30791 2 0.00% 81.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30848-30855 1 0.00% 81.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30976-30983 79 0.09% 81.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31040-31047 1 0.00% 81.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31104-31111 2 0.00% 81.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31232-31239 75 0.09% 82.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31296-31303 1 0.00% 82.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31360-31367 1 0.00% 82.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31488-31495 72 0.08% 82.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31552-31559 2 0.00% 82.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31616-31623 3 0.00% 82.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31680-31687 1 0.00% 82.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31744-31751 264 0.31% 82.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31872-31879 1 0.00% 82.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32000-32007 85 0.10% 82.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32064-32071 2 0.00% 82.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32128-32135 1 0.00% 82.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32256-32263 158 0.18% 82.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32320-32327 1 0.00% 82.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32384-32391 1 0.00% 82.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32448-32455 1 0.00% 82.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32512-32519 132 0.15% 82.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32576-32583 2 0.00% 82.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32640-32647 1 0.00% 82.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32768-32775 526 0.61% 83.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32896-32903 2 0.00% 83.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33024-33031 130 0.15% 83.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33216-33223 1 0.00% 83.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33280-33287 160 0.19% 83.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33408-33415 2 0.00% 83.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33472-33479 1 0.00% 83.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33536-33543 90 0.10% 83.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33600-33607 4 0.00% 83.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33792-33799 276 0.32% 84.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33856-33863 1 0.00% 84.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33920-33927 2 0.00% 84.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34048-34055 69 0.08% 84.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34112-34119 1 0.00% 84.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34304-34311 76 0.09% 84.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34432-34439 3 0.00% 84.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34560-34567 78 0.09% 84.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34688-34695 1 0.00% 84.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34752-34759 1 0.00% 84.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34816-34823 329 0.38% 84.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34944-34951 1 0.00% 84.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35072-35079 37 0.04% 84.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35200-35207 1 0.00% 84.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35328-35335 132 0.15% 85.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35456-35463 1 0.00% 85.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35584-35591 157 0.18% 85.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35712-35719 3 0.00% 85.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35840-35847 272 0.32% 85.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36032-36039 1 0.00% 85.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36096-36103 68 0.08% 85.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36224-36231 2 0.00% 85.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36352-36359 82 0.10% 85.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36480-36487 3 0.00% 85.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36608-36615 85 0.10% 85.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36800-36807 2 0.00% 85.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36864-36871 328 0.38% 86.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37120-37127 78 0.09% 86.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37184-37191 2 0.00% 86.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37248-37255 1 0.00% 86.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37312-37319 1 0.00% 86.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37376-37383 7 0.01% 86.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37504-37511 1 0.00% 86.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37632-37639 154 0.18% 86.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37888-37895 389 0.45% 87.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38016-38023 2 0.00% 87.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38144-38151 41 0.05% 87.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38272-38279 2 0.00% 87.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38336-38343 1 0.00% 87.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38400-38407 63 0.07% 87.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38528-38535 4 0.00% 87.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38656-38663 83 0.10% 87.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38912-38919 332 0.39% 87.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39040-39047 1 0.00% 87.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39168-39175 17 0.02% 87.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39424-39431 81 0.09% 87.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39552-39559 2 0.00% 87.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39680-39687 95 0.11% 87.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39936-39943 463 0.54% 88.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40192-40199 69 0.08% 88.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40320-40327 4 0.00% 88.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40384-40391 1 0.00% 88.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40448-40455 15 0.02% 88.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40576-40583 4 0.00% 88.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40640-40647 1 0.00% 88.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40704-40711 149 0.17% 88.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40960-40967 257 0.30% 88.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41152-41159 1 0.00% 88.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41216-41223 145 0.17% 89.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41344-41351 1 0.00% 89.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41408-41415 1 0.00% 89.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41472-41479 16 0.02% 89.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41536-41543 1 0.00% 89.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41600-41607 2 0.00% 89.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41728-41735 72 0.08% 89.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41984-41991 458 0.53% 89.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42176-42183 1 0.00% 89.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42240-42247 90 0.10% 89.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42304-42311 2 0.00% 89.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42432-42439 1 0.00% 89.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42496-42503 82 0.10% 89.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42624-42631 4 0.00% 89.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42688-42695 1 0.00% 89.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42752-42759 17 0.02% 90.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42816-42823 1 0.00% 90.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42880-42887 2 0.00% 90.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43008-43015 331 0.38% 90.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43200-43207 1 0.00% 90.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43264-43271 81 0.09% 90.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43328-43335 1 0.00% 90.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43520-43527 64 0.07% 90.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43648-43655 4 0.00% 90.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43712-43719 1 0.00% 90.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43776-43783 37 0.04% 90.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43840-43847 1 0.00% 90.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44032-44039 395 0.46% 91.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44096-44103 1 0.00% 91.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44288-44295 150 0.17% 91.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44352-44359 2 0.00% 91.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44544-44551 10 0.01% 91.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44608-44615 2 0.00% 91.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44672-44679 4 0.00% 91.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44800-44807 81 0.09% 91.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44864-44871 2 0.00% 91.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45056-45063 328 0.38% 91.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45312-45319 82 0.10% 91.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45376-45383 2 0.00% 91.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45440-45447 2 0.00% 91.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45568-45575 83 0.10% 91.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45696-45703 3 0.00% 91.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45824-45831 69 0.08% 92.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45952-45959 1 0.00% 92.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46080-46087 277 0.32% 92.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46208-46215 3 0.00% 92.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46336-46343 151 0.18% 92.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46592-46599 129 0.15% 92.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46656-46663 1 0.00% 92.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46720-46727 2 0.00% 92.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46784-46791 1 0.00% 92.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46848-46855 36 0.04% 92.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46912-46919 1 0.00% 92.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46976-46983 2 0.00% 92.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47104-47111 330 0.38% 93.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47168-47175 1 0.00% 93.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47296-47303 1 0.00% 93.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47360-47367 81 0.09% 93.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47488-47495 1 0.00% 93.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47552-47559 1 0.00% 93.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47616-47623 82 0.10% 93.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47744-47751 1 0.00% 93.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47808-47815 2 0.00% 93.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47872-47879 74 0.09% 93.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47936-47943 1 0.00% 93.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48128-48135 266 0.31% 93.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48256-48263 1 0.00% 93.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48384-48391 83 0.10% 93.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48512-48519 1 0.00% 93.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48640-48647 154 0.18% 93.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48704-48711 2 0.00% 93.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48768-48775 62 0.07% 94.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48896-48903 129 0.15% 94.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48960-48967 2 0.00% 94.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49024-49031 2 0.00% 94.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49088-49095 4 0.00% 94.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49152-49159 4946 5.74% 99.96% # Bytes accessed per row activation
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.bytesPerActivate::49216-49223 1 0.00% 99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49600-49607 1 0.00% 99.96% # Bytes accessed per row activation
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.physmem.bytesPerActivate::49664-49671 1 0.00% 99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49920-49927 2 0.00% 99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50048-50055 1 0.00% 99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50176-50183 1 0.00% 99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50432-50439 4 0.00% 99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50496-50503 2 0.00% 99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50560-50567 1 0.00% 99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50624-50631 2 0.00% 99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50688-50695 1 0.00% 99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50816-50823 1 0.00% 99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50880-50887 1 0.00% 99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51136-51143 1 0.00% 99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51200-51207 2 0.00% 99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51264-51271 1 0.00% 99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51456-51463 2 0.00% 99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51584-51591 1 0.00% 99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51712-51719 2 0.00% 99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51904-51911 1 0.00% 100.00% # Bytes accessed per row activation
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.bytesPerActivate::51968-51975 2 0.00% 100.00% # Bytes accessed per row activation
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.physmem.bytesPerActivate::52160-52167 1 0.00% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::52288-52295 1 0.00% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 86110 # Bytes accessed per row activation
system.physmem.totQLat 365142496500 # Total ticks spent queuing
system.physmem.totMemAccLat 457904364000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 75291530000 # Total ticks spent in databus transfers
system.physmem.totBankLat 17470337500 # Total ticks spent accessing banks
system.physmem.avgQLat 24248.58 # Average queueing delay per DRAM burst
system.physmem.avgBankLat 1160.18 # Average bank access latency per DRAM burst
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.physmem.avgMemAccLat 30408.76 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 381.50 # Average DRAM read bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBW 2.73 # Average achieved write bandwidth in MiByte/s
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.physmem.avgRdBWSys 51.24 # Average system read bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBWSys 2.69 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 3.00 # Data bus utilization in percentage
system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.physmem.avgWrQLen 13.37 # Average write queue length when enqueuing
system.physmem.readRowHits 14986658 # Number of row buffer hits during reads
system.physmem.writeRowHits 93339 # Number of row buffer hits during writes
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.physmem.writeRowHitRate 86.57 # Row buffer hit rate for writes
system.physmem.avgGap 158777.68 # Average gap between requests
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.physmem.prechargeAllPercent 2.54 # Percentage of time for which DRAM has all the banks in precharge state
test: update stats Update stats for recent changes. Mostly minor changes in register access stats due to addition of new cc register type and slightly different (and more accurate) classification of int vs. fp register accesses.
2013-10-16 16:44:12 +02:00
system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.membus.throughput 54877277 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 16149448 # Transaction distribution
system.membus.trans_dist::ReadResp 16149448 # Transaction distribution
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.membus.trans_dist::WriteReq 763332 # Transaction distribution
system.membus.trans_dist::WriteResp 763332 # Transaction distribution
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.membus.trans_dist::Writeback 59102 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4681 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
system.membus.trans_dist::UpgradeResp 4683 # Transaction distribution
system.membus.trans_dist::ReadExReq 131427 # Transaction distribution
system.membus.trans_dist::ReadExResp 131427 # Transaction distribution
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382942 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885760 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272466 # Packet count per connected master and slave (bytes)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.membus.pkt_count::total 34156882 # Packet count per connected master and slave (bytes)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390301 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16692512 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19090401 # Cumulative packet size per connected master and slave (bytes)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.membus.tot_pkt_size::total 138628065 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 138628065 # Total data (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.membus.reqLayer0.occupancy 1486850000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.membus.reqLayer2.occupancy 3609000 # Layer occupancy (ticks)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks)
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.membus.reqLayer6.occupancy 17361408000 # Layer occupancy (ticks)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.membus.respLayer1.occupancy 4731178629 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.membus.respLayer2.occupancy 33737119450 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.respLayer2.utilization 1.3 # Layer utilization (%)
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.iobus.throughput 48266379 # Throughput (bytes/s)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.iobus.trans_dist::ReadReq 16125522 # Transaction distribution
system.iobus.trans_dist::ReadResp 16125522 # Transaction distribution
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iobus.trans_dist::WriteReq 8157 # Transaction distribution
system.iobus.trans_dist::WriteResp 8157 # Transaction distribution
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 516 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1024 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.iobus.pkt_count_system.bridge.master::total 2382942 # Packet count per connected master and slave (bytes)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29884416 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total 29884416 # Packet count per connected master and slave (bytes)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.iobus.pkt_count::total 32267358 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1032 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2048 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.iobus.tot_pkt_size_system.bridge.master::total 2390301 # Cumulative packet size per connected master and slave (bytes)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119537664 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119537664 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.iobus.tot_pkt_size::total 121927965 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 121927965 # Total data (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.iobus.reqLayer1.occupancy 3973000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iobus.reqLayer2.occupancy 516000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iobus.reqLayer3.occupancy 518000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iobus.reqLayer25.occupancy 14942208000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.iobus.respLayer0.occupancy 2374785000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.iobus.respLayer1.occupancy 40921538550 # Layer occupancy (ticks)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.iobus.respLayer1.utilization 1.6 # Layer utilization (%)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.branchPred.lookups 14756776 # Number of BP lookups
system.cpu.branchPred.condPredicted 11839520 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 705876 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 9493937 # Number of BTB lookups
system.cpu.branchPred.BTBHits 7667614 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.branchPred.BTBHitPct 80.763270 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1398139 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 72469 # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.dtb.read_hits 51181584 # DTB read hits
system.cpu.dtb.read_misses 65031 # DTB read misses
system.cpu.dtb.write_hits 11699885 # DTB write hits
system.cpu.dtb.write_misses 15694 # DTB write misses
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.dtb.flush_entries 3476 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 2524 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 396 # Number of TLB faults due to prefetch
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.dtb.perms_faults 1369 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 51246615 # DTB read accesses
system.cpu.dtb.write_accesses 11715579 # DTB write accesses
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.dtb.hits 62881469 # DTB hits
system.cpu.dtb.misses 80725 # DTB misses
system.cpu.dtb.accesses 62962194 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 11524718 # ITB inst hits
system.cpu.itb.inst_misses 11477 # ITB inst misses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.itb.flush_entries 2510 # Number of entries that have been flushed from TLB
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.itb.perms_faults 2880 # Number of TLB faults due to permissions restrictions
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.itb.inst_accesses 11536195 # ITB inst accesses
system.cpu.itb.hits 11524718 # DTB hits
system.cpu.itb.misses 11477 # DTB misses
system.cpu.itb.accesses 11536195 # DTB accesses
system.cpu.numCycles 477111575 # number of cpu cycles simulated
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.fetch.icacheStallCycles 29753545 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 90325732 # Number of instructions fetch has processed
system.cpu.fetch.Branches 14756776 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 9065753 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 20157040 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 4656007 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 125616 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.BlockedCycles 98208682 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 2521 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 87096 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 2698608 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles 449 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 11521342 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 709389 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes 5491 # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples 154241572 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.730167 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.081671 # Number of instructions fetched each cycle (Total)
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.fetch.rateDist::0 134100120 86.94% 86.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 1306005 0.85% 87.79% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 1712076 1.11% 88.90% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 2296227 1.49% 90.39% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 2110153 1.37% 91.76% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 1105630 0.72% 92.47% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 2555237 1.66% 94.13% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 745864 0.48% 94.61% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 8310260 5.39% 100.00% # Number of instructions fetched each cycle (Total)
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.fetch.rateDist::total 154241572 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.030929 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.189318 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 31783151 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 100076545 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 18079225 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 1264474 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 3038177 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 1958594 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 172374 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 107306930 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 570435 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 3038177 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 33521222 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 38625715 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 55163536 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 17589404 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 6303518 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 102301164 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 457 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 997569 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 4061695 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 772 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 106380900 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 473930729 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 432790417 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 10427 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 78723244 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 27657655 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 1170957 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 1077143 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 12622955 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 19717794 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 13303938 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1949827 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 2475969 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 95121483 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 1987498 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 122914150 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 166701 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 18940781 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 47245549 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 505193 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 154241572 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.796894 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.515720 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.iq.issued_per_cycle::0 109895599 71.25% 71.25% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 14389173 9.33% 80.58% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 6873802 4.46% 85.03% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 5671511 3.68% 88.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 12312296 7.98% 96.69% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 2806335 1.82% 98.51% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 1696199 1.10% 99.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 468469 0.30% 99.92% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 128188 0.08% 100.00% # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.iq.issued_per_cycle::total 154241572 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.iq.fu_full::IntAlu 62148 0.70% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 4 0.00% 0.70% # attempts to use FU when none available
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.iq.fu_full::MemRead 8367826 94.63% 95.33% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 412812 4.67% 100.00% # attempts to use FU when none available
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.iq.FU_type_0::No_OpClass 28518 0.02% 0.02% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 57963749 47.16% 47.18% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 93288 0.08% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 18 0.00% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 19 0.00% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.26% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 52506877 42.72% 89.98% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 12319545 10.02% 100.00% # Type of FU issued
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.iq.FU_type_0::total 122914150 # Type of FU issued
system.cpu.iq.rate 0.257621 # Inst issue rate
system.cpu.iq.fu_busy_cnt 8842790 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.071943 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 409136453 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 116066186 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 85476047 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 23300 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 12528 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 10301 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 131716001 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 12421 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 624558 # Number of loads that had data forwarded from stores
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.iew.lsq.thread0.squashedLoads 4063711 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 6653 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 30079 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 1572166 # Number of stores squashed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.iew.lsq.thread0.rescheduledLoads 34107729 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 680356 # Number of times an access to memory failed due to the cache being blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.iew.iewSquashCycles 3038177 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 30160267 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 434164 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 97330281 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 206491 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 19717794 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 13303938 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 1415153 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 113233 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 3362 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 30079 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 350155 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 270547 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 620702 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 120836027 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 51869099 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 2078123 # Number of squashed instructions skipped in execute
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.iew.exec_nop 221300 # number of nop insts executed
system.cpu.iew.exec_refs 64080526 # number of memory reference insts executed
system.cpu.iew.exec_branches 11821026 # Number of branches executed
system.cpu.iew.exec_stores 12211427 # Number of stores executed
system.cpu.iew.exec_rate 0.253266 # Inst execution rate
system.cpu.iew.wb_sent 119895169 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 85486348 # cumulative count of insts written-back
system.cpu.iew.wb_producers 47016858 # num instructions producing a value
system.cpu.iew.wb_consumers 87565512 # num instructions consuming a value
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.iew.wb_rate 0.179175 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.536934 # average fanout of values written-back
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.commit.commitSquashedInsts 18677700 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1482305 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 536038 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 151203395 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.514192 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.490223 # Number of insts commited each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.commit.committed_per_cycle::0 122740077 81.18% 81.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 14637973 9.68% 90.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 3917047 2.59% 93.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 2134429 1.41% 94.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 1622101 1.07% 95.93% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 972992 0.64% 96.57% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 1598831 1.06% 97.63% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 713641 0.47% 98.10% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 2866304 1.90% 100.00% # Number of insts commited each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.commit.committed_per_cycle::total 151203395 # Number of insts commited each cycle
system.cpu.commit.committedInsts 60456535 # Number of instructions committed
system.cpu.commit.committedOps 77747623 # Number of ops (including micro ops) committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.commit.refs 27385855 # Number of memory references committed
system.cpu.commit.loads 15654083 # Number of loads committed
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.commit.membars 403571 # Number of memory barriers committed
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.commit.branches 10305769 # Number of branches committed
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.commit.int_insts 69188185 # Number of committed integer instructions.
system.cpu.commit.function_calls 991209 # Number of function calls committed.
system.cpu.commit.bw_lim_events 2866304 # number cycles where commit BW limit reached
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.rob.rob_reads 242914035 # The number of ROB reads
system.cpu.rob.rob_writes 195975439 # The number of ROB writes
system.cpu.timesIdled 1776357 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 322870003 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 4575099289 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 60306154 # Number of Instructions Simulated
system.cpu.committedOps 77597242 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 60306154 # Number of Instructions Simulated
system.cpu.cpi 7.911491 # CPI: Cycles Per Instruction
system.cpu.cpi_total 7.911491 # CPI: Total CPI of All Threads
system.cpu.ipc 0.126398 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.126398 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 548607871 # number of integer regfile reads
system.cpu.int_regfile_writes 87541390 # number of integer regfile writes
system.cpu.fp_regfile_reads 8324 # number of floating regfile reads
system.cpu.fp_regfile_writes 2920 # number of floating regfile writes
system.cpu.misc_regfile_reads 268241142 # number of misc regfile reads
system.cpu.misc_regfile_writes 1173227 # number of misc regfile writes
system.cpu.toL2Bus.throughput 58865094 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 2658464 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 2658463 # Transaction distribution
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.toL2Bus.trans_dist::WriteReq 763332 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 763332 # Transaction distribution
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.toL2Bus.trans_dist::Writeback 607582 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 2966 # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 2978 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 246158 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 246158 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961995 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5795878 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31363 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128647 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 7917883 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62746624 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85500065 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 43624 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215596 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total 148505909 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 148505909 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 195968 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 3128804200 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.toL2Bus.respLayer0.occupancy 1474711974 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.toL2Bus.respLayer1.occupancy 2550008218 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.toL2Bus.respLayer2.occupancy 20466481 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.toL2Bus.respLayer3.occupancy 74842560 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.icache.tags.replacements 980909 # number of replacements
system.cpu.icache.tags.tagsinuse 511.574447 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 10459956 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 981421 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 10.657970 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 6918965000 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 511.574447 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.999169 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.999169 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 221 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 155 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.icache.tags.tag_accesses 12502670 # Number of tag accesses
system.cpu.icache.tags.data_accesses 12502670 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 10459956 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 10459956 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 10459956 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 10459956 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 10459956 # number of overall hits
system.cpu.icache.overall_hits::total 10459956 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1061258 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1061258 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1061258 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1061258 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1061258 # number of overall misses
system.cpu.icache.overall_misses::total 1061258 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 14277146640 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 14277146640 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 14277146640 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 14277146640 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 14277146640 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 14277146640 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 11521214 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 11521214 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 11521214 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 11521214 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 11521214 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 11521214 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092113 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.092113 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.092113 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.092113 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.092113 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.092113 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13453.040297 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13453.040297 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13453.040297 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13453.040297 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13453.040297 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13453.040297 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 6445 # number of cycles access was blocked
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.icache.blocked::no_mshrs 336 # number of cycles access was blocked
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 19.181548 # average number of cycles each access was blocked
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79801 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 79801 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 79801 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 79801 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 79801 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 79801 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981457 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 981457 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 981457 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 981457 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 981457 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 981457 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11591245017 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 11591245017 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11591245017 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 11591245017 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11591245017 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 11591245017 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8870000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8870000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8870000 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total 8870000 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085187 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085187 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085187 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.085187 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085187 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.085187 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11810.242341 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11810.242341 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11810.242341 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11810.242341 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11810.242341 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11810.242341 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.l2cache.tags.replacements 64359 # number of replacements
system.cpu.l2cache.tags.tagsinuse 51360.491961 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1887854 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 129751 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 14.549822 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 2490800967500 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 36938.900442 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 39.947099 # Average occupied blocks per requestor
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000373 # Average occupied blocks per requestor
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.l2cache.tags.occ_blocks::cpu.inst 8146.352593 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 6235.291454 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.563643 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000610 # Average percentage of cache occupancy
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124303 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.095143 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.783699 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023 28 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65364 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 28 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 357 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3045 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6929 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54997 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000427 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997375 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 18795937 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 18795937 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53847 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10904 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst 967954 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 386879 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1419584 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 607582 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 607582 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 43 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 43 # number of UpgradeReq hits
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 10 # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.l2cache.ReadExReq_hits::cpu.data 112973 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 112973 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 53847 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 10904 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 967954 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 499852 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1532557 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 53847 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 10904 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 967954 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 499852 # number of overall hits
system.cpu.l2cache.overall_hits::total 1532557 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 52 # number of ReadReq misses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.l2cache.ReadReq_misses::cpu.inst 12341 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 10725 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 23120 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2923 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 2923 # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 133185 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 133185 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 52 # number of demand (read+write) misses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.l2cache.demand_misses::cpu.inst 12341 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 143910 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 156305 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 52 # number of overall misses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.l2cache.overall_misses::cpu.inst 12341 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 143910 # number of overall misses
system.cpu.l2cache.overall_misses::total 156305 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 4042250 # number of ReadReq miss cycles
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 158000 # number of ReadReq miss cycles
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 908634500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 819979999 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 1732814749 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 583475 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 583475 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9837869742 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 9837869742 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 4042250 # number of demand (read+write) miss cycles
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 158000 # number of demand (read+write) miss cycles
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.l2cache.demand_miss_latency::cpu.inst 908634500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 10657849741 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 11570684491 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 4042250 # number of overall miss cycles
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 158000 # number of overall miss cycles
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.l2cache.overall_miss_latency::cpu.inst 908634500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 10657849741 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 11570684491 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53899 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10906 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst 980295 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 397604 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1442704 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 607582 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 607582 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2966 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 2966 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 12 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total 12 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 246158 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 246158 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53899 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 10906 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 980295 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 643762 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 1688862 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53899 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 10906 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 980295 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 643762 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 1688862 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000965 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000183 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012589 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026974 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.016025 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.985502 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.985502 # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.166667 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.166667 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541055 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.541055 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000965 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000183 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012589 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.223545 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.092550 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000965 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000183 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012589 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.223545 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.092550 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 77735.576923 # average ReadReq miss latency
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 79000 # average ReadReq miss latency
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73627.299246 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76455.011562 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 74948.734818 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 199.615121 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 199.615121 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73866.199212 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73866.199212 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 77735.576923 # average overall miss latency
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 79000 # average overall miss latency
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73627.299246 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74059.132381 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 74026.323477 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 77735.576923 # average overall miss latency
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 79000 # average overall miss latency
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73627.299246 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74059.132381 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 74026.323477 # average overall miss latency
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.l2cache.writebacks::writebacks 59102 # number of writebacks
system.cpu.l2cache.writebacks::total 59102 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 13 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 65 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 65 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 78 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 65 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 78 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 52 # number of ReadReq MSHR misses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12328 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10660 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 23042 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2923 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 2923 # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133185 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 133185 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 52 # number of demand (read+write) MSHR misses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.l2cache.demand_mshr_misses::cpu.inst 12328 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 143845 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 156227 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 52 # number of overall MSHR misses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.l2cache.overall_mshr_misses::cpu.inst 12328 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 143845 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 156227 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3398750 # number of ReadReq MSHR miss cycles
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 133500 # number of ReadReq MSHR miss cycles
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 752714750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 682165499 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1438412499 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29232923 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29232923 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 20002 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8179067758 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8179067758 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3398750 # number of demand (read+write) MSHR miss cycles
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 133500 # number of demand (read+write) MSHR miss cycles
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 752714750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8861233257 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 9617480257 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3398750 # number of overall MSHR miss cycles
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 133500 # number of overall MSHR miss cycles
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 752714750 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8861233257 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 9617480257 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 6336999 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166935139250 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166941476249 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17447345437 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17447345437 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 6336999 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184382484687 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184388821686 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000965 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000183 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012576 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026811 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015971 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985502 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985502 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.166667 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.166667 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541055 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541055 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000965 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000183 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012576 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223444 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.092504 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000965 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000183 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012576 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223444 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.092504 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65360.576923 # average ReadReq mshr miss latency
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 66750 # average ReadReq mshr miss latency
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61057.328845 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63993.011163 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62425.679151 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61411.328288 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61411.328288 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65360.576923 # average overall mshr miss latency
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 66750 # average overall mshr miss latency
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61057.328845 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61602.650471 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61560.935414 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65360.576923 # average overall mshr miss latency
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 66750 # average overall mshr miss latency
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61057.328845 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61602.650471 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61560.935414 # average overall mshr miss latency
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.dcache.tags.replacements 643250 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.993295 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 21507454 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 643762 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 33.409015 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 42602250 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.993295 # Average occupied blocks per requestor
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.dcache.tags.tag_accesses 101513406 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 101513406 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 13755166 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 13755166 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 7258873 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 7258873 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 242710 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 242710 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 247594 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 247594 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 21014039 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 21014039 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 21014039 # number of overall hits
system.cpu.dcache.overall_hits::total 21014039 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 736315 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 736315 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 2963189 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2963189 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 13552 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 13552 # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data 3699504 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 3699504 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 3699504 # number of overall misses
system.cpu.dcache.overall_misses::total 3699504 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 10015008577 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 10015008577 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 140227660304 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 140227660304 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 186052000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 186052000 # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 181002 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 181002 # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 150242668881 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 150242668881 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 150242668881 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 150242668881 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 14491481 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 14491481 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 10222062 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 10222062 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256262 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 256262 # number of LoadLockedReq accesses(hits+misses)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.dcache.StoreCondReq_accesses::cpu.data 247606 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 247606 # number of StoreCondReq accesses(hits+misses)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.dcache.demand_accesses::cpu.data 24713543 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 24713543 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 24713543 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 24713543 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050810 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.050810 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289882 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.289882 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052883 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052883 # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000048 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000048 # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.149695 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.149695 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.149695 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.149695 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13601.527304 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13601.527304 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47323.225182 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 47323.225182 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13728.748524 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13728.748524 # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15083.500000 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15083.500000 # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 40611.570870 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 40611.570870 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 40611.570870 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 40611.570870 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 31857 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 27549 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 2688 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 281 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.851562 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 98.039146 # average number of cycles each access was blocked
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.dcache.writebacks::writebacks 607582 # number of writebacks
system.cpu.dcache.writebacks::total 607582 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 350850 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 350850 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714158 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 2714158 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1320 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 1320 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 3065008 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 3065008 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 3065008 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 3065008 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385465 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 385465 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249031 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 249031 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12232 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 12232 # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 634496 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 634496 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 634496 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 634496 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4975619608 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4975619608 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11323354786 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 11323354786 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 146514250 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 146514250 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 156998 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 156998 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16298974394 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 16298974394 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16298974394 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 16298974394 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182328293250 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182328293250 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26845365872 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26845365872 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209173659122 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 209173659122 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026599 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026599 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024362 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024362 # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047732 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047732 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000048 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025674 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.025674 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025674 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.025674 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12908.096995 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12908.096995 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45469.659544 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45469.659544 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11977.947188 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11977.947188 # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13083.166667 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13083.166667 # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25688.064848 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 25688.064848 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25688.064848 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 25688.064848 # average overall mshr miss latency
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iocache.tags.replacements 0 # number of replacements
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.iocache.tags.tag_accesses 0 # Number of tag accesses
system.iocache.tags.data_accesses 0 # Number of data accesses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1499072952550 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1499072952550 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1499072952550 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1499072952550 # number of overall MSHR uncacheable cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.kern.inst.quiesce 83032 # number of quiesce instructions executed
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
---------- End Simulation Statistics ----------
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