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gem5/src/arch/arm/miscregs.hh

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ARM: Pull some static code out of the isa desc and create miscregs.hh.
2009-06-21 18:21:07 +02:00
/*
ARM: Add limited CP14 support. New kernels attempt to read CP14 what debug architecture is available. These changes add the debug registers and return that none is currently available.
2012-03-02 00:26:31 +01:00
* Copyright (c) 2010-2012 ARM Limited
ARM: Track the current ISA mode using the PC.
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* All rights reserved
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
ARM: Pull some static code out of the isa desc and create miscregs.hh.
2009-06-21 18:21:07 +02:00
* Copyright (c) 2009 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#ifndef __ARCH_ARM_MISCREGS_HH__
#define __ARCH_ARM_MISCREGS_HH__
#include "base/bitunion.hh"
arm: Use a static_assert to test that miscRegName[] is complete Instead of statically defining miscRegName to contain NUM_MISCREGS elements, let the compiler determine the length of the array. This allows us to use a static_assert to test that all registers are listed in the name vector.
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#include "base/compiler.hh"
ARM: Pull some static code out of the isa desc and create miscregs.hh.
2009-06-21 18:21:07 +02:00
namespace ArmISA
{
enum ConditionCode {
COND_EQ = 0,
COND_NE, // 1
COND_CS, // 2
COND_CC, // 3
COND_MI, // 4
COND_PL, // 5
COND_VS, // 6
COND_VC, // 7
COND_HI, // 8
COND_LS, // 9
COND_GE, // 10
COND_LT, // 11
COND_GT, // 12
COND_LE, // 13
COND_AL, // 14
ARM: Replace the "never" condition with the "unconditional" condition.
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COND_UC // 15
ARM: Pull some static code out of the isa desc and create miscregs.hh.
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};
enum MiscRegIndex {
MISCREG_CPSR = 0,
ARM: Remove the saturating (Q) condition code from the renamed register. Move the saturating bit (which is also saturating) from the renamed register that holds the flags to the CPSR miscreg and adds a allows setting it in a similar way to the FP saturating registers. This removes a dependency in instructions that don't write, but need to preserve the Q bit.
2011-05-14 00:27:01 +02:00
MISCREG_CPSR_Q,
ARM: Implement fault classes. Implement some fault classes using the curriously recurring template pattern, similar to SPARCs.
2009-11-11 05:34:38 +01:00
MISCREG_SPSR,
ARM: Pull some static code out of the isa desc and create miscregs.hh.
2009-06-21 18:21:07 +02:00
MISCREG_SPSR_FIQ,
MISCREG_SPSR_IRQ,
MISCREG_SPSR_SVC,
ARM: Add in more bits for the mon mode.
2009-11-08 11:01:02 +01:00
MISCREG_SPSR_MON,
ARM: Pull some static code out of the isa desc and create miscregs.hh.
2009-06-21 18:21:07 +02:00
MISCREG_SPSR_UND,
MISCREG_SPSR_ABT,
ARM: Fill out the printReg function.
2009-06-27 07:01:34 +02:00
MISCREG_FPSR,
ARM: Add in spots for the VFP control registers.
2009-07-27 09:53:10 +02:00
MISCREG_FPSID,
MISCREG_FPSCR,
O3: Make all instructions that write a misc. register not perform the write until commit. ARM instructions updating cumulative flags (ARM FP exceptions and saturation flags) are not serialized. Added aliases for ARM FP exceptions and saturation flags in FPSCR. Removed write accesses to the FP condition codes for most ARM VFP instructions: only VCMP and VCMPE instructions update the FP condition codes. Removed a potential cause of seg. faults in the O3 model for NEON memory macro-ops (ARM).
2010-12-08 01:19:57 +01:00
MISCREG_FPSCR_QC, // Cumulative saturation flag
MISCREG_FPSCR_EXC, // Cumulative FP exception flags
ARM: Add in spots for the VFP control registers.
2009-07-27 09:53:10 +02:00
MISCREG_FPEXC,
ARM: Update the set of FP related miscregs.
2010-06-02 19:58:11 +02:00
MISCREG_MVFR0,
MISCREG_MVFR1,
ARM: Implement ARM CPU interrupts
2010-06-02 19:58:16 +02:00
MISCREG_SCTLR_RST,
ARM: Add some support for wfi/wfe/yield/etc
2010-06-02 19:58:13 +02:00
MISCREG_SEV_MAILBOX,
ARM: Implement a function to decode CP15 registers to MiscReg indices.
2010-06-02 19:58:08 +02:00
ARM: Add limited CP14 support. New kernels attempt to read CP14 what debug architecture is available. These changes add the debug registers and return that none is currently available.
2012-03-02 00:26:31 +01:00
// CP14 registers
MISCREG_CP14_START,
MISCREG_DBGDIDR = MISCREG_CP14_START,
MISCREG_DBGDSCR_INT,
MISCREG_DBGDTRRX_INT,
MISCREG_DBGTRTX_INT,
MISCREG_DBGWFAR,
MISCREG_DBGVCR,
MISCREG_DBGECR,
MISCREG_DBGDSCCR,
MISCREG_DBGSMCR,
MISCREG_DBGDTRRX_EXT,
MISCREG_DBGDSCR_EXT,
MISCREG_DBGDTRTX_EXT,
MISCREG_DBGDRCR,
MISCREG_DBGBVR,
MISCREG_DBGBCR,
MISCREG_DBGBVR_M,
MISCREG_DBGBCR_M,
MISCREG_DBGDRAR,
MISCREG_DBGBXVR_M,
MISCREG_DBGOSLAR,
MISCREG_DBGOSSRR,
MISCREG_DBGOSDLR,
MISCREG_DBGPRCR,
MISCREG_DBGPRSR,
MISCREG_DBGDSAR,
MISCREG_DBGITCTRL,
MISCREG_DBGCLAIMSET,
MISCREG_DBGCLAIMCLR,
MISCREG_DBGAUTHSTATUS,
MISCREG_DBGDEVID2,
MISCREG_DBGDEVID1,
MISCREG_DBGDEVID,
ARM: Implement a function to decode CP15 registers to MiscReg indices.
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// CP15 registers
MISCREG_CP15_START,
MISCREG_SCTLR = MISCREG_CP15_START,
ARM: Warn about and ignore accesses to DCCISW. This register is supposed to "Clean and invalidate data or unified cache line by set/way." Since there isn't a good way to do that, we'll just ignore these and warn about it.
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MISCREG_DCCISW,
ARM: Ignore accesses to DCCIMVAC.
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MISCREG_DCCIMVAC,
ARM: Ignore/warn on accesses to the dccmvac register.
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MISCREG_DCCMVAC,
ARM: Allow accesses to the contextidr register.
2010-06-02 19:58:08 +02:00
MISCREG_CONTEXTIDR,
ARM: Allow accesses to the software thread id registers.
2010-06-02 19:58:08 +02:00
MISCREG_TPIDRURW,
MISCREG_TPIDRURO,
MISCREG_TPIDRPRW,
ARM: Decode the unimplemented cp15 instruction barrier.
2010-06-02 19:58:08 +02:00
MISCREG_CP15ISB,
ARM: Decode the unimplemented data barrier CP15 accesses. These are CP15DSB (Data Synchronization Barrier), and CP15DMB (Data Memory Barrier).
2010-06-02 19:58:09 +02:00
MISCREG_CP15DSB,
MISCREG_CP15DMB,
ARM: Implement a stub of CPACR. This register controls access to the coprocessors. This doesn't actually implement it, it allows writes which don't turn anything off. In other words, it allows the simulated program to ask for what it already has.
2010-06-02 19:58:09 +02:00
MISCREG_CPACR,
ARM: Add support for the clidr register. This register will always report 0 caches as implemented. It's not clear how to find out how many there really are when dealing with an arbitrary hierarchy.
2010-06-02 19:58:09 +02:00
MISCREG_CLIDR,
ARM: Ignore/warn when CSSELR or CCSIDR are accessed. These registers provide information about the caches. Since we can't provide that information, these will be harmlessly inert.
2010-06-02 19:58:09 +02:00
MISCREG_CCSIDR,
MISCREG_CSSELR,
ARM: Ignore/warn on ICIALLUIS.
2010-06-02 19:58:09 +02:00
MISCREG_ICIALLUIS,
ARM: Ignore/warn on iciallu.
2010-06-02 19:58:09 +02:00
MISCREG_ICIALLU,
ARM: Ignore/warn on accesses to icimvau.
2010-06-02 19:58:09 +02:00
MISCREG_ICIMVAU,
ARM: Ignore/warn access to the bpimva registers.
2010-06-02 19:58:09 +02:00
MISCREG_BPIMVA,
ARM: Ignore/warn on accesses to the BPIALLIS and BPIALL registers.
2010-06-02 19:58:10 +02:00
MISCREG_BPIALLIS,
MISCREG_BPIALL,
ARM: Make the MPUIR register report that 1 unified data region is supported.
2010-06-02 19:58:10 +02:00
MISCREG_MIDR,
ARM: Handle accesses to TTBR0 and TTBR1.
2010-06-02 19:58:13 +02:00
MISCREG_TTBR0,
MISCREG_TTBR1,
ARM: Handle accesses to TLBTR.
2010-06-02 19:58:13 +02:00
MISCREG_TLBTR,
ARM: Handle accesses to the DACR.
2010-06-02 19:58:13 +02:00
MISCREG_DACR,
ARM: Warn/ignore when TLB maintenance operations are performed.
2010-06-02 19:58:13 +02:00
MISCREG_TLBIALLIS,
MISCREG_TLBIMVAIS,
MISCREG_TLBIASIDIS,
MISCREG_TLBIMVAAIS,
MISCREG_ITLBIALL,
MISCREG_ITLBIMVA,
MISCREG_ITLBIASID,
MISCREG_DTLBIALL,
MISCREG_DTLBIMVA,
MISCREG_DTLBIASID,
MISCREG_TLBIALL,
MISCREG_TLBIMVA,
MISCREG_TLBIASID,
MISCREG_TLBIMVAA,
ARM: Implement and update the DFSR and IFSR registers on faults.
2010-06-02 19:58:14 +02:00
MISCREG_DFSR,
MISCREG_IFSR,
MISCREG_DFAR,
MISCREG_IFAR,
ARM: Make MPIDR return 0 and ignore writes.
2010-06-02 19:58:15 +02:00
MISCREG_MPIDR,
ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements.
2010-06-02 19:58:16 +02:00
MISCREG_PRRR,
MISCREG_NMRR,
MISCREG_TTBCR,
MISCREG_ID_PFR0,
ARM: Some TLB bug fixes.
2010-06-02 19:58:16 +02:00
MISCREG_CTR,
MISCREG_SCR,
MISCREG_SDER,
ARM: Added support for Access Flag and some CP15 regs (V2PCWPR, V2PCWPW, V2PCWUR, V2PCWUW,...)
2010-06-02 19:58:18 +02:00
MISCREG_PAR,
MISCREG_V2PCWPR,
MISCREG_V2PCWPW,
MISCREG_V2PCWUR,
MISCREG_V2PCWUW,
MISCREG_V2POWPR,
MISCREG_V2POWPW,
MISCREG_V2POWUR,
MISCREG_V2POWUW,
ARM: Implement some more misc registers
2010-08-23 18:18:40 +02:00
MISCREG_ID_MMFR0,
ARM: Add two unimplemented miscellaneous registers. Adds MISCREG_ID_MMFR2 and removes break on access to MISCREG_CLIDR. Both registers now return values that are consistent with current ARM implementations.
2011-07-15 18:53:34 +02:00
MISCREG_ID_MMFR2,
ARM: Add support for MP misc regs and broadcast flushes.
2011-05-05 03:38:28 +02:00
MISCREG_ID_MMFR3,
ARM: Implement some more misc registers
2010-08-23 18:18:40 +02:00
MISCREG_ACTLR,
MISCREG_PMCR,
MISCREG_PMCCNTR,
MISCREG_PMCNTENSET,
MISCREG_PMCNTENCLR,
MISCREG_PMOVSR,
MISCREG_PMSWINC,
MISCREG_PMSELR,
MISCREG_PMCEID0,
MISCREG_PMCEID1,
MISCREG_PMC_OTHER,
MISCREG_PMXEVCNTR,
MISCREG_PMUSERENR,
MISCREG_PMINTENSET,
MISCREG_PMINTENCLR,
ARM: Implement the Instruction Set Attribute Registers (ISAR). The ISAR registers describe which features the processor supports. Transcribe the values listed in section B5.2.5 of the ARM ARM into the registers as read-only values
2011-03-18 01:20:20 +01:00
MISCREG_ID_ISAR0,
MISCREG_ID_ISAR1,
MISCREG_ID_ISAR2,
MISCREG_ID_ISAR3,
MISCREG_ID_ISAR4,
MISCREG_ID_ISAR5,
ARM: Use CPU local lock before sending load to mem system. This change uses the locked_mem.hh header to handle implementing CLREX. It simplifies the current implementation greatly.
2011-04-04 18:42:29 +02:00
MISCREG_LOCKFLAG,
MISCREG_LOCKADDR,
ARM: Better RealView/Versatile EB platform support. Add registers and components to better support the VersatileEB board. Made the MIDR and SYS_ID register parameters to ArmSystem and RealviewCtrl respectively.
2011-05-14 00:27:00 +02:00
MISCREG_ID_PFR1,
ARM: Implement numcpus bits in L2CTLR register.
2011-09-13 19:06:13 +02:00
MISCREG_L2CTLR,
ARM: Implement a function to decode CP15 registers to MiscReg indices.
2010-06-02 19:58:08 +02:00
MISCREG_CP15_UNIMP_START,
ARM: Some TLB bug fixes.
2010-06-02 19:58:16 +02:00
MISCREG_TCMTR = MISCREG_CP15_UNIMP_START,
ARM: Implement a function to decode CP15 registers to MiscReg indices.
2010-06-02 19:58:08 +02:00
MISCREG_ID_DFR0,
MISCREG_ID_AFR0,
MISCREG_ID_MMFR1,
MISCREG_AIDR,
MISCREG_ADFSR,
MISCREG_AIFSR,
MISCREG_DCIMVAC,
MISCREG_DCISW,
MISCREG_MCCSW,
MISCREG_DCCMVAU,
ARM: Convert the CP15 registers from MPU to MMU.
2010-06-02 19:58:13 +02:00
MISCREG_NSACR,
MISCREG_VBAR,
MISCREG_MVBAR,
MISCREG_ISR,
MISCREG_FCEIDR,
ARM: Adds dummy support for a L2 latency miscreg.
2011-02-23 22:10:48 +01:00
MISCREG_L2LATENCY,
CP15 c15: enable execution with accesses to c15 registers Previously, coprocessor accesses to CP15 c15 would fault. This patch enables accesses but prints out a warning, as the registers are not implemented.
2011-09-13 19:06:13 +02:00
MISCREG_CRN15,
ARM: Convert the CP15 registers from MPU to MMU.
2010-06-02 19:58:13 +02:00
ARM: Implement a function to decode CP15 registers to MiscReg indices.
2010-06-02 19:58:08 +02:00
MISCREG_CP15_END,
// Dummy indices
MISCREG_NOP = MISCREG_CP15_END,
MISCREG_RAZ,
ARM: Implement fault classes. Implement some fault classes using the curriously recurring template pattern, similar to SPARCs.
2009-11-11 05:34:38 +01:00
NUM_MISCREGS
ARM: Fill out the printReg function.
2009-06-27 07:01:34 +02:00
};
ARM: Add limited CP14 support. New kernels attempt to read CP14 what debug architecture is available. These changes add the debug registers and return that none is currently available.
2012-03-02 00:26:31 +01:00
MiscRegIndex decodeCP14Reg(unsigned crn, unsigned opc1,
unsigned crm, unsigned opc2);
ARM: Implement a function to decode CP15 registers to MiscReg indices.
2010-06-02 19:58:08 +02:00
MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
unsigned crm, unsigned opc2);
ARM: Add limited CP14 support. New kernels attempt to read CP14 what debug architecture is available. These changes add the debug registers and return that none is currently available.
2012-03-02 00:26:31 +01:00
arm: Use a static_assert to test that miscRegName[] is complete Instead of statically defining miscRegName to contain NUM_MISCREGS elements, let the compiler determine the length of the array. This allows us to use a static_assert to test that all registers are listed in the name vector.
2012-09-25 18:49:40 +02:00
const char * const miscRegName[] = {
ARM: Remove the saturating (Q) condition code from the renamed register. Move the saturating bit (which is also saturating) from the renamed register that holds the flags to the CPSR miscreg and adds a allows setting it in a similar way to the FP saturating registers. This removes a dependency in instructions that don't write, but need to preserve the Q bit.
2011-05-14 00:27:01 +02:00
"cpsr", "cpsr_q", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
ARM: Implement a function to decode CP15 registers to MiscReg indices.
2010-06-02 19:58:08 +02:00
"spsr_mon", "spsr_und", "spsr_abt",
O3: Make all instructions that write a misc. register not perform the write until commit. ARM instructions updating cumulative flags (ARM FP exceptions and saturation flags) are not serialized. Added aliases for ARM FP exceptions and saturation flags in FPSCR. Removed write accesses to the FP condition codes for most ARM VFP instructions: only VCMP and VCMPE instructions update the FP condition codes. Removed a potential cause of seg. faults in the O3 model for NEON memory macro-ops (ARM).
2010-12-08 01:19:57 +01:00
"fpsr", "fpsid", "fpscr", "fpscr_qc", "fpscr_exc", "fpexc",
"mvfr0", "mvfr1",
ARM: Implement ARM CPU interrupts
2010-06-02 19:58:16 +02:00
"sctlr_rst", "sev_mailbox",
ARM: Add limited CP14 support. New kernels attempt to read CP14 what debug architecture is available. These changes add the debug registers and return that none is currently available.
2012-03-02 00:26:31 +01:00
"DBGDIDR",
"DBGDSCR_INT",
"DBGDTRRX_INT",
"DBGTRTX_INT",
"DBGWFAR",
"DBGVCR",
"DBGECR",
"DBGDSCCR",
"DBGSMCR",
"DBGDTRRX_EXT",
"DBGDSCR_EXT",
"DBGDTRTX_EXT",
"DBGDRCR",
"DBGBVR",
"DBGBCR",
"DBGBVR_M",
"DBGBCR_M",
"DBGDRAR",
"DBGBXVR_M",
"DBGOSLAR",
"DBGOSSRR",
"DBGOSDLR",
"DBGPRCR",
"DBGPRSR",
"DBGDSAR",
"DBGITCTRL",
"DBGCLAIMSET",
"DBGCLAIMCLR",
"DBGAUTHSTATUS",
"DBGDEVID2",
"DBGDEVID1",
"DBGDEVID",
ARM: Ignore/warn on accesses to the dccmvac register.
2010-06-02 19:58:09 +02:00
"sctlr", "dccisw", "dccimvac", "dccmvac",
ARM: Ignore accesses to DCCIMVAC.
2010-06-02 19:58:08 +02:00
"contextidr", "tpidrurw", "tpidruro", "tpidrprw",
ARM: Ignore/warn when CSSELR or CCSIDR are accessed. These registers provide information about the caches. Since we can't provide that information, these will be harmlessly inert.
2010-06-02 19:58:09 +02:00
"cp15isb", "cp15dsb", "cp15dmb", "cpacr",
"clidr", "ccsidr", "csselr",
ARM: Ignore/warn on accesses to the BPIALLIS and BPIALL registers.
2010-06-02 19:58:10 +02:00
"icialluis", "iciallu", "icimvau",
"bpimva", "bpiallis", "bpiall",
ARM: Warn/ignore when TLB maintenance operations are performed.
2010-06-02 19:58:13 +02:00
"midr", "ttbr0", "ttbr1", "tlbtr", "dacr",
"tlbiallis", "tlbimvais", "tlbiasidis", "tlbimvaais",
"itlbiall", "itlbimva", "itlbiasid",
"dtlbiall", "dtlbimva", "dtlbiasid",
"tlbiall", "tlbimva", "tlbiasid", "tlbimvaa",
ARM: Make MPIDR return 0 and ignore writes.
2010-06-02 19:58:15 +02:00
"dfsr", "ifsr", "dfar", "ifar", "mpidr",
ARM: Added support for Access Flag and some CP15 regs (V2PCWPR, V2PCWPW, V2PCWUR, V2PCWUW,...)
2010-06-02 19:58:18 +02:00
"prrr", "nmrr", "ttbcr", "id_pfr0", "ctr",
"scr", "sder", "par",
"v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw",
"v2powpr", "v2powpw", "v2powur", "v2powuw",
ARM: Add two unimplemented miscellaneous registers. Adds MISCREG_ID_MMFR2 and removes break on access to MISCREG_CLIDR. Both registers now return values that are consistent with current ARM implementations.
2011-07-15 18:53:34 +02:00
"id_mmfr0", "id_mmfr2", "id_mmfr3", "actlr", "pmcr", "pmccntr",
ARM: Implement some more misc registers
2010-08-23 18:18:40 +02:00
"pmcntenset", "pmcntenclr", "pmovsr",
"pmswinc", "pmselr", "pmceid0",
"pmceid1", "pmc_other", "pmxevcntr",
"pmuserenr", "pmintenset", "pmintenclr",
ARM: Implement the Instruction Set Attribute Registers (ISAR). The ISAR registers describe which features the processor supports. Transcribe the values listed in section B5.2.5 of the ARM ARM into the registers as read-only values
2011-03-18 01:20:20 +01:00
"id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
arm: Remove the register mapping hack used when copying TCs In order to see all registers independent of the current CPU mode, the ARM architecture model uses the magic MISCREG_CPSR_MODE register to change the register mappings without actually updating the CPU mode. This hack is no longer needed since the thread context now provides a flat interface to the register file. This patch replaces the CPSR_MODE hack with the flat register interface.
2013-01-07 19:05:44 +01:00
"lockflag", "lockaddr", "id_pfr1",
ARM: Implement numcpus bits in L2CTLR register.
2011-09-13 19:06:13 +02:00
"l2ctlr",
ARM: Implement some more misc registers
2010-08-23 18:18:40 +02:00
// Unimplemented below
ARM: Some TLB bug fixes.
2010-06-02 19:58:16 +02:00
"tcmtr",
ARM: Better RealView/Versatile EB platform support. Add registers and components to better support the VersatileEB board. Made the MIDR and SYS_ID register parameters to ArmSystem and RealviewCtrl respectively.
2011-05-14 00:27:00 +02:00
"id_dfr0", "id_afr0",
ARM: Add two unimplemented miscellaneous registers. Adds MISCREG_ID_MMFR2 and removes break on access to MISCREG_CLIDR. Both registers now return values that are consistent with current ARM implementations.
2011-07-15 18:53:34 +02:00
"id_mmfr1",
ARM: Implement the Instruction Set Attribute Registers (ISAR). The ISAR registers describe which features the processor supports. Transcribe the values listed in section B5.2.5 of the ARM ARM into the registers as read-only values
2011-03-18 01:20:20 +01:00
"aidr", "adfsr", "aifsr",
ARM: Ignore/warn on accesses to the BPIALLIS and BPIALL registers.
2010-06-02 19:58:10 +02:00
"dcimvac", "dcisw", "mccsw",
ARM: Decode the unimplemented data barrier CP15 accesses. These are CP15DSB (Data Synchronization Barrier), and CP15DMB (Data Memory Barrier).
2010-06-02 19:58:09 +02:00
"dccmvau",
ARM: Some TLB bug fixes.
2010-06-02 19:58:16 +02:00
"nsacr",
Arm: Add in a missing miscRegName.
2011-03-25 05:46:14 +01:00
"vbar", "mvbar", "isr", "fceidr", "l2latency",
CP15 c15: enable execution with accesses to c15 registers Previously, coprocessor accesses to CP15 c15 would fault. This patch enables accesses but prints out a warning, as the registers are not implemented.
2011-09-13 19:06:13 +02:00
"crn15",
ARM: Implement a function to decode CP15 registers to MiscReg indices.
2010-06-02 19:58:08 +02:00
"nop", "raz"
ARM: Pull some static code out of the isa desc and create miscregs.hh.
2009-06-21 18:21:07 +02:00
};
arm: Use a static_assert to test that miscRegName[] is complete Instead of statically defining miscRegName to contain NUM_MISCREGS elements, let the compiler determine the length of the array. This allows us to use a static_assert to test that all registers are listed in the name vector.
2012-09-25 18:49:40 +02:00
static_assert(sizeof(miscRegName) / sizeof(*miscRegName) == NUM_MISCREGS,
"The miscRegName array and NUM_MISCREGS are inconsistent.");
ARM: Pull some static code out of the isa desc and create miscregs.hh.
2009-06-21 18:21:07 +02:00
BitUnion32(CPSR)
ARM: Further break up condition code into NZ, C, V bits. Break up the condition code bits into NZ, C, V registers. These are individually written and this removes some incorrect dependencies between instructions.
2011-05-14 00:27:01 +02:00
Bitfield<31,30> nz;
ARM: Pull some static code out of the isa desc and create miscregs.hh.
2009-06-21 18:21:07 +02:00
Bitfield<29> c;
Bitfield<28> v;
Bitfield<27> q;
ARM: Implement fault classes. Implement some fault classes using the curriously recurring template pattern, similar to SPARCs.
2009-11-11 05:34:38 +01:00
Bitfield<26,25> it1;
ARM: Pull some static code out of the isa desc and create miscregs.hh.
2009-06-21 18:21:07 +02:00
Bitfield<24> j;
Bitfield<19, 16> ge;
ARM: Implement fault classes. Implement some fault classes using the curriously recurring template pattern, similar to SPARCs.
2009-11-11 05:34:38 +01:00
Bitfield<15,10> it2;
ARM: Pull some static code out of the isa desc and create miscregs.hh.
2009-06-21 18:21:07 +02:00
Bitfield<9> e;
Bitfield<8> a;
Bitfield<7> i;
Bitfield<6> f;
Bitfield<5> t;
Bitfield<4, 0> mode;
EndBitUnion(CPSR)
ARM: Implement fault classes. Implement some fault classes using the curriously recurring template pattern, similar to SPARCs.
2009-11-11 05:34:38 +01:00
ARM: Define a mask to differentiate purely CPSR bits from CondCodes bits.
2009-11-15 04:22:30 +01:00
// This mask selects bits of the CPSR that actually go in the CondCodes
// integer register to allow renaming.
ARM: Remove the saturating (Q) condition code from the renamed register. Move the saturating bit (which is also saturating) from the renamed register that holds the flags to the CPSR miscreg and adds a allows setting it in a similar way to the FP saturating registers. This removes a dependency in instructions that don't write, but need to preserve the Q bit.
2011-05-14 00:27:01 +02:00
static const uint32_t CondCodesMask = 0xF00F0000;
static const uint32_t CpsrMaskQ = 0x08000000;
ARM: Define a mask to differentiate purely CPSR bits from CondCodes bits.
2009-11-15 04:22:30 +01:00
ARM: Implement fault classes. Implement some fault classes using the curriously recurring template pattern, similar to SPARCs.
2009-11-11 05:34:38 +01:00
BitUnion32(SCTLR)
ARM: Add in some missing SCTLR fields.
2010-06-02 19:58:13 +02:00
Bitfield<31> ie; // Instruction endianness
ARM: Implement fault classes. Implement some fault classes using the curriously recurring template pattern, similar to SPARCs.
2009-11-11 05:34:38 +01:00
Bitfield<30> te; // Thumb Exception Enable
Bitfield<29> afe; // Access flag enable
ARM: removed extra white space Extra white space fixes in miscregs.hh
2012-06-05 07:23:10 +02:00
Bitfield<28> tre; // TEX Remap bit
ARM: Implement fault classes. Implement some fault classes using the curriously recurring template pattern, similar to SPARCs.
2009-11-11 05:34:38 +01:00
Bitfield<27> nmfi;// Non-maskable fast interrupts enable
Bitfield<25> ee; // Exception Endianness bit
Bitfield<24> ve; // Interrupt vectors enable
ARM: Some TLB bug fixes.
2010-06-02 19:58:16 +02:00
Bitfield<23> xp; // Extended page table enable bit
ARM: Implement fault classes. Implement some fault classes using the curriously recurring template pattern, similar to SPARCs.
2009-11-11 05:34:38 +01:00
Bitfield<22> u; // Alignment (now unused)
Bitfield<21> fi; // Fast interrupts configuration enable
ARM: Add in some missing SCTLR fields.
2010-06-02 19:58:13 +02:00
Bitfield<19> dz; // Divide by Zero fault enable bit
ARM: Implement fault classes. Implement some fault classes using the curriously recurring template pattern, similar to SPARCs.
2009-11-11 05:34:38 +01:00
Bitfield<18> rao2;// Read as one
ARM: Add in some missing SCTLR fields.
2010-06-02 19:58:13 +02:00
Bitfield<17> br; // Background region bit
ARM: Implement fault classes. Implement some fault classes using the curriously recurring template pattern, similar to SPARCs.
2009-11-11 05:34:38 +01:00
Bitfield<16> rao3;// Read as one
Bitfield<14> rr; // Round robin cache replacement
Bitfield<13> v; // Base address for exception vectors
Bitfield<12> i; // instruction cache enable
Bitfield<11> z; // branch prediction enable bit
Bitfield<10> sw; // Enable swp/swpb
ARM: Some TLB bug fixes.
2010-06-02 19:58:16 +02:00
Bitfield<9,8> rs; // deprecated protection bits
ARM: Implement fault classes. Implement some fault classes using the curriously recurring template pattern, similar to SPARCs.
2009-11-11 05:34:38 +01:00
Bitfield<6,3> rao4;// Read as one
ARM: removed extra white space Extra white space fixes in miscregs.hh
2012-06-05 07:23:10 +02:00
Bitfield<7> b; // Endianness support (unused)
ARM: Implement fault classes. Implement some fault classes using the curriously recurring template pattern, similar to SPARCs.
2009-11-11 05:34:38 +01:00
Bitfield<2> c; // Cache enable bit
Bitfield<1> a; // Alignment fault checking
ARM: removed extra white space Extra white space fixes in miscregs.hh
2012-06-05 07:23:10 +02:00
Bitfield<0> m; // MMU enable bit
ARM: Implement fault classes. Implement some fault classes using the curriously recurring template pattern, similar to SPARCs.
2009-11-11 05:34:38 +01:00
EndBitUnion(SCTLR)
ARM: Ignore attempts to disable coprocessors that aren't implemented anyway.
2010-06-02 19:58:11 +02:00
BitUnion32(CPACR)
Bitfield<1, 0> cp0;
Bitfield<3, 2> cp1;
Bitfield<5, 4> cp2;
Bitfield<7, 6> cp3;
Bitfield<9, 8> cp4;
Bitfield<11, 10> cp5;
Bitfield<13, 12> cp6;
Bitfield<15, 14> cp7;
Bitfield<17, 16> cp8;
Bitfield<19, 18> cp9;
Bitfield<21, 20> cp10;
Bitfield<23, 22> cp11;
Bitfield<25, 24> cp12;
Bitfield<27, 26> cp13;
ARM: Cleanup and small fixes to some NEON ops to match the spec. Only certain bits of the cpacr can be written, some must be equal. Mult instructions that write the same register should do something sane
2011-04-04 18:42:28 +02:00
Bitfield<29, 28> rsvd;
ARM: Ignore attempts to disable coprocessors that aren't implemented anyway.
2010-06-02 19:58:11 +02:00
Bitfield<30> d32dis;
Bitfield<31> asedis;
EndBitUnion(CPACR)
ARM: Implement and update the DFSR and IFSR registers on faults.
2010-06-02 19:58:14 +02:00
BitUnion32(FSR)
Bitfield<3, 0> fsLow;
Bitfield<7, 4> domain;
Bitfield<10> fsHigh;
Bitfield<11> wnr;
Bitfield<12> ext;
EndBitUnion(FSR)
ARM: Add support for VFP vector mode.
2010-06-02 19:58:14 +02:00
BitUnion32(FPSCR)
Bitfield<0> ioc;
Bitfield<1> dzc;
Bitfield<2> ofc;
Bitfield<3> ufc;
Bitfield<4> ixc;
Bitfield<7> idc;
Bitfield<8> ioe;
Bitfield<9> dze;
Bitfield<10> ofe;
Bitfield<11> ufe;
Bitfield<12> ixe;
Bitfield<15> ide;
Bitfield<18, 16> len;
Bitfield<21, 20> stride;
Bitfield<23, 22> rMode;
Bitfield<24> fz;
Bitfield<25> dn;
Bitfield<26> ahp;
Bitfield<27> qc;
Bitfield<28> v;
Bitfield<29> c;
Bitfield<30> z;
Bitfield<31> n;
EndBitUnion(FPSCR)
ARM: Set the value of the MVFR0 and MVFR1 registers.
2010-06-02 19:58:15 +02:00
ARM: Seperate out the renamable bits in the FPSCR.
2010-08-26 02:10:42 +02:00
// This mask selects bits of the FPSCR that actually go in the FpCondCodes
// integer register to allow renaming.
O3: Make all instructions that write a misc. register not perform the write until commit. ARM instructions updating cumulative flags (ARM FP exceptions and saturation flags) are not serialized. Added aliases for ARM FP exceptions and saturation flags in FPSCR. Removed write accesses to the FP condition codes for most ARM VFP instructions: only VCMP and VCMPE instructions update the FP condition codes. Removed a potential cause of seg. faults in the O3 model for NEON memory macro-ops (ARM).
2010-12-08 01:19:57 +01:00
static const uint32_t FpCondCodesMask = 0xF0000000;
// This mask selects the cumulative FP exception flags of the FPSCR.
static const uint32_t FpscrExcMask = 0x0000009F;
// This mask selects the cumulative saturation flag of the FPSCR.
static const uint32_t FpscrQcMask = 0x08000000;
ARM: Seperate out the renamable bits in the FPSCR.
2010-08-26 02:10:42 +02:00
ARM: Implement CPACR register and return Undefined Instruction when FP access is disabled.
2010-08-26 02:10:42 +02:00
BitUnion32(FPEXC)
Bitfield<31> ex;
Bitfield<30> en;
Bitfield<29, 0> subArchDefined;
EndBitUnion(FPEXC)
ARM: Set the value of the MVFR0 and MVFR1 registers.
2010-06-02 19:58:15 +02:00
BitUnion32(MVFR0)
Bitfield<3, 0> advSimdRegisters;
Bitfield<7, 4> singlePrecision;
Bitfield<11, 8> doublePrecision;
Bitfield<15, 12> vfpExceptionTrapping;
Bitfield<19, 16> divide;
Bitfield<23, 20> squareRoot;
Bitfield<27, 24> shortVectors;
Bitfield<31, 28> roundingModes;
EndBitUnion(MVFR0)
BitUnion32(MVFR1)
Bitfield<3, 0> flushToZero;
Bitfield<7, 4> defaultNaN;
Bitfield<11, 8> advSimdLoadStore;
Bitfield<15, 12> advSimdInteger;
Bitfield<19, 16> advSimdSinglePrecision;
Bitfield<23, 20> advSimdHalfPrecision;
Bitfield<27, 24> vfpHalfPrecision;
Bitfield<31, 28> raz;
EndBitUnion(MVFR1)
ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements.
2010-06-02 19:58:16 +02:00
BitUnion32(PRRR)
Bitfield<1,0> tr0;
Bitfield<3,2> tr1;
Bitfield<5,4> tr2;
Bitfield<7,6> tr3;
Bitfield<9,8> tr4;
Bitfield<11,10> tr5;
Bitfield<13,12> tr6;
Bitfield<15,14> tr7;
Bitfield<16> ds0;
Bitfield<17> ds1;
Bitfield<18> ns0;
Bitfield<19> ns1;
Bitfield<24> nos0;
Bitfield<25> nos1;
Bitfield<26> nos2;
Bitfield<27> nos3;
Bitfield<28> nos4;
Bitfield<29> nos5;
Bitfield<30> nos6;
Bitfield<31> nos7;
EndBitUnion(PRRR)
BitUnion32(NMRR)
Bitfield<1,0> ir0;
Bitfield<3,2> ir1;
Bitfield<5,4> ir2;
Bitfield<7,6> ir3;
Bitfield<9,8> ir4;
Bitfield<11,10> ir5;
Bitfield<13,12> ir6;
Bitfield<15,14> ir7;
Bitfield<17,16> or0;
Bitfield<19,18> or1;
Bitfield<21,20> or2;
Bitfield<23,22> or3;
Bitfield<25,24> or4;
Bitfield<27,26> or5;
Bitfield<29,28> or6;
Bitfield<31,30> or7;
EndBitUnion(NMRR)
ARM: update TLB to set request packet ASID field
2011-09-13 19:06:13 +02:00
BitUnion32(CONTEXTIDR)
Bitfield<7,0> asid;
Bitfield<31,8> procid;
EndBitUnion(CONTEXTIDR)
ARM: Implement numcpus bits in L2CTLR register.
2011-09-13 19:06:13 +02:00
BitUnion32(L2CTLR)
Bitfield<2,0> sataRAMLatency;
Bitfield<4,3> reserved_4_3;
Bitfield<5> dataRAMSetup;
Bitfield<8,6> tagRAMLatency;
Bitfield<9> tagRAMSetup;
Bitfield<11,10> dataRAMSlice;
Bitfield<12> tagRAMSlice;
Bitfield<20,13> reserved_20_13;
Bitfield<21> eccandParityEnable;
Bitfield<22> reserved_22;
Bitfield<23> interptCtrlPresent;
Bitfield<25,24> numCPUs;
Bitfield<30,26> reserved_30_26;
Bitfield<31> l2rstDISABLE_monitor;
EndBitUnion(L2CTLR)
ARM: fix value of MISCREG_CTR returned by readMiscReg() According to the A15 TRM the value of this register is as follows (assuming 16 word = 64 byte lines) [31:29] Format - b100 specifies v7 [28] RAZ - b0 [27:24] CWG log2(max writeback size #words) - 0x4 16 words [23:20] ERG log2(max reservation size #words) - 0x4 16 words [19:16] DminLine log2(smallest dcache line #words) - 0x4 16 words [15:14] L1Ip L1 index/tagging policy - b11 specifies PIPT [13:4] RAZ - b0000000000 [3:0] IminLine log2(smallest icache line #words) - 0x4 16 words
2012-07-27 22:08:04 +02:00
BitUnion32(CTR)
Bitfield<3,0> iCacheLineSize;
Bitfield<13,4> raz_13_4;
Bitfield<15,14> l1IndexPolicy;
Bitfield<19,16> dCacheLineSize;
Bitfield<23,20> erg;
Bitfield<27,24> cwg;
Bitfield<28> raz_28;
Bitfield<31,29> format;
EndBitUnion(CTR)
gcc: Clean-up of non-C++0x compliant code, first steps This patch cleans up a number of minor issues aiming to get closer to compliance with the C++0x standard as interpreted by gcc and clang (compile with std=c++0x and -pedantic-errors). In particular, the patch cleans up enums where the last item was succeded by a comma, namespaces closed by a curcly brace followed by a semi-colon, and the use of the GNU-extension typeof (replaced by templated functions). It does not address variable-length arrays, zero-size arrays, anonymous structs, range expressions in switch statements, and the use of long long. The generated CPU code also has a large number of issues that remain to be fixed, mainly related to overflows in implicit constant conversion (due to shifts).
2012-03-19 11:36:09 +01:00
}
ARM: Pull some static code out of the isa desc and create miscregs.hh.
2009-06-21 18:21:07 +02:00
#endif // __ARCH_ARM_MISCREGS_HH__
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