84 lines
2.7 KiB
C++
84 lines
2.7 KiB
C++
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/*
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* Copyright (c) 2009 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#ifndef __ARCH_ARM_MISCREGS_HH__
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#define __ARCH_ARM_MISCREGS_HH__
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#include "base/bitunion.hh"
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namespace ArmISA
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{
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enum ConditionCode {
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COND_EQ = 0,
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COND_NE, // 1
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COND_CS, // 2
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COND_CC, // 3
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COND_MI, // 4
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COND_PL, // 5
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COND_VS, // 6
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COND_VC, // 7
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COND_HI, // 8
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COND_LS, // 9
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COND_GE, // 10
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COND_LT, // 11
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COND_GT, // 12
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COND_LE, // 13
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COND_AL, // 14
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COND_NV // 15
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};
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enum MiscRegIndex {
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MISCREG_CPSR = 0,
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MISCREG_SPSR_FIQ,
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MISCREG_SPSR_IRQ,
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MISCREG_SPSR_SVC,
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MISCREG_SPSR_UND,
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MISCREG_SPSR_ABT,
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MISCREG_FPSR
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};
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BitUnion32(CPSR)
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Bitfield<31> n;
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Bitfield<30> z;
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Bitfield<29> c;
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Bitfield<28> v;
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Bitfield<27> q;
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Bitfield<24> j;
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Bitfield<19, 16> ge;
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Bitfield<9> e;
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Bitfield<8> a;
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Bitfield<7> i;
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Bitfield<6> f;
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Bitfield<5> t;
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Bitfield<4, 0> mode;
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EndBitUnion(CPSR)
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};
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#endif // __ARCH_ARM_MISCREGS_HH__
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