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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini

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ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
[root]
type=Root
children=system
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
Regressions: Update stats due to O3 CPU changes
2012-02-10 16:51:37 +01:00
full_system=true
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
sim_quantum=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=LinuxArmSystem
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
atags_addr=134217728
boot_loader=/dist/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
boot_release_addr=65528
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
cache_line_size=64
clk_domain=system.clk_domain
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
early_kernel_symbols=false
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
enable_context_switch_stats_dump=false
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
flags_addr=469827632
gic_cpu_addr=738205696
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
have_generic_timer=false
have_large_asid_64=false
have_lpae=false
have_security=false
have_virtualization=false
highest_el_is_64=false
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
init_param=0
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
kernel_addr_check=true
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
load_addr_mask=268435455
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
load_offset=2147483648
machine_type=VExpress_EMM
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
mem_mode=timing
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
mem_ranges=2147483648:2415919103
memories=system.realview.nvmem system.physmem system.realview.vram
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
multi_proc=true
stats: Update stats for ARM init param changes.
2012-01-10 01:08:20 +01:00
num_work_ids=16
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
panic_on_oops=true
panic_on_panic=true
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
phys_addr_range_64=40
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
readfile=/work/gem5.ext/tests/halt.sh
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
reset_addr_64=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system_port=system.membus.slave[1]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
[system.bridge]
type=Bridge
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
delay=50000
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
req_size=16
resp_size=16
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
master=system.iobus.slave[0]
slave=system.membus.master[0]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.cf0]
type=IdeDisk
children=image
delay=1000000
driveID=master
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
image=system.cf0.image
[system.cf0.image]
type=CowDiskImage
children=child
child=system.cf0.image.child
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
image_file=
read_only=false
table_size=65536
[system.cf0.image.child]
type=RawDiskImage
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
image_file=/dist/disks/linux-aarch32-ael.img
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
read_only=true
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.clk_domain]
type=SrcClockDomain
clock=1000
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
domain_id=-1
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
init_perf_level=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
voltage_domain=system.voltage_domain
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
[system.cpu]
type=DerivO3CPU
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
LFSTSize=1024
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
LQEntries=16
ARM: Update stats for previous changes.
2011-04-04 18:42:31 +02:00
LSQCheckLoads=true
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
LSQDepCheckShift=0
SQEntries=16
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
SSITSize=1024
activity=0
backComSize=5
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
branchPred=system.cpu.branchPred
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
cachePorts=200
checker=Null
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
decodeToRenameDelay=2
decodeWidth=3
dispatchWidth=6
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
dstage2_mmu=system.cpu.dstage2_mmu
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
dtb=system.cpu.dtb
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
fetchBufferSize=16
fetchQueueSize=32
fetchToDecodeDelay=3
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
fetchTrapLatency=1
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
fetchWidth=3
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
interrupts=system.cpu.interrupts
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
isa=system.cpu.isa
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
issueToExecuteDelay=1
issueWidth=8
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
istage2_mmu=system.cpu.istage2_mmu
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
Regressions: Update stats due to O3 CPU changes
2012-02-10 16:51:37 +01:00
needsTSO=false
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
numIQEntries=32
numPhysCCRegs=640
numPhysFloatRegs=192
numPhysIntRegs=128
numROBEntries=40
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
numRobs=1
numThreads=1
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
renameToIEWDelay=1
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
renameToROBDelay=1
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
renameWidth=3
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
simpoint_start_insts=
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
socket_id=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
squashWidth=8
StoreSet: Update stats for store-set clearing
2011-08-19 22:08:08 +02:00
store_set_clear_period=250000
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
switched_out=false
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
system=system
tracer=system.cpu.tracer
trapLatency=13
wbWidth=8
Regressions: Update stats due to O3 CPU changes
2012-02-10 16:51:37 +01:00
workload=
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
[system.cpu.branchPred]
type=BranchPredictor
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
BTBEntries=2048
BTBTagSize=18
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
globalCtrBits=2
globalPredictorSize=8192
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
predType=bi-mode
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
[system.cpu.dcache]
type=BaseCache
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
children=tags
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
addr_ranges=0:18446744073709551615
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
assoc=4
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
forward_snoops=true
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
hit_latency=2
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
prefetcher=Null
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
response_latency=2
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
size=32768
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system=system
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
tags=system.cpu.dcache.tags
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
mem_side=system.cpu.toL2Bus.slave[1]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.cpu.dcache.tags]
type=LRU
assoc=4
block_size=64
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
hit_latency=2
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
size=32768
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[5]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
[system.cpu.dtb]
type=ArmTLB
children=walker
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
is_stage2=false
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
is_stage2=false
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
num_squash_per_cycle=2
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
sys=system
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
port=system.cpu.toL2Bus.slave[3]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
[system.cpu.fuPool]
type=FUPool
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
children=FUList0 FUList1 FUList2 FUList3 FUList4
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
count=2
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
issueLat=1
opClass=IntAlu
opLat=1
[system.cpu.fuPool.FUList1]
type=FUDesc
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
children=opList0 opList1 opList2
count=1
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
issueLat=1
opClass=IntMult
opLat=3
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
issueLat=12
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
opClass=IntDiv
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opLat=12
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList1.opList2]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
issueLat=1
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opClass=IprAccess
opLat=3
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList
count=1
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opList=system.cpu.fuPool.FUList2.opList
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList2.opList]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
issueLat=1
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opClass=MemRead
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
opLat=2
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
count=1
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opList=system.cpu.fuPool.FUList3.opList
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList3.opList]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
issueLat=1
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opClass=MemWrite
opLat=2
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
type=FUDesc
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
count=2
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList00]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
issueLat=1
opClass=SimdAdd
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opLat=4
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList01]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
issueLat=1
opClass=SimdAddAcc
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opLat=4
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList02]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
issueLat=1
opClass=SimdAlu
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opLat=4
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList03]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
issueLat=1
opClass=SimdCmp
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opLat=4
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList04]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
issueLat=1
opClass=SimdCvt
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opLat=3
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList05]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
issueLat=1
opClass=SimdMisc
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opLat=3
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList06]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
issueLat=1
opClass=SimdMult
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opLat=5
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList07]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
issueLat=1
opClass=SimdMultAcc
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opLat=5
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList08]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
issueLat=1
opClass=SimdShift
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opLat=3
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList09]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
issueLat=1
opClass=SimdShiftAcc
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opLat=3
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList10]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
issueLat=1
opClass=SimdSqrt
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opLat=9
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList11]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
issueLat=1
opClass=SimdFloatAdd
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opLat=5
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList12]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
issueLat=1
opClass=SimdFloatAlu
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opLat=5
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList13]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
issueLat=1
opClass=SimdFloatCmp
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opLat=3
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList14]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
issueLat=1
opClass=SimdFloatCvt
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opLat=3
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList15]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
issueLat=1
opClass=SimdFloatDiv
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opLat=3
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList16]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
issueLat=1
opClass=SimdFloatMisc
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opLat=3
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList17]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
issueLat=1
opClass=SimdFloatMult
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opLat=3
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList18]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList19]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
issueLat=1
opClass=SimdFloatSqrt
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opLat=9
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList20]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
issueLat=1
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opClass=FloatAdd
opLat=5
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList21]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
issueLat=1
opClass=FloatCmp
opLat=5
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList22]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
issueLat=1
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opClass=FloatCvt
opLat=5
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList23]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
issueLat=9
opClass=FloatDiv
opLat=9
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList24]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
issueLat=33
opClass=FloatSqrt
opLat=33
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList25]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
issueLat=1
opClass=FloatMult
opLat=4
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
[system.cpu.icache]
type=BaseCache
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
children=tags
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
addr_ranges=0:18446744073709551615
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
assoc=1
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
forward_snoops=true
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
hit_latency=2
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
prefetcher=Null
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
response_latency=2
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
size=32768
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system=system
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
tags=system.cpu.icache.tags
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
mem_side=system.cpu.toL2Bus.slave[0]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.cpu.icache.tags]
type=LRU
assoc=1
block_size=64
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
hit_latency=2
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
size=32768
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
[system.cpu.interrupts]
type=ArmInterrupts
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
[system.cpu.isa]
type=ArmISA
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
fpsid=1090793632
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
id_mmfr0=270536963
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
id_mmfr1=0
id_mmfr2=19070976
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
id_mmfr3=34611729
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
id_pfr0=49
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
id_pfr1=4113
midr=1091551472
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pmu=Null
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system=system
[system.cpu.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.istage2_mmu.stage2_tlb.walker
[system.cpu.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[4]
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
[system.cpu.itb]
type=ArmTLB
children=walker
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
is_stage2=false
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
is_stage2=false
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
num_squash_per_cycle=2
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
sys=system
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
children=tags
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
addr_ranges=0:18446744073709551615
assoc=8
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
forward_snoops=true
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
response_latency=20
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
size=4194304
system=system
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
tags=system.cpu.l2cache.tags
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
mem_side=system.membus.slave[2]
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.cpu.l2cache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
hit_latency=20
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
size=4194304
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
[system.cpu.toL2Bus]
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
type=CoherentXBar
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
header_cycles=1
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
snoop_filter=Null
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system=system
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
[system.cpu.tracer]
type=ExeTracer
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
domain_id=-1
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
init_perf_level=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
voltage_domain=system.voltage_domain
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
[system.intrctrl]
type=IntrControl
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
sys=system
[system.iobus]
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
type=NoncoherentXBar
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
header_cycles=1
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
use_default_range=true
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
width=8
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
[system.iocache]
type=BaseCache
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
children=tags
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
addr_ranges=2147483648:2415919103
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
assoc=8
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
forward_snoops=false
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
hit_latency=50
is_top_level=true
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
max_miss_count=0
mshrs=20
prefetch_on_access=false
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
prefetcher=Null
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
response_latency=50
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
size=1024
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system=system
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
tags=system.iocache.tags
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
tgts_per_mshr=12
two_queue=false
write_buffers=8
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
cpu_side=system.iobus.master[27]
mem_side=system.membus.slave[3]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.iocache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
hit_latency=50
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
size=1024
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
[system.membus]
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
type=CoherentXBar
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
children=badaddr_responder
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
header_cycles=1
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
snoop_filter=Null
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system=system
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
use_default_range=false
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
width=8
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
default=system.membus.badaddr_responder.pio
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
[system.membus.badaddr_responder]
type=IsaFake
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
fake_mem=false
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
pio_addr=0
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
pio_size=8
ret_bad_addr=true
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=warn
pio=system.membus.default
[system.physmem]
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
type=DRAMCtrl
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
IDD0=0.075000
IDD02=0.000000
IDD2N=0.050000
IDD2N2=0.000000
IDD2P0=0.000000
IDD2P02=0.000000
IDD2P1=0.000000
IDD2P12=0.000000
IDD3N=0.057000
IDD3N2=0.000000
IDD3P0=0.000000
IDD3P02=0.000000
IDD3P1=0.000000
IDD3P12=0.000000
IDD4R=0.187000
IDD4R2=0.000000
IDD4W=0.165000
IDD4W2=0.000000
IDD5=0.220000
IDD52=0.000000
IDD6=0.000000
IDD62=0.000000
VDD=1.500000
VDD2=0.000000
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
activation_limit=4
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
addr_mapping=RoRaBaChCo
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
bank_groups_per_rank=0
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
banks_per_rank=8
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
burst_length=8
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
channels=1
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
conf_table_reported=true
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
device_bus_width=8
device_rowbuffer_size=1024
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
device_size=536870912
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
devices_per_rank=8
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
dll=true
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
in_addr_map=true
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
max_accesses_per_row=16
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
mem_sched_policy=frfcfs
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
min_writes_per_switch=16
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
null=false
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
page_policy=open_adaptive
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
range=2147483648:2415919103
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
ranks_per_channel=2
read_buffer_size=32
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
static_backend_latency=10000
static_frontend_latency=10000
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
tBURST=5000
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
tCCD_L=0
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
tCK=1250
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
tCL=13750
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
tCS=2500
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
tRAS=35000
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
tRCD=13750
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
tREFI=7800000
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
tRFC=260000
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
tRP=13750
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
tRRD=6000
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
tRRD_L=0
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
tRTP=7500
tRTW=2500
tWR=15000
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
tWTR=7500
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
tXAW=30000
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
tXP=0
tXPDLL=0
tXS=0
tXSDLL=0
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
port=system.membus.master[5]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
[system.realview]
type=RealView
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
intrctrl=system.intrctrl
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pci_cfg_base=805306368
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
pci_cfg_gen_offsets=false
pci_io_base=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
system=system
[system.realview.aaci_fake]
type=AmbaFake
amba_id=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
ignore_access=false
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio_addr=470024192
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
system=system
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio=system.iobus.master[18]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
ARM: Update stats for default inclusion of CF adapter.
2011-04-04 18:42:32 +02:00
[system.realview.cf_ctrl]
type=IdeController
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
BAR0=471465984
ARM: Update stats for default inclusion of CF adapter.
2011-04-04 18:42:32 +02:00
BAR0LegacyIO=true
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
BAR0Size=256
BAR1=471466240
ARM: Update stats for default inclusion of CF adapter.
2011-04-04 18:42:32 +02:00
BAR1LegacyIO=true
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
BAR1Size=4096
ARM: Update stats for default inclusion of CF adapter.
2011-04-04 18:42:32 +02:00
BAR2=1
BAR2LegacyIO=false
BAR2Size=8
BAR3=1
BAR3LegacyIO=false
BAR3Size=4
BAR4=1
BAR4LegacyIO=false
BAR4Size=16
BAR5=1
BAR5LegacyIO=false
BAR5Size=0
BIST=0
CacheLineSize=0
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
CapabilityPtr=0
ARM: Update stats for default inclusion of CF adapter.
2011-04-04 18:42:32 +02:00
CardbusCIS=0
ClassCode=1
Command=1
DeviceID=28945
ExpansionROM=0
HeaderType=0
InterruptLine=31
InterruptPin=1
LatencyTimer=0
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
LegacyIOBase=0
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
MSICAPMsgAddr=0
MSICAPMsgCtrl=0
MSICAPMsgData=0
MSICAPMsgUpperAddr=0
MSICAPNextCapability=0
MSICAPPendingBits=0
MSIXCAPBaseOffset=0
MSIXCAPCapId=0
MSIXCAPNextCapability=0
MSIXMsgCtrl=0
MSIXPbaOffset=0
MSIXTableOffset=0
ARM: Update stats for default inclusion of CF adapter.
2011-04-04 18:42:32 +02:00
MaximumLatency=0
MinimumGrant=0
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
PMCAPBaseOffset=0
PMCAPCapId=0
PMCAPCapabilities=0
PMCAPCtrlStatus=0
PMCAPNextCapability=0
PXCAPBaseOffset=0
PXCAPCapId=0
PXCAPCapabilities=0
PXCAPDevCap2=0
PXCAPDevCapabilities=0
PXCAPDevCtrl=0
PXCAPDevCtrl2=0
PXCAPDevStatus=0
PXCAPLinkCap=0
PXCAPLinkCtrl=0
PXCAPLinkStatus=0
PXCAPNextCapability=0
ARM: Update stats for default inclusion of CF adapter.
2011-04-04 18:42:32 +02:00
ProgIF=133
Revision=0
Status=640
SubClassCode=1
SubsystemID=0
SubsystemVendorID=0
VendorID=32902
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
ARM: Update stats for default inclusion of CF adapter.
2011-04-04 18:42:32 +02:00
config_latency=20000
ctrl_offset=2
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
disks=
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
io_shift=2
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
pci_bus=2
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pci_dev=0
ARM: Update stats for default inclusion of CF adapter.
2011-04-04 18:42:32 +02:00
pci_func=0
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=30000
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
platform=system.realview
system=system
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
config=system.iobus.master[9]
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
dma=system.iobus.slave[2]
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio=system.iobus.master[8]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
[system.realview.clcd]
type=Pl111
amba_id=1315089
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
enable_capture=true
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
gic=system.realview.gic
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
int_num=46
pio_addr=471793664
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
pio_latency=10000
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
pixel_clock=41667
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
system=system
vnc=system.vncserver
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
dma=system.iobus.slave[1]
pio=system.iobus.master[4]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
[system.realview.energy_ctrl]
type=EnergyCtrl
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
dvfs_handler=system.dvfs_handler
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio_addr=470286336
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
system=system
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio=system.iobus.master[22]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
[system.realview.ethernet]
type=IGbE
BAR0=0
BAR0LegacyIO=false
BAR0Size=131072
BAR1=0
BAR1LegacyIO=false
BAR1Size=0
BAR2=0
BAR2LegacyIO=false
BAR2Size=0
BAR3=0
BAR3LegacyIO=false
BAR3Size=0
BAR4=0
BAR4LegacyIO=false
BAR4Size=0
BAR5=0
BAR5LegacyIO=false
BAR5Size=0
BIST=0
CacheLineSize=0
CapabilityPtr=0
CardbusCIS=0
ClassCode=2
Command=0
DeviceID=4213
ExpansionROM=0
HeaderType=0
InterruptLine=1
InterruptPin=1
LatencyTimer=0
LegacyIOBase=0
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
MSICAPMsgAddr=0
MSICAPMsgCtrl=0
MSICAPMsgData=0
MSICAPMsgUpperAddr=0
MSICAPNextCapability=0
MSICAPPendingBits=0
MSIXCAPBaseOffset=0
MSIXCAPCapId=0
MSIXCAPNextCapability=0
MSIXMsgCtrl=0
MSIXPbaOffset=0
MSIXTableOffset=0
MaximumLatency=0
MinimumGrant=255
PMCAPBaseOffset=0
PMCAPCapId=0
PMCAPCapabilities=0
PMCAPCtrlStatus=0
PMCAPNextCapability=0
PXCAPBaseOffset=0
PXCAPCapId=0
PXCAPCapabilities=0
PXCAPDevCap2=0
PXCAPDevCapabilities=0
PXCAPDevCtrl=0
PXCAPDevCtrl2=0
PXCAPDevStatus=0
PXCAPLinkCap=0
PXCAPLinkCtrl=0
PXCAPLinkStatus=0
PXCAPNextCapability=0
ProgIF=0
Revision=0
Status=0
SubClassCode=0
SubsystemID=4104
SubsystemVendorID=32902
VendorID=32902
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
clk_domain=system.clk_domain
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
config_latency=20000
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
eventq_index=0
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
fetch_comp_delay=10000
fetch_delay=10000
hardware_address=00:90:00:00:00:01
pci_bus=0
pci_dev=0
pci_func=0
phy_epid=896
phy_pid=680
pio_latency=30000
platform=system.realview
rx_desc_cache_size=64
rx_fifo_size=393216
rx_write_delay=0
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system=system
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
tx_desc_cache_size=64
tx_fifo_size=393216
tx_read_delay=0
wb_comp_delay=10000
wb_delay=10000
config=system.iobus.master[26]
dma=system.iobus.slave[4]
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
pio=system.iobus.master[25]
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
[system.realview.generic_timer]
type=GenericTimer
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
gic=system.realview.gic
int_num=29
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
system=system
[system.realview.gic]
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
type=Pl390
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
cpu_addr=738205696
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
cpu_pio_delay=10000
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
dist_addr=738201600
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
dist_pio_delay=10000
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update ARM_FS stats for mp changes
2011-05-05 03:38:28 +02:00
int_latency=10000
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
it_lines=128
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
msix_addr=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
platform=system.realview
system=system
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
pio=system.membus.master[2]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
[system.realview.hdlcd]
type=HDLcd
amba_id=1314816
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
enable_capture=true
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
gic=system.realview.gic
int_num=117
pio_addr=721420288
pio_latency=10000
pixel_clock=7299
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
system=system
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
vnc=system.vncserver
dma=system.membus.slave[0]
pio=system.iobus.master[5]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
[system.realview.ide]
type=IdeController
BAR0=1
BAR0LegacyIO=false
BAR0Size=8
BAR1=1
BAR1LegacyIO=false
BAR1Size=4
BAR2=1
BAR2LegacyIO=false
BAR2Size=8
BAR3=1
BAR3LegacyIO=false
BAR3Size=4
BAR4=1
BAR4LegacyIO=false
BAR4Size=16
BAR5=1
BAR5LegacyIO=false
BAR5Size=0
BIST=0
CacheLineSize=0
CapabilityPtr=0
CardbusCIS=0
ClassCode=1
Command=0
DeviceID=28945
ExpansionROM=0
HeaderType=0
InterruptLine=2
InterruptPin=2
LatencyTimer=0
LegacyIOBase=0
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
MSICAPMsgAddr=0
MSICAPMsgCtrl=0
MSICAPMsgData=0
MSICAPMsgUpperAddr=0
MSICAPNextCapability=0
MSICAPPendingBits=0
MSIXCAPBaseOffset=0
MSIXCAPCapId=0
MSIXCAPNextCapability=0
MSIXMsgCtrl=0
MSIXPbaOffset=0
MSIXTableOffset=0
MaximumLatency=0
MinimumGrant=0
PMCAPBaseOffset=0
PMCAPCapId=0
PMCAPCapabilities=0
PMCAPCtrlStatus=0
PMCAPNextCapability=0
PXCAPBaseOffset=0
PXCAPCapId=0
PXCAPCapabilities=0
PXCAPDevCap2=0
PXCAPDevCapabilities=0
PXCAPDevCtrl=0
PXCAPDevCtrl2=0
PXCAPDevStatus=0
PXCAPLinkCap=0
PXCAPLinkCtrl=0
PXCAPLinkStatus=0
PXCAPNextCapability=0
ProgIF=133
Revision=0
Status=640
SubClassCode=1
SubsystemID=0
SubsystemVendorID=0
VendorID=32902
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
config_latency=20000
ctrl_offset=0
disks=system.cf0
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
io_shift=0
pci_bus=0
pci_dev=1
pci_func=0
pio_latency=30000
platform=system.realview
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
system=system
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
config=system.iobus.master[24]
dma=system.iobus.slave[3]
pio=system.iobus.master[23]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
[system.realview.kmi0]
type=Pl050
amba_id=1314896
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
gic=system.realview.gic
int_delay=1000000
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
int_num=44
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
is_mouse=false
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio_addr=470155264
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
system=system
vnc=system.vncserver
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio=system.iobus.master[6]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
[system.realview.kmi1]
type=Pl050
amba_id=1314896
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
gic=system.realview.gic
int_delay=1000000
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
int_num=45
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
is_mouse=true
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio_addr=470220800
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
system=system
vnc=system.vncserver
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio=system.iobus.master[7]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
[system.realview.l2x0_fake]
type=IsaFake
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
fake_mem=false
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio_addr=739246080
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
pio_size=4095
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio=system.iobus.master[12]
[system.realview.lan_fake]
type=IsaFake
clk_domain=system.clk_domain
eventq_index=0
fake_mem=false
pio_addr=436207616
pio_latency=100000
pio_size=65535
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[19]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
[system.realview.local_cpu_timer]
type=CpuLocalTimer
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
gic=system.realview.gic
int_num_timer=29
int_num_watchdog=30
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio_addr=738721792
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system=system
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio=system.membus.master[3]
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
[system.realview.mmc_fake]
type=AmbaFake
amba_id=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
ignore_access=false
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio_addr=470089728
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
system=system
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio=system.iobus.master[21]
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
[system.realview.nvmem]
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
type=SimpleMemory
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
bandwidth=73.000000
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
conf_table_reported=false
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
in_addr_map=true
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
latency=30000
latency_var=0
null=false
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
range=0:67108863
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
port=system.membus.master[1]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
[system.realview.pciconfig]
type=PciConfigAll
bus=0
clk_domain=system.clk_domain
eventq_index=0
pio_addr=0
pio_latency=30000
platform=system.realview
size=268435456
system=system
pio=system.iobus.default
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
[system.realview.realview_io]
type=RealViewCtrl
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
idreg=35979264
pio_addr=469827584
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
proc_id0=335544320
proc_id1=335544320
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
system=system
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
pio=system.iobus.master[1]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
ARM: Update stats for IT and conditional branch changes
2012-03-21 16:36:45 +01:00
[system.realview.rtc]
type=PL031
amba_id=3412017
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for IT and conditional branch changes
2012-03-21 16:36:45 +01:00
gic=system.realview.gic
int_delay=100000
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
int_num=36
pio_addr=471269376
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
system=system
ARM: Update stats for IT and conditional branch changes
2012-03-21 16:36:45 +01:00
time=Thu Jan 1 00:00:00 2009
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio=system.iobus.master[10]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
[system.realview.sp810_fake]
type=AmbaFake
amba_id=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
ignore_access=true
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio_addr=469893120
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
system=system
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio=system.iobus.master[16]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
[system.realview.timer0]
type=Sp804
amba_id=1316868
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
clock0=1000000
clock1=1000000
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
gic=system.realview.gic
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
int_num0=34
int_num1=34
pio_addr=470876160
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
system=system
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
pio=system.iobus.master[2]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
[system.realview.timer1]
type=Sp804
amba_id=1316868
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
clock0=1000000
clock1=1000000
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
gic=system.realview.gic
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
int_num0=35
int_num1=35
pio_addr=470941696
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
system=system
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
pio=system.iobus.master[3]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
[system.realview.uart]
type=Pl011
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
end_on_eot=false
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
gic=system.realview.gic
int_delay=100000
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
int_num=37
pio_addr=470351872
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
platform=system.realview
system=system
terminal=system.terminal
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
pio=system.iobus.master[0]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
[system.realview.uart1_fake]
type=AmbaFake
amba_id=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
ignore_access=false
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio_addr=470417408
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
system=system
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio=system.iobus.master[13]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
[system.realview.uart2_fake]
type=AmbaFake
amba_id=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
ignore_access=false
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio_addr=470482944
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
system=system
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio=system.iobus.master[14]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
[system.realview.uart3_fake]
type=AmbaFake
amba_id=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
ignore_access=false
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio_addr=470548480
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
system=system
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio=system.iobus.master[15]
[system.realview.usb_fake]
type=IsaFake
clk_domain=system.clk_domain
eventq_index=0
fake_mem=false
pio_addr=452984832
pio_latency=100000
pio_size=131071
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[20]
[system.realview.vgic]
type=VGic
clk_domain=system.clk_domain
eventq_index=0
gic=system.realview.gic
hv_addr=738213888
pio_delay=10000
platform=system.realview
ppint=25
system=system
vcpu_addr=738222080
pio=system.membus.master[4]
[system.realview.vram]
type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=false
eventq_index=0
in_addr_map=true
latency=30000
latency_var=0
null=false
range=402653184:436207615
port=system.iobus.master[11]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
[system.realview.watchdog_fake]
type=AmbaFake
amba_id=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
ignore_access=false
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio_addr=470745088
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
system=system
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio=system.iobus.master[17]
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
[system.terminal]
type=Terminal
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
intr_control=system.intrctrl
number=0
output=true
port=3456
[system.vncserver]
type=VncServer
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: Update stats for ARM init param changes.
2012-01-10 01:08:20 +01:00
frame_capture=false
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
number=0
port=5900
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.voltage_domain]
type=VoltageDomain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
voltage=1.000000
Reference in a new issue Copy permalink