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Author SHA1 Message Date
Korey Sewell
d8e0935af2 inorder: add insts to cpu event 
some events are going to need instruction data when they process, so just
include the instruction in the event construction
 2010-01-31 18:26:03 -05:00
Korey Sewell
e8312ab6f7 inorder: switch out buffer 
add buffer for instructions to switch out to in a pipeline stage
can't squash the instruction and remove the pipeline so we kind of need
to 'suspend' an instruction at the stage while the memory stall resolves
for the switch on cache miss model
 2010-01-31 18:25:48 -05:00
Korey Sewell
a892af7b26 inorder: dont allow early loads 
- loads were happening on same cycle as the address was generated which is slightly
unrealistic. Instead, force address generation to be on separate cycle from load
initiation
- also, mark the stages in a more traditional way (F-D-X-M-W)
 2010-01-31 18:25:27 -05:00
Korey Sewell
0e96798fe0 configs/inorder: add options for switch-on-miss to inorder cpu 2010-01-31 18:25:13 -05:00
Korey Sewell
7b3b362ba5 inorder: init internal debug cpu counters 
- cpuEventNum
- resReqCount
 2010-01-31 17:18:15 -05:00
Brad Beckmann
ab2f864af2 m5: Regression Tester Update 
This patch includes the necessary regression updates to test the new ruby
configuration system.  The patch includes support for multiple ruby protocols
and adds the ruby random tester.  The patch removes atomic mode test for
ruby since ruby does not support atomic mode acceses.  These tests can be
added back in when ruby supports atomic mode for real.

--HG--
rename : tests/quick/50.memtest/test.py => tests/quick/60.rubytest/test.py
 2010-01-29 20:29:40 -08:00
Brad Beckmann
ceae8383ff ruby: Replaced gems_common debug statements 
Replaced Ruby debug statements with M5 statements.
 2010-01-29 20:29:34 -08:00
Brad Beckmann
143d8ea698 ruby: removed last level cache support 
Removed the last level cache support and MOESI_hammer's dependency on it.
Replaces the LLC support with the more generic MachineType count.
 2010-01-29 20:29:34 -08:00
Brad Beckmann
90aab239a1 ruby: Added a Scons option to prevent HTML file creation 2010-01-29 20:29:33 -08:00
Brad Beckmann
1feae85017 ruby: Removed static members in RubyPort including hitcallback 
Removed static members in RubyPort and removed the ruby request unique id.
 2010-01-29 20:29:33 -08:00
Brad Beckmann
a579d3e43c ruby: Removed the old config interface 
Removed the old config interface from RubySystem and libruby.
 2010-01-29 20:29:33 -08:00
Brad Beckmann
e4218dd08f ruby: Re-enabled orion power models 
Removed the dummy power function implementations so that Orion can implement
them correctly.  Since Orion lacks modular design, this patch simply enables
scons to compile it.  There are no python configuration changes in this patch.
 2010-01-29 20:29:33 -08:00
Brad Beckmann
8dd45674ae ruby: Converted Garnet to M5 configuration 2010-01-29 20:29:32 -08:00
Steve Reinhardt
b544462505 Garnet: reorganize directory tree. 
Rename the ruby/network/garnet-foo directories to garnet/foo.
Move the common NetworkHeader.hh file from garnet-fixed-pipeline
up to the common garnet directory.
Fix up include paths.

--HG--
rename : src/mem/ruby/network/garnet-fixed-pipeline/NetworkHeader.hh => src/mem/ruby/network/garnet/NetworkHeader.hh
rename : src/mem/ruby/network/garnet-fixed-pipeline/CreditLink_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/CreditLink_d.hh
rename : src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
rename : src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh
rename : src/mem/ruby/network/garnet-fixed-pipeline/InputUnit_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.cc
rename : src/mem/ruby/network/garnet-fixed-pipeline/InputUnit_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh
rename : src/mem/ruby/network/garnet-fixed-pipeline/NetworkInterface_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
rename : src/mem/ruby/network/garnet-fixed-pipeline/NetworkInterface_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.hh
rename : src/mem/ruby/network/garnet-fixed-pipeline/NetworkLink_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc
rename : src/mem/ruby/network/garnet-fixed-pipeline/NetworkLink_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh
rename : src/mem/ruby/network/garnet-fixed-pipeline/OutVcState_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/OutVcState_d.cc
rename : src/mem/ruby/network/garnet-fixed-pipeline/OutVcState_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/OutVcState_d.hh
rename : src/mem/ruby/network/garnet-fixed-pipeline/OutputUnit_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.cc
rename : src/mem/ruby/network/garnet-fixed-pipeline/OutputUnit_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh
rename : src/mem/ruby/network/garnet-fixed-pipeline/Router_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc
rename : src/mem/ruby/network/garnet-fixed-pipeline/Router_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh
rename : src/mem/ruby/network/garnet-fixed-pipeline/RoutingUnit_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/RoutingUnit_d.cc
rename : src/mem/ruby/network/garnet-fixed-pipeline/RoutingUnit_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/RoutingUnit_d.hh
rename : src/mem/ruby/network/garnet-fixed-pipeline/SConscript => src/mem/ruby/network/garnet/fixed-pipeline/SConscript
rename : src/mem/ruby/network/garnet-fixed-pipeline/SWallocator_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc
rename : src/mem/ruby/network/garnet-fixed-pipeline/SWallocator_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.hh
rename : src/mem/ruby/network/garnet-fixed-pipeline/Switch_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.cc
rename : src/mem/ruby/network/garnet-fixed-pipeline/Switch_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.hh
rename : src/mem/ruby/network/garnet-fixed-pipeline/VCallocator_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/VCallocator_d.cc
rename : src/mem/ruby/network/garnet-fixed-pipeline/VCallocator_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/VCallocator_d.hh
rename : src/mem/ruby/network/garnet-fixed-pipeline/VirtualChannel_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.cc
rename : src/mem/ruby/network/garnet-fixed-pipeline/VirtualChannel_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.hh
rename : src/mem/ruby/network/garnet-fixed-pipeline/flitBuffer_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.cc
rename : src/mem/ruby/network/garnet-fixed-pipeline/flitBuffer_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.hh
rename : src/mem/ruby/network/garnet-fixed-pipeline/flit_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/flit_d.cc
rename : src/mem/ruby/network/garnet-fixed-pipeline/flit_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/flit_d.hh
rename : src/mem/ruby/network/garnet-flexible-pipeline/FlexibleConsumer.hh => src/mem/ruby/network/garnet/flexible-pipeline/FlexibleConsumer.hh
rename : src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.cc => src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc
rename : src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.hh => src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh
rename : src/mem/ruby/network/garnet-flexible-pipeline/InVcState.cc => src/mem/ruby/network/garnet/flexible-pipeline/InVcState.cc
rename : src/mem/ruby/network/garnet-flexible-pipeline/InVcState.hh => src/mem/ruby/network/garnet/flexible-pipeline/InVcState.hh
rename : src/mem/ruby/network/garnet-flexible-pipeline/NetworkConfig.hh => src/mem/ruby/network/garnet/flexible-pipeline/NetworkConfig.hh
rename : src/mem/ruby/network/garnet-flexible-pipeline/NetworkInterface.cc => src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
rename : src/mem/ruby/network/garnet-flexible-pipeline/NetworkInterface.hh => src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.hh
rename : src/mem/ruby/network/garnet-flexible-pipeline/NetworkLink.cc => src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.cc
rename : src/mem/ruby/network/garnet-flexible-pipeline/NetworkLink.hh => src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.hh
rename : src/mem/ruby/network/garnet-flexible-pipeline/OutVcState.cc => src/mem/ruby/network/garnet/flexible-pipeline/OutVcState.cc
rename : src/mem/ruby/network/garnet-flexible-pipeline/OutVcState.hh => src/mem/ruby/network/garnet/flexible-pipeline/OutVcState.hh
rename : src/mem/ruby/network/garnet-flexible-pipeline/Router.cc => src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
rename : src/mem/ruby/network/garnet-flexible-pipeline/Router.hh => src/mem/ruby/network/garnet/flexible-pipeline/Router.hh
rename : src/mem/ruby/network/garnet-flexible-pipeline/SConscript => src/mem/ruby/network/garnet/flexible-pipeline/SConscript
rename : src/mem/ruby/network/garnet-flexible-pipeline/VCarbiter.cc => src/mem/ruby/network/garnet/flexible-pipeline/VCarbiter.cc
rename : src/mem/ruby/network/garnet-flexible-pipeline/VCarbiter.hh => src/mem/ruby/network/garnet/flexible-pipeline/VCarbiter.hh
rename : src/mem/ruby/network/garnet-flexible-pipeline/flit.cc => src/mem/ruby/network/garnet/flexible-pipeline/flit.cc
rename : src/mem/ruby/network/garnet-flexible-pipeline/flit.hh => src/mem/ruby/network/garnet/flexible-pipeline/flit.hh
rename : src/mem/ruby/network/garnet-flexible-pipeline/flitBuffer.cc => src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.cc
rename : src/mem/ruby/network/garnet-flexible-pipeline/flitBuffer.hh => src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.hh
rename : src/mem/ruby/network/garnet-flexible-pipeline/netconfig.defaults => src/mem/ruby/network/garnet/flexible-pipeline/netconfig.defaults
 2010-01-29 20:29:30 -08:00
Brad Beckmann
6c867f8263 ruby: Added a mesh topology 2010-01-29 20:29:27 -08:00
Brad Beckmann
faa76fc248 ruby: MESI_CMP_directory updated to the new config system 2010-01-29 20:29:27 -08:00
Brad Beckmann
3e286d825d ruby: Sorted the file includes to maintain consistency 2010-01-29 20:29:26 -08:00
Brad Beckmann
5fb1f5c72b ruby: Renamed the MESI directory sm file 
Renamed the MESI directory file to be consistent with all other protocols.

--HG--
rename : src/mem/protocol/MESI_CMP_directory-mem.sm => src/mem/protocol/MESI_CMP_directory-dir.sm
 2010-01-29 20:29:26 -08:00
Brad Beckmann
79f354466e ruby: Removed the GPL header in MESI_CMP_directory-msg 
I'm not sure how this got past our initial ruby code import, but this obviously
needed to be removed.
 2010-01-29 20:29:26 -08:00
Brad Beckmann
31fcf09a68 ruby: MOESI_CMP_directory updated to the new config system 2010-01-29 20:29:26 -08:00
Brad Beckmann
1c4405ad5e ruby: Added atomic support to MOESI_CMP_token 2010-01-29 20:29:25 -08:00
Brad Beckmann
042d5b87a4 ruby: fixed memory fetch bug for persistent requests 2010-01-29 20:29:25 -08:00
Brad Beckmann
d77a9df3c1 ruby: MOESI_CMP_token updates to use the new config system 2010-01-29 20:29:25 -08:00
Brad Beckmann
d42152742b ruby: Allows boolean and string defaults for StateMachine parameters 2010-01-29 20:29:24 -08:00
Brad Beckmann
b3d195153e ruby: MI_example updates to use the new config system 2010-01-29 20:29:24 -08:00
Brad Beckmann
134cc3d48d ruby: convert to M5 MemorySize 
Converted both ruby caches and directory memory to use the M5 MemorySize python
type.
 2010-01-29 20:29:23 -08:00
Brad Beckmann
3a835c7cbb ruby: Added Cache and MemCntrl profiler calls 2010-01-29 20:29:23 -08:00
Brad Beckmann
47502163b7 ruby: added data print to ruby request 2010-01-29 20:29:23 -08:00
Brad Beckmann
66279fac3f ruby: Added atomic support to MOESI_hammer 2010-01-29 20:29:23 -08:00
Brad Beckmann
45230a4f6b ruby: added the GEMS ruby tester 2010-01-29 20:29:23 -08:00
Brad Beckmann
4eb3bfc31b ruby: fixed MOESI_hammer data writebacks to the directory 2010-01-29 20:29:22 -08:00
Brad Beckmann
f88faa6c11 ruby: cleaned up ruby profilers 
Cleaned up the ruby profilers by moving the memory controller profiling code
out of the main profiler object and into a separate object similar to the
current CacheProfiler.  Both the CacheProfiler and MemCntrlProfiler are
specific to a particular Ruby object, CacheMemory and MemoryControl
respectively.  Therefore, these profilers should not be SimObjects and
created by the python configuration system, but instead private objects.  This
simplifies the creation of these profilers.
 2010-01-29 20:29:22 -08:00
Brad Beckmann
cfe41d0a1b ruby: Removed RubySystem::getNumberOfSequencers 
removed the static function RubySystem::getNumberOfSequencers and replaced
it with a python config variable
 2010-01-29 20:29:21 -08:00
Brad Beckmann
1907e39fd2 ruby: added ruby stats print 
Moved the previous rubymem stats print feature to ruby System so that ruby
stats are printed on simulation exit.
 2010-01-29 20:29:21 -08:00
Brad Beckmann
020716cab3 ruby: fixed Set.cc bug to allow zero sized sets 
This is necessary for example when no dma sequencers are necessary in the
simulated system.
 2010-01-29 20:29:21 -08:00
Brad Beckmann
ce2d13195b ruby: FS support using the new configuration system 2010-01-29 20:29:21 -08:00
Brad Beckmann
dc758641c9 ruby: reorganized ruby python configuration 
Reorganized ruby python configuration so that protocol and ruby memory system
configuration code can be shared by multiple front-end configuration files
(i.e. memory tester, full system, and hopefully the regression tester).  This
code works for memory tester, but have not tested fs mode.
 2010-01-29 20:29:20 -08:00
Brad Beckmann
e735ca7c77 ruby: Removed out_link_vec from Consumer 
Removed the out_line_vec data structure from the Consumer.  I'm not sure
what this did before, but currently it has no usefulness.
 2010-01-29 20:29:20 -08:00
Brad Beckmann
0f6535dba1 ruby: Convered ruby tracing support usage of sequencer 
Modified ruby's tracing support to no longer rely on the RubySystem map
to convert a sequencer string name to a sequencer pointer.  As a
temporary solution, the code uses the sim_object find function.
Eventually, we should develop a better fix.
 2010-01-29 20:29:20 -08:00
Brad Beckmann
2c9ca672df ruby: Memory Controller Profiler with new config system 
This patch includes a rather substantial change to the memory controller
profiler in order to work with the new configuration system.  Most
noteably, the mem_cntrl_profiler no longer uses a string map, but instead
a vector.  Eventually this support should be removed from the main
profiler and go into a separate object.  Each memory controller should have
a pointer to that new mem_cntrl profile object.
 2010-01-29 20:29:20 -08:00
Brad Beckmann
2a0555470c ruby: Converted MOESI_hammer dma cntrl to new config system 2010-01-29 20:29:19 -08:00
Brad Beckmann
3b290a35ac ruby: Added the cache profiler to the new config system 2010-01-29 20:29:19 -08:00
Brad Beckmann
4e5f4b5074 ruby: Converted the sequencer deadlock event to m5 eventq 2010-01-29 20:29:19 -08:00
Brad Beckmann
e15abd17f9 ruby: Wrapped ruby events into m5 events 
Wrapped ruby events using the m5 event object.  Removed the prio_heap
from ruby's event queue and instead schedule ruby events on the m5 event
queue.
 2010-01-29 20:29:19 -08:00
Brad Beckmann
63a60cc81e ruby: Removed the tech_nm variable from RubySystem 2010-01-29 20:29:19 -08:00
Brad Beckmann
12daaed84a ruby: Added clock to ruby system 
As a first step to migrate ruby to the M5 eventqueue, added a clock
variable to the ruby system.
 2010-01-29 20:29:19 -08:00
Brad Beckmann
ed81489954 ruby: Ruby changes required to use the python config system 
This patch includes the necessary changes to connect ruby objects using
the python configuration system.  Mainly it consists of removing
unnecessary ruby object pointers and connecting the necessary object
pointers using the generated param objects.  This patch includes the
slicc changes necessary to connect generated ruby objects together using
the python configuraiton system.
 2010-01-29 20:29:19 -08:00
Brad Beckmann
42bebab779 ruby: connects sm queues to the network 2010-01-29 20:29:18 -08:00
Steve Reinhardt
a8ea70dac6 ruby: Calculate system total memory capacity in Python 
rather than in RubySystem object.
 2010-01-29 20:29:18 -08:00
Steve Reinhardt
0b54f1db8e ruby: Add support for generating topologies in Python. 2010-01-29 20:29:17 -08:00
Steve Reinhardt
184cf4db5b scons: ignore blank lines in .slicc files 2010-01-29 20:29:17 -08:00
Steve Reinhardt
c6f1d959be ruby: Make SLICC-generated objects SimObjects. 
Also add SLICC support for state-machine parameter defaults
(passed through to Python as SimObject Param defaults).
 2010-01-29 20:29:17 -08:00
Steve Reinhardt
98c94cfe3c ruby: Convert most Ruby objects to M5 SimObjects. 
The necessary companion conversion of Ruby objects generated by SLICC
are converted to M5 SimObjects in the following patch, so this patch
alone does not compile.
Conversion of Garnet network models is also handled in a separate
patch; that code is temporarily disabled from compiling to allow
testing of interim code.
 2010-01-29 20:29:17 -08:00
Steve Reinhardt
b43994ba45 ruby: get rid of obsolete, unused CustomTopology class. 2010-01-29 20:29:14 -08:00
Brad Beckmann
7f03dce012 ruby: fix out_port declaration 2010-01-29 20:29:14 -08:00
Brad Beckmann
43e4f59e4f ruby: Added message type check to OutPortDeclAST.py 
Though OutPort's message type is not used to generate code, this fix checks
that the programmer's intent is correct.  Eventually, we may want to
remove the message type from the OutPort declaration statement.
 2010-01-29 20:29:13 -08:00
Nathan Binkert
5b90934dd2 build: need to include cstdio 2010-01-23 14:02:03 -08:00
Nathan Binkert
8a3fbbd8d9 compile: compile on 32 bit hardware 2009-11-05 17:21:26 -08:00
Nathan Binkert
52ccfde2cd isa_parser: allow negative integer literals 2009-11-05 17:21:25 -08:00
Derek Hower
589218168c Automated merge with ssh://hg@m5sim.org/m5 2010-01-22 17:23:21 -06:00
Lisa Hsu
d6da172517 util: do checkpoint aggregation more cleanly, fix last changeset. 
1) Move alpha-specific code out of page_table.cc:serialize().
2) Begin serializing M5_pid and unserializing it, but adding an function to do optional paramIn so that old checkpoints don't need to be fixed up.
3) Fix up alpha startup code so that the unserialized M5_pid value is properly written to DTB_IPR_ASN.
4) Fix the memory unserialize that I forgot somehow in the last changeset.
5) Add in an agg_se.py to handle aggregated checkpoints. --bench foo-bar plus positional arguments foo bar are the only changes in usage from se.py.
Note this aggregation stuff has only been tested for Alpha and nothing else, though it should take a very minimal amount of work to get it to work with another ISA.
 2010-01-19 22:03:44 -08:00
Derek Hower
07ea0891f1 ruby: new atomics implementation 
This patch changes the way that Ruby handles atomic RMW instructions. This implementation, unlike the prior one, is protocol independent. It works by locking an address from the sequencer immediately after the read portion of an RMW completes. When that address is locked, the coherence controller will only satisfy requests coming from one port (e.g., the mandatory queue) and will ignore all others. After the write portion completed, the line is unlocked. This should also work with multi-line atomics, as long as the blocks are always acquired in the same order.
 2010-01-19 17:11:36 -06:00
Derek Hower
279f179bab merge 2010-01-19 15:48:12 -06:00
Lisa Hsu
4a40ac71f8 util: make a generic checkpoint aggregator that can aggregate different cpts into one multi-programmed cpt. Make minor changes to serialization/unserialization to get it to work properly. Note that checkpoints were made with a comment at the beginning with // - this must be changed to ## to work properly with the python config parser in the aggregator. 2010-01-18 14:30:31 -08:00
Lisa Hsu
8b4e8690b7 cache: make tags->insertBlock() and tags->accessBlock() context aware so that the cache can make context-specific decisions within their various tag policy implementations. 2010-01-12 10:53:02 -08:00
Lisa Hsu
9f63548478 since totalInstructions() is impl'ed by all the cpus, make it an abstract base class. 2010-01-12 10:22:46 -08:00
Lisa Hsu
daebe18e89 faults: i think these fault invocations should be panic and not fatal. it definitely made implementing a trace cpu easier this way. 2010-01-12 10:17:19 -08:00
Matt DeVuyst
18dc80e07b MIPS: Beef up process initialization. 2009-12-31 15:30:51 -05:00
Gabe Black
ecaa7070e6 MIPS: Implement the SE mode version of rdhwr. 2009-12-31 15:30:51 -05:00
Gabe Black
c70f3c93af MIPS: Fix decoding of the rdhwr instruction. 2009-12-31 15:30:51 -05:00
Gabe Black
134937b594 MIPS: Implement the set_thread_area system call. 2009-12-31 15:30:50 -05:00
Gabe Black
d3ed32b989 MIPS: Create an artificial control register to hold the thread pointer. 
In Linux, the set_thread_area system call stores the address of the thread
local storage area into a field of the current thread_info structure. Later,
to access that value, the program uses the rdhwr instruction to read a
"hardware register" with index 29. The 64 bit MIPS manual, volume II, says
that index 29 is reserved for a future ABI extension and should cause a
"Reserved Instruction Exception". In Linux (and potentially other ISAs) that
exception is trapped and emulated to return the value stored by
set_thread_area as if that were actually stored by a physical register.

The tp_value address (as named in the Linux kernel) is ironically stored as a
control register so that it goes with a particular ThreadContext. Syscall
emulation will use that to emulate storing to the OS's thread info structure,
and rdhwr will emulate faulting and returning that value from software by
returning the value itself, as if it was in hardware. In other words, we fake
faking the register in SE mode. In an FS mode implementation it should
work as specified in the manual.
 2009-12-31 15:30:50 -05:00
Gabe Black
cc07dcf026 MIPS: Extract CPU pointer from the thread context in scheduleCP0 setMiscReg. 
The MIPS ISA object expects to be constructed with a CPU pointer it uses to
look at other thread contexts and allow them to be manipulated with control
registers. Unfortunately, that differs from all the other ISA classes and
would complicate their implementation.

This change makes the event constructor use a CPU pointer pulled out of the
thread context passed to setMiscReg instead.
 2009-12-31 15:30:50 -05:00
Gabe Black
1261f1d8db MIPS: Add missing syscall slots. 
These are all after the existing ones, suggesting they were added after the
original list was created.
 2009-12-21 14:59:40 -08:00
Soumyaroop Roy
1bd0f772f1 Alpha: Implement MVI and remaining BWX instructions. 2009-12-20 15:03:23 -06:00
Gabe Black
3e1cda5080 X86: Add a latency that describes how long an interrupt takes to propagate through the IO APIC. 2009-12-19 01:50:06 -08:00
Gabe Black
c7ca1d3c8a X86: Add a common named flag for signed media operations. 2009-12-19 01:48:31 -08:00
Gabe Black
2554511533 X86: Create a common flag with a name to indicate high multiplies. 2009-12-19 01:48:07 -08:00
Gabe Black
e474079ddc X86: Create a common flag with a name to indicate scalar media instructions. 2009-12-19 01:47:30 -08:00
Derek Hower
5aa104e072 ruby: cleaned up ruby-lang configuration 2009-12-04 13:12:40 -06:00
Brad Beckmann
5d8a669539 Resurrection of the CMP token protocol to GEM5 2009-11-18 16:34:33 -08:00
Brad Beckmann
dcac2ec24c ruby: removed the chip pointer from MessageBuffer 
The Chip object no longer exists and thus is removed from the MessageBuffer
constructor.
 2009-11-18 16:34:32 -08:00
Brad Beckmann
c9764b1ff1 ruby: added error message to isinstance check 
Added error message when a symbol is not an instance of a particular expected
type.
 2009-11-18 16:34:32 -08:00
Brad Beckmann
20f872ed2a ruby: Added boolean to State Machine parameters 
* * *
ruby: Removed primitive .hh includes
 2009-11-18 16:34:32 -08:00
Brad Beckmann
8011e80725 ruby: The persistent table files from GEMS 
These files are need by the MOESI_CMP_token protocol.
 2009-11-18 16:34:32 -08:00
Brad Beckmann
cef3c56163 ruby: MOESI hammer support for DMA reads and writes 2009-11-18 16:34:32 -08:00
Brad Beckmann
dbb2c111cc ruby: Added a memory controller feature to MOESI hammer 2009-11-18 16:34:32 -08:00
Brad Beckmann
bc12b8432d ruby: Hammer ruby configuration support 2009-11-18 16:34:32 -08:00
Brad Beckmann
877be2009c ruby: Changes necessary to get the hammer protocol to work in GEM5 2009-11-18 16:34:32 -08:00
Brad Beckmann
b0973035b4 ruby: added the original hammer protocols from old ruby 2009-11-18 16:34:31 -08:00
Brad Beckmann
2783a7b9ad ruby: returns the number of LLC needed for broadcast 
Added feature to CacheMemory to return the number of last level caches.
This count is need for broadcast protocols such as MOESI_hammer.
 2009-11-18 16:34:31 -08:00
Brad Beckmann
7b8fcecf11 ruby: cache configuration fix to use bytes 
Changed cache size to be in bytes instead of kb so that testers can use very
small caches and increase the chance of writeback races.
 2009-11-18 16:34:31 -08:00
Brad Beckmann
99338a7460 ruby: fix CacheMemory destructor 2009-11-18 16:33:35 -08:00
Brad Beckmann
7ab484624f ruby: split CacheMemory.hh into a .hh and a .cc 2009-11-18 16:33:35 -08:00
Brad Beckmann
8b0f970084 ruby: Added default names to message buffers 
Added default names to message buffers created by the simple network.
 2009-11-18 13:55:58 -08:00
Brad Beckmann
ed54ecf1c8 ruby: slicc method error fix 
Added error message when a method call is not supported by an object.
 2009-11-18 13:55:58 -08:00
Brad Beckmann
994169327a ruby: slicc action error fix 
Small fix to the State Machine error message when duplicate actions are defined.
 2009-11-18 13:55:58 -08:00
Brad Beckmann
cc2db929cb ruby: slicc state machine error fixes 
Added error messages when:
- a state does not exist in a machine's list of known states.
- an event does not exist in a machine
- the actions of a certain machine have not been declared
 2009-11-18 13:55:58 -08:00
Brad Beckmann
e84881b7a3 ruby: Removed unused action z_stall 2009-11-18 13:55:58 -08:00
Brad Beckmann
b5d2052fa0 m5: Fixed bug in atomic cpu destructor 2009-11-18 13:55:58 -08:00
Brad Beckmann
faf1d97f24 ruby: fixed dma mi example to work with multiple dma ports 2009-11-18 13:55:58 -08:00
Brad Beckmann
f54790977b m5: removed master and slave deletions. 
The unresolved destructor call caused a seg fault when called.
 2009-11-18 13:55:58 -08:00
Brad Beckmann
4d731a522d m5: fixed destructor to deschedule the tickEvent and event 2009-11-18 13:55:58 -08:00
Brad Beckmann
93f0069dd5 ruby: getPort function fix 
Fixed RubyMemory::getPort function to not pass in a -1 for the idx parameter
 2009-11-18 13:55:58 -08:00
Brad Beckmann
204d1776ca ruby: Fixed Directory memory destructor 2009-11-18 13:55:58 -08:00
Brad Beckmann
6e1dc2546c m5: Added isValidSrc and isValidDest calls to packet.hh 2009-11-18 13:55:58 -08:00
Brad Beckmann
90d6e2652f ruby: included ruby config parameter ports per core 
Slightly improved the major hack need to correctly assign the number of ports
per core.  CPUs have two ports: icache + dcache.  MemTester has one port.
 2009-11-18 13:55:58 -08:00
Brad Beckmann
dce53610c3 ruby: Added error check for openning the ruby config file 2009-11-18 13:55:58 -08:00
Brad Beckmann
3cf24f9716 ruby: Support for merging ALPHA_FS and ruby 
Connects M5 cpu and dma ports directly to ruby sequencers and dma
sequencers.  Rubymem also includes a pio port so that pio requests
and be forwarded to a special pio bus connecting to device pio
ports.
 2009-11-18 13:55:58 -08:00
Brad Beckmann
d7a4f665ed ruby: Added more info to bridge error message 2009-11-18 13:55:57 -08:00
Brad Beckmann
17e14efa7e ruby: Ruby 64-bit address output fixes. 2009-11-18 13:55:57 -08:00
Brad Beckmann
b7cc66af31 ruby: Ruby destruction fix. 2009-11-18 13:55:57 -08:00
Brad Beckmann
5492f71755 ruby: Ruby debug print fixes. 2009-11-18 13:55:57 -08:00
Derek Hower
9ef5e72917 ruby: added sequencer stats to track what requests are waiting on 2009-11-18 11:55:30 -06:00
Derek Hower
d11dd6ed2c ruby: turned off randomization by default, turned on memory controller random arbitrate 2009-11-18 11:53:43 -06:00
Ali Saidi
422f0d9f10 ARM: Begin implementing CP15 2009-11-17 18:02:09 -06:00
Ali Saidi
0916c376a9 ARM: Differentiate between LDM exception return and LDM user regs. 2009-11-17 18:02:08 -06:00
Ali Saidi
1470dae8e9 ARM: Boilerplate full-system code. 
--HG--
rename : src/arch/sparc/interrupts.hh => src/arch/arm/interrupts.hh
rename : src/arch/sparc/kernel_stats.hh => src/arch/arm/kernel_stats.hh
rename : src/arch/sparc/stacktrace.cc => src/arch/arm/stacktrace.cc
rename : src/arch/sparc/system.cc => src/arch/arm/system.cc
rename : src/arch/sparc/system.hh => src/arch/arm/system.hh
rename : src/dev/sparc/T1000.py => src/dev/arm/Versatile.py
rename : src/dev/sparc/t1000.cc => src/dev/arm/versatile.cc
rename : src/dev/sparc/t1000.hh => src/dev/arm/versatile.hh
 2009-11-17 18:02:08 -06:00
Ali Saidi
171e7f7b24 imported patch isa_fixes2.diff 2009-11-16 11:37:03 -06:00
Gabe Black
9127ee5ac8 ARM: Make the exception return form of ldm restore CPSR. 2009-11-15 00:23:14 -08:00
Gabe Black
903fb8c73d ARM: Create a new type of load uop that restores spsr into cpsr. 2009-11-15 00:15:42 -08:00
Gabe Black
b41725f723 ARM: Check in the actual change from the last commit. 
The last commit was somehow empty. This was what was supposed to go in it.
 2009-11-14 21:03:10 -08:00
Gabe Black
c4042985d7 ARM: Fix up the implmentation of the msr instruction. 2009-11-14 19:22:30 -08:00
Gabe Black
e2ab64543b ARM: Define a mask to differentiate purely CPSR bits from CondCodes bits. 2009-11-14 19:22:30 -08:00
Gabe Black
425ebf6bd7 ARM: Add a bitfield to indicate if an immediate should be used. 2009-11-14 19:22:30 -08:00
Gabe Black
e543f16247 ARM: Write some functions to write to the CPSR and SPSR for instructions. 2009-11-14 19:22:30 -08:00
Gabe Black
812e390693 ARM: Fix up the implmentation of the mrs instruction. 2009-11-14 19:22:29 -08:00
Gabe Black
1df0025e28 ARM: More accurately describe the effects of using the control operands. 2009-11-14 19:22:29 -08:00
Gabe Black
50b9149c75 ARM: Hook up the moded versions of the SPSR. 
These registers can be accessed directly, or through MISCREG_SPSR which will
act as whichever SPSR is appropriate for the current mode.
 2009-11-14 19:22:29 -08:00
Ali Saidi
4e9ce1805e SE: Fix SE mode OS X compilation. 2009-11-14 11:49:01 -06:00
Ali Saidi
48bc573f5f ARM: Move around decoder to properly decode CP15 2009-11-14 11:25:00 -06:00
Derek Hower
2f5839832e ruby: added -A option to TwoLevel_SplitL1UnifiedL2 to set the L1 cache size 2009-11-13 09:45:23 -06:00
Derek Hower
f7f475a6f4 ruby: gave ALIASED_REQUEST priority over BUFFER_FULL in sequencer 2009-11-13 09:44:51 -06:00
Derek Hower
2ee04d6587 ruby: reduce the memory usage of ruby by making memory vector page based 2009-11-13 09:43:39 -06:00
Derek Hower
ceb8fde914 ruby: cache memory bugfix 2009-11-13 09:42:47 -06:00
Vince Weaver
8f6744c19c X86: add ULL to 1's being shifted in 64-bit values 
Some of the micro-ops weren't casting 1 to ULL before shifting,
which can cause problems.  On the perl makerand input this
caused some values to be negative that shouldn't have been.

The casts are done as ULL(1) instead of 1ULL to match others
in the m5 code base.
 2009-11-11 17:49:09 -05:00
Gabe Black
5524af83ef ARM: Fix some bugs in the ISA desc and fill out some instructions. 2009-11-10 23:44:05 -08:00
Gabe Black
850eb54a7c Merge with the head. 2009-11-10 21:12:53 -08:00
Gabe Black
b8120f6c38 Mem: Eliminate the NO_FAULT request flag. 2009-11-10 21:10:18 -08:00
Gabe Black
2e28da5583 ARM: Implement fault classes. 
Implement some fault classes using the curriously recurring template pattern,
similar to SPARCs.
 2009-11-10 20:34:38 -08:00
Gabe Black
4779020e13 ARM: Fix the integer register indexes. 
The PC indexes in the various register sets was defined in the section for
unaliased registers which was throwing off the indexing. This moves those
where they belong. Also, to make detecting accesses to the PC easier and
because it's in the same place in all modes, the intRegForceUser function
now passes it through as index 15.
 2009-11-10 20:19:55 -08:00
Vince Weaver
53e27c0277 X86: Fix bugs in movd implementation. 
Unfortunately my implementation of the movd instruction had two bugs.

In one case, when moving a 32-bit value into an xmm register, the
lower half of the xmm register was not zero extended.

The other case is that xmm was used instead of xmmlm as the source
for a register move.  My test case didn't notice this at first
as it moved xmm0 to eax, which both have the same register
number.
 2009-11-10 11:29:30 -05:00
Vince Weaver
e81cc233a6 X86: Remove double-cast in Cvtf2i micro-op 
This double cast led to rounding errors which caused
some benchmarks to get the wrong values, most notably lucas
which failed spectacularly due to CVTTSD2SI returning an
off-by-one value.  equake was also broken.
 2009-11-10 11:18:23 -05:00
Vince Weaver
7da221ca82 syscall: missing initializer in getcwd call 
This one case was missed during the update to stack-based arguments.
Without this fix, m5 will crash during a gwtcwd call, at least
with X86.
 2009-11-09 10:02:55 -05:00
Gabe Black
bbbfdee2ed X86: Don't panic on faults on prefetches in SE mode. 2009-11-08 22:49:58 -08:00
Gabe Black
44e912c6bd X86: Explain what really didn't work with unmapped addresses in SE mode. 2009-11-08 22:49:57 -08:00
Gabe Black
53086dfefe X86: Make x86 use PREFETCH instead of PF_EXCLUSIVE. 2009-11-08 22:49:57 -08:00
Nathan Binkert
b1a1f9aec8 automerge 2009-11-08 20:15:54 -08:00
Steve Reinhardt
374d337693 scons: deal with generated .py files properly 2009-11-08 17:35:49 -08:00
Gabe Black
8a4af3668d ARM: Support forcing load/store multiple to use user registers. 2009-11-08 15:49:03 -08:00