src/arch/sparc/isa/decoder.isa:
Fix up the casa and casxa instructions.
src/arch/sparc/isa/formats/formats.isa:
This is handled in loadstore.isa now
src/arch/sparc/isa/formats/mem/basicmem.isa:
src/arch/sparc/isa/formats/mem/blockmem.isa:
Renamed doSplitExecute to doDualSplitExecute. This differentiates between the version that does both a register and immediate version, and one that just does a register version.
src/arch/sparc/isa/formats/mem/mem.isa:
The cas format is handled in loadstore.isa as well now.
src/arch/sparc/isa/formats/mem/util.isa:
Reorganized things a bit to better support cas
--HG--
extra : convert_revision : 12411e89e763287e52f9825bf7a417b263c1037f
src/arch/sparc/isa/formats/priv.isa:
Fix the priv format so that it uses isa_parser operands rather than accessing the registers directly in checkCode. Also, the expressions needed to be negated.
src/arch/sparc/isa/operands.isa:
Added an Hpstate operand, and adjusted the numbering.
--HG--
extra : convert_revision : 4a70862df061aa9e1b9eab125c4c2fc839ac3b5a
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
Added a function to do normal SPARC trap processing, and implemented the spill and fill faults for SE
src/arch/sparc/process.cc:
src/arch/sparc/process.hh:
Added fill and spill handlers which are stuffed into the processes address space. The location of these handlers are stored in fillStart and spillStart.
--HG--
extra : convert_revision : 59adb96570cce86f373fbc2c3e4c05abe1742d3b
not necessarily 100% there yet.
src/mem/cache/cache_impl.hh:
Generate response packet on failed store conditional.
src/mem/packet.hh:
Clear packet flags when reinitializing.
(SATISFIED in particular is one we don't want to leave set.)
--HG--
extra : convert_revision : 29207c8a09afcbce43f41c480ad0c1b21d47454f
src/sim/faults.cc:
Fix fault message.
src/kern/tru64/tru64.hh:
Add DPRINTF to see where new thread stacks are allocated.
src/arch/alpha/faults.cc:
Add print statement so we know what the faulting address is in SE mode.
--HG--
extra : convert_revision : 6eb2b513c339496a0d013b7e914953a0a066c12d
running SCons, make it into a sticky option that can be
overridden at build time, and set it up before the interpreter
is started. Also, fix the code that turns sticky options into
config/*.hh so that it works with types other than bool.
--HG--
extra : convert_revision : 602398b35d4da4e813f78865678ed348fdea7270
Fix fixPacket assert function.
Stop timing port from forwarding the request if a response was found in its queue on a read.
src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
src/python/m5/objects/MemTest.py:
Add parameter to configure what percentage of mem accesses are functional
src/mem/cache/base_cache.cc:
src/mem/cache/cache_impl.hh:
Use fix Packet function
src/mem/packet.cc:
Fix an assert that was checking the wrong thing
src/mem/tport.cc:
Properly detect if we need to do the access to the functional device
--HG--
extra : convert_revision : 447cc1a9a65ddd2a41e937fb09dc0e7c74e9c75e
I need to move over to using the fixPacket function so I don't have to make the same changes everywhere.
Still a functional access bug someplace I need to track down in timing mode.
src/mem/cache/base_cache.cc:
src/mem/cache/cache_impl.hh:
Fix corner case on assertion
tests/configs/memtest.py:
Updated memtester with uncacheable addresses and functional accesses
--HG--
extra : convert_revision : e6fa851621700ff9227b83cc5cac20af4fc8444f
src/cpu/memtest/memtest.cc:
Fix memtest to do functional accesses
src/mem/cache/cache_impl.hh:
Fix cache to handle functional accesses properly based on memtester changes
Still need to fix functional accesses in timing mode now that the memtester can test it.
--HG--
extra : convert_revision : a6dbca4dc23763ca13560fbf5d41a23ddf021113
?? doesn't compile in warn statements
Should have been false, where I had a true.
src/cpu/o3/lsq_impl.hh:
Apparently you can't have ?? in a warn statement (Something about trigraphs)
src/mem/cache/cache_impl.hh:
Forgot to signal atomic mode in snoopProbe
--HG--
extra : convert_revision : c75cb76e193e852284564993440c8ea39e6de426
Now to try L2 caches in FS.
src/mem/cache/base_cache.hh:
Fix uni-coherence for atomic accesses in coherence protocol access to port
src/mem/cache/cache_impl.hh:
Properly handle uni-coherence
src/mem/cache/coherence/simple_coherence.hh:
Properly forward invalidates (not done for MSI+ protocols (assumed top level for now)
src/mem/cache/coherence/uni_coherence.cc:
src/mem/cache/coherence/uni_coherence.hh:
Properly forward invalidates in atomic/timing uni-coherence
--HG--
extra : convert_revision : f0f11315e8e7f32c19d92287f6f9c27b079c96f7
src/mem/cache/cache_impl.hh:
Get the read data from the highest level of cache on a functional access
--HG--
extra : convert_revision : 7437ac46fb40f3ea3b42197a1aa8aec62af60181
that tracing gets turned on as the very first thing
in the selected cycle (tick).
--HG--
extra : convert_revision : c08f749ca42782af1b48e5aa5f0860bf7076bd3c
configs/example/fs.py:
Add MOESI protocol to caches (uni coherence not quite working w/FS yet).
--HG--
extra : convert_revision : 7bef7d9c5b24bf7241cc810df692408837b06b86
src/cpu/exetrace.cc:
Fixed up to deal with microcode, and to make floating point register numbers correlate to the numbers used in SPARC.
util/statetrace/arch/tracechild_sparc.cc:
util/statetrace/arch/tracechild_sparc.hh:
Make floating point register numbers correlate to the numbers used in SPARC.
--HG--
extra : convert_revision : 878897292f696092453cf61d6eac2d1c407ca13b
src/python/m5/SimObject.py:
how did i not commit this already? the other way doesn't seem to work.
--HG--
extra : convert_revision : 55737d3d10742a1913a376d1febbc5809f2fab8f
configs/example/fs.py:
Add flag for MP server systems.
src/python/m5/objects/AlphaConsole.py:
src/python/m5/objects/IntrControl.py:
Change CPU from 'any' to 'cpu[0]' to work better with MP sytems.
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-timing-dual.py:
Don't need to set console & intrcontrol cpu
params anymore (default is fixed now).
--HG--
extra : convert_revision : 9417b12b1b395ff7d6a9f2894e4123923c754daf
Still a bug in atomic uni-coherence in FS.
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
Make CPU models handle coherence requests
src/mem/cache/base_cache.cc:
Properly signal coherence CSHRs
src/mem/cache/coherence/uni_coherence.cc:
Only deallocate once
--HG--
extra : convert_revision : c4533de421c371c5532ee505e3ecd451511f5c99
Still need to rework upgrades into this system, but works for now.
src/mem/cache/base_cache.cc:
Re order code to be more readable
src/mem/cache/base_cache.hh:
Be sure to delete the copy on a bus block
src/mem/cache/cache_impl.hh:
Be sure to remove the copy on a writeback success
src/mem/cache/miss/mshr_queue.cc:
Demorgans to make it easier to understand
src/mem/tport.cc:
Delete writebacks
--HG--
extra : convert_revision : 9519fb37b46ead781d340de29bb342a322a6a92e
Still need to fix upgrades to use this path
src/mem/cache/base_cache.cc:
Copy the pkt to the MSHR before issuing the sendTiming where it may be changed/consumed
src/mem/cache/cache_impl.hh:
Use copy of packet, because sendTiming may have changed the pkt
Also, delete the copy when the time comes
--HG--
extra : convert_revision : 635cde6b4f08d010affde310c46b1caf50fbe424
src/arch/sparc/isa/formats/blockmem.isa:
Several small and medium bug fixes.
src/cpu/simple/base.cc:
Fixed a few compiler errors and made sure the next micro pc is set to 1 to prevent the first microop from executing twice. Also fixed a fetching bug.
src/cpu/thread_state.cc:
Made sure the microPC and nextMicroPC are initialized properly.
--HG--
extra : convert_revision : a0fc8aa18d1ade916f17c557181a793c6108a8af
