Commit graph

439 commits

Author SHA1 Message Date
Korey Sewell bfdd2f379b remove unnecessary debug messages I added
--HG--
extra : convert_revision : 5c23218fd1b899fa7fe42701f7cb2f6033f7a583
2007-11-14 06:18:58 -05:00
Korey Sewell 2692590049 Add in files from merge-bare-iron, get them compiling in FS and SE mode
--HG--
extra : convert_revision : d4e19afda897bc3797868b40469ce2ec7ec7d251
2007-11-13 16:58:16 -05:00
Ali Saidi c8123cef1b Cache: Fix for OS X 10.5 compiling.
--HG--
extra : convert_revision : ba3c33ed524367280eefc096177d767168ac2cf6
2007-11-04 18:57:36 -05:00
Ali Saidi 333ac6cc32 DRAM: Make latency parameters be Param.Latency instead of ints.
--HG--
extra : convert_revision : 553b86cc4653da089d7aa0045a3f3bdcabf6c4d8
2007-11-01 17:30:50 -04:00
Steve Reinhardt 90f42bf3ad Merge in bus DPRINTF changes.
--HG--
extra : convert_revision : 3bbd7c0745b31bb2a628b604ab1627cd9c61643c
2007-10-31 00:39:16 -07:00
Ali Saidi 538fae951b Traceflags: Add SCons function to created a traceflag instead of having one file with them all.
--HG--
extra : convert_revision : 427f6bd8f050861ace3bc0d354a1afa5fc8319e6
2007-10-31 01:21:54 -04:00
Gabe Black fddfa71658 TLB: Fix serialization issues with the tlb entries and make the page table store the process, not the system.
--HG--
extra : convert_revision : 2421af11f62f60fb48faeee6bddadac2987df0e8
2007-10-25 19:04:44 -07:00
Ali Saidi 0711f4f17a SE: Fix page table and system serialization, don't reinit process if this is a checkpoint restore.
--HG--
extra : convert_revision : 03dcf3c088e57b7abab60efe700d947117888306
2007-10-25 20:13:35 -04:00
Steve Reinhardt 76c4c5fabc mem: clean up bus/cache DPRINTFs a bit
Not so much noise on failed sends, and more complete
info when grepping a trace using an address.

--HG--
extra : convert_revision : 05a8261c9452072ca08b906200c6322b33e2b9f1
2007-09-16 16:46:38 -07:00
Ali Saidi bf7c01d43d Bus: Fix drain code; old method could return 1 in atomic mode and never call de->process().
--HG--
extra : convert_revision : 35990e5eaf93f7a95a0ec72e9f92034a042def3e
2007-09-05 17:12:41 -04:00
Miles Kaufmann 54cc0053f0 params: Deprecate old-style constructors; update most SimObject constructors.
SimObjects not yet updated:
- Process and subclasses
- BaseCPU and subclasses

The SimObject(const std::string &name) constructor was removed.  Subclasses
that still rely on that behavior must call the parent initializer as
  : SimObject(makeParams(name))

--HG--
extra : convert_revision : d6faddde76e7c3361ebdbd0a7b372a40941c12ed
2007-08-30 15:16:59 -04:00
Gabe Black 7227ab5f22 Merge with head
--HG--
extra : convert_revision : cc73b9aaf73e9dacf52f3350fa591e67ca4ccee6
2007-08-26 21:45:40 -07:00
Gabe Black 9b49a78cfd Address translation: Make the page table more flexible.
The page table now stores actual page table entries. It is still a templated
class here, but this will be corrected in the near future.

--HG--
extra : convert_revision : 804dcc6320414c2b3ab76a74a15295bd24e1d13d
2007-08-26 20:33:57 -07:00
Ali Saidi 02353a60ee MemorySystem: Fix the use of ?: to produce correct results.
--HG--
extra : convert_revision : 31aad7170b35556a4c984f4ebc013137d55d85eb
2007-08-12 19:43:54 -04:00
Ali Saidi 06a9f58c68 DMA: Add IOCache and fix bus bridge to optionally only send requests one
way so a cache can handle partial block requests for i/o devices.

--HG--
extra : convert_revision : a68b5ae826731bc87ed93eb7ef326a2393053964
2007-08-10 16:14:01 -04:00
Ali Saidi 5c38668ed6 Bus: Only call end() on an stl object once in a loop
--HG--
extra : convert_revision : 238dcd6da7577b533e52ada2107591c4e9168ebd
2007-08-10 16:14:01 -04:00
Vincentius Robby 3d40cba8d4 Port, StaticInst: Revert unnecessary changes.
--HG--
extra : convert_revision : e6ef262bbbc5ad53498e55caac1897e6cc2a61e6
2007-08-08 14:54:02 -04:00
Vincentius Robby 13d10e844c alpha: Make the TLB cache to actually work.
Improve MRU checking for StaticInst, Bus, TLB

--HG--
extra : convert_revision : 9116b5655cd2986aeb4205438aad4a0f5a440006
2007-08-08 14:18:09 -04:00
Vincentius Robby 1db9e1fb8f port: Implement cache for port interfaces and ranges
--HG--
extra : convert_revision : d7cbec7c277fb8f4d8846203caae36ce629602d5
2007-08-04 16:05:55 -04:00
Steve Reinhardt 62aa1d7f55 cache: get rid of obsolete params from python.
--HG--
extra : convert_revision : cd40e0ef938ef6da1cccedf7be01c3ac5b4883fb
2007-08-03 03:51:13 -04:00
Steve Reinhardt 2f93db6f95 memory system: fix functional access bug.
Make sure not to keep processing functional accesses
after they've been responded to.
Also use checkFunctional() return value instead of checking
packet command field where possible, mostly just for consistency.

--HG--
extra : convert_revision : 29fc76bc18731bd93a4ed05a281297827028ef75
2007-07-29 20:17:03 -07:00
Steve Reinhardt 4a7d0c4b79 bus: take out response prioritization (timing was messed up).
Also make express snoops not occupy bus (since they're magic).

--HG--
extra : convert_revision : 75aa5211a59380026d1e3f122778425e48e2edcd
2007-07-29 13:24:48 -07:00
Steve Reinhardt 8705b0799b packet: get rid of unused intersect() function.
--HG--
extra : convert_revision : f0a2947ccc49e0d18bc17a59371fa396d9ebd6c0
2007-07-27 12:46:55 -07:00
Steve Reinhardt 0cbcb715e0 cache/memtest: fixes for functional accesses.
--HG--
extra : convert_revision : 688ba4d882cad2c96cf44c9e46999f74266e02ee
2007-07-27 12:46:45 -07:00
Steve Reinhardt 01c9d34a0b cache: Get rid of unused variable.
--HG--
extra : convert_revision : 394adc12fbd7ea10280a1b8d6bc3cb15ee019f27
2007-07-27 03:51:15 -04:00
Nathan Binkert f0fef8f850 Merge python and x86 changes with cache branch
--HG--
extra : convert_revision : e06a950964286604274fba81dcca362d75847233
2007-07-26 23:15:49 -07:00
Steve Reinhardt 6b73ff43ff Have owner respond to UpgradeReq to avoid race.
--HG--
extra : convert_revision : 30916fca6978c73d8a14558f2d7288c1eab54ad4
2007-07-26 17:04:17 -07:00
Steve Reinhardt c3bf59dcb9 Add downward express snoops for invalidations.
--HG--
extra : convert_revision : 4916fa9721d727d8416ad8c07df3a8171d02b2b4
2007-07-26 17:04:17 -07:00
Steve Reinhardt f1b5c8fb57 Continue snooping after a writeback is encountered.
--HG--
extra : convert_revision : 8411338a6c0fdd7072dd32bdffacdace62d5de90
2007-07-26 17:04:16 -07:00
Steve Reinhardt 58250b8e5f bus: Fix default port handling.
--HG--
extra : convert_revision : 121b6e31cddff17c51fc4f3df20e7e2bde87d04f
2007-07-26 17:04:12 -07:00
Steve Reinhardt c1097d06f7 Can't block on memInhibit packets
(now that bus no longer filters them for us).

--HG--
extra : convert_revision : 34e7eaf5ee1e739f5557a2d417e569ed2ceb14b3
2007-07-25 07:47:37 -07:00
Steve Reinhardt de52eebd3b Integrate snoop loop functions into their respective call sites.
Also some additional cleanup of Bus::recvTiming().

--HG--
extra : convert_revision : 156814119f75d04c2e954aec2d7ed6fdc186c26f
2007-07-24 22:37:41 -07:00
Steve Reinhardt d094f9cf27 Don't delete request at target... requester still needs it.
--HG--
extra : convert_revision : 76377ca2e4d7ea70d1d54d325a63ce710e260b93
2007-07-24 22:36:10 -07:00
Steve Reinhardt 1f9ea6e122 A couple more minor bug fixes for multilevel coherence.
--HG--
extra : convert_revision : 370f9e34911157765be6fd49e826fa1af589b466
2007-07-23 22:28:40 -07:00
Nathan Binkert abc76f20cb Major changes to how SimObjects are created and initialized. Almost all
creation and initialization now happens in python.  Parameter objects
are generated and initialized by python.  The .ini file is now solely for
debugging purposes and is not used in construction of the objects in any
way.

--HG--
extra : convert_revision : 7e722873e417cb3d696f2e34c35ff488b7bff4ed
2007-07-23 21:51:38 -07:00
Steve Reinhardt 82e2a35576 Replace lowerMSHRPending flag with more robust scheme
based on following Packet senderState links.

--HG--
extra : convert_revision : 9027d59bd7242aa0e4275bf94d8b1fb27bd59d79
2007-07-22 21:43:38 -07:00
Steve Reinhardt 1c2d5f5e64 Replace DeferredSnoop flag with LowerMSHRPending flag.
Turns out DeferredSnoop isn't quite the right bit of info
we needed... see new comment in cache_impl.hh.

--HG--
extra : convert_revision : a38de8c1677a37acafb743b7074ef88b21d3b7be
2007-07-22 08:09:24 -07:00
Steve Reinhardt 1edd143b68 A few minor non-debug compilation issues.
--HG--
extra : convert_revision : d59a5cad6187a2229dddd1a48282ebd2923d1d8d
2007-07-22 03:07:26 -04:00
Steve Reinhardt 92ce2b5974 Deal with invalidations intersecting outstanding upgrades.
If the invalidation beats the upgrade at a lower level
then the upgrade must be converted to a read exclusive
"in the field".
Restructure target list & deferred target list to
factor out some common code.

--HG--
extra : convert_revision : 7bab4482dd6c48efdb619610f0d3778c60ff777a
2007-07-21 18:18:42 -07:00
Steve Reinhardt 9117860094 Several more fixes for multi-level timing coherence.
- Add "deferred snoop" flag to Packet so upper-level caches
  can distinguish whether lower-level cache request was
  in-service or not at the time of the original snoop.
- Revamp response handling to properly handle deferred snoops
  on non-cache-fill requests (i.e. upgrades).
- Make sure forwarded writebacks are kept in write buffer at
  lower-level caches so they get snooped properly.

--HG--
extra : convert_revision : 17f8a3772a1ae31a16991a53f8225ddf54d31fc9
2007-07-21 13:45:17 -07:00
Steve Reinhardt a67a0025b3 Make sure responses never get blocked.
--HG--
extra : convert_revision : 29f359d743994a94dc403aa0621ba72cd137d1a1
2007-07-17 08:15:23 -07:00
Steve Reinhardt a25f3ac67f Forward cache-to-cache responses through other caches.
--HG--
extra : convert_revision : 5b6a02255bccd98b00949703cf4ba4b221553cea
2007-07-17 06:33:28 -07:00
Steve Reinhardt ff13827ccb Assert that an mshr has a target in getTarget().
--HG--
extra : convert_revision : 08091670fc319876012ed139fcd2584c364a980c
2007-07-17 06:23:11 -07:00
Steve Reinhardt 884807a68a Fix up a bunch of multilevel coherence issues.
Atomic mode seems to work.  Timing is closer but not there yet.

--HG--
extra : convert_revision : 0dea5c3d4b973d009e9d4a4c21b9cad15961d56f
2007-07-15 20:11:06 -07:00
Steve Reinhardt f790f34fe3 Make Bus::findPort() a little more useful.
Move check for loops outside, since half the call sites
end up working around it anyway.  Return integer port ID
instead of port object pointer.

--HG--
extra : convert_revision : 4c31fe9930f4d1aa4919e764efb7c50d43792ea3
2007-07-15 20:09:03 -07:00
Steve Reinhardt 15a51d0cae Add CacheRepl trace flag and move a couple DPRINTFs to it.
--HG--
extra : convert_revision : 31724d19ebdf2cdc2a2bafff83d17845b3a0b183
2007-07-14 13:28:52 -07:00
Steve Reinhardt abd194df5c Move a couple of DPRINTFs from Cache to CachePort.
--HG--
extra : convert_revision : 55a0d26660aeb8f63b41897d53e6b2d1f0a163be
2007-07-14 13:16:58 -07:00
Steve Reinhardt 3b4ff75939 Fix bug in copying packet with static data pointer.
--HG--
extra : convert_revision : 2fcf99f050d73e007433c1db2475f2893c5961a0
2007-07-14 13:14:53 -07:00
Steve Reinhardt a51e16dc89 Merge of DPRINTF fixes from head.
--HG--
extra : convert_revision : f99a33b2df6a6c5592856d17d00e73ee83267442
2007-07-14 12:09:37 -07:00
Steve Reinhardt 7cd6c7ee05 Fix & tweak DPRINTFs for tracediff w/new cache code.
Note that we should *not* print pointer values in DPRINTFs as
these needlessly clutter tracediff output.

--HG--
extra : convert_revision : 25a448f1b3ac8d453a717a104ad6dc0112fb30bb
2007-07-14 11:48:30 -07:00
Steve Reinhardt 4738649e32 Delete packets when we're done with them.
--HG--
extra : convert_revision : b8894d26e1ca7a6c9b736500accdaa53bfb09558
2007-07-03 00:40:31 -04:00
Steve Reinhardt 4b68652c87 Couple more minor bug fixes for FS timing mode.
src/cpu/simple/timing.cc:
    Fix another SC problem.
src/mem/cache/cache_impl.hh:
    Forgot to call makeTimingResponse() on uncached timing responses.

--HG--
extra : convert_revision : 5a5a58ca2053e4e8de2133205bfd37de15eb4209
2007-07-02 13:57:45 -07:00
Steve Reinhardt e9c04dad60 Fix a couple LL/SC bugs that only affected timing mode.
src/cpu/simple/timing.cc:
    Fix swap/stq_c command bug.
src/mem/packet.cc:
    Fix incorrect LoadLockedReq command response field.

--HG--
extra : convert_revision : 7a4523be900bc2c9b1bdf2d372ce55f89ae58ae5
2007-07-02 09:26:36 -07:00
Steve Reinhardt ffd697e149 bus.cc:
Fix atomic timing issue.

src/mem/bus.cc:
    Fix atomic timing issue.

--HG--
extra : convert_revision : a22ff80cd75f83c785b0604c2a4fde2e2e9f71ef
2007-07-02 01:02:35 -07:00
Steve Reinhardt 5e59739416 Don't propagate snoops across bridges. Wouldn't work anyway.
--HG--
extra : convert_revision : af29fc7d0c134f5e89dd2e814c819151350fcb38
2007-06-30 18:03:17 -07:00
Steve Reinhardt 07f091d6ed Get rid of remaining traces of obsolete CoherenceProtocol object.
--HG--
extra : convert_revision : c5555b00bef1b304a84886188ad2c0dcb4d7c5b9
2007-06-30 17:59:45 -07:00
Steve Reinhardt d10a843723 Get rid of obsolete fixPacket() functions.
Handled by Packet::checkFunctional() now.

--HG--
extra : convert_revision : 63642254e2789c80a369ac269f317ec054ffe3c0
2007-06-30 17:51:29 -07:00
Steve Reinhardt ee54ad318a Event descriptions should not end in "event"
(they function as adjectives not nouns)

--HG--
extra : convert_revision : 6506474ff3356ae8c80ed276c3608d8a4680bfdb
2007-06-30 17:45:58 -07:00
Steve Reinhardt f0c4dd7920 Factor out a little more common code.
--HG--
extra : convert_revision : 626255a91679d534030c91bcdb4fc1bed36ceb9b
2007-06-30 13:56:25 -07:00
Steve Reinhardt 6babda7123 Fix up a few statistics problems.
Stats pretty much line up with old code, except:
- bug in old code included L1 latency in L2 miss time, making it too high
- UniCoherence did cache-to-cache transfers even from non-owner caches,
so occasionally the icache would get a block from the dcache not the L2
- L2 can now receive ReadExReq from L1 since L1s have coherence

--HG--
extra : convert_revision : 5052c1a1767b5a662f30a88f16012165a73b791c
2007-06-30 13:34:16 -07:00
Steve Reinhardt 6ab53415ef Get rid of Packet result field. Error responses are
now encoded in cmd field.

--HG--
extra : convert_revision : d67819b7e3ee4b9a5bf08541104de0a89485e90b
2007-06-30 10:16:18 -07:00
Steve Reinhardt 9117c94f9c Get rid of coherence protocol object.
--HG--
extra : convert_revision : 4ff144342dca23af9a12a2169ca318a002654b42
2007-06-27 20:54:13 -07:00
Steve Reinhardt c4903e0882 Revamp replacement-of-upgrade handling.
--HG--
extra : convert_revision : 9bc09d8ae6d50e6dfbb4ab21514612f9aa102a2e
2007-06-26 23:30:30 -07:00
Steve Reinhardt 1b20df5607 Handle deferred snoops better.
--HG--
extra : convert_revision : 703da6128832eb0d5cfed7724e5105f4b3fe4f90
2007-06-26 22:23:10 -07:00
Steve Reinhardt 69ff6d9163 cache_impl.hh:
Change target overflow from assertion to warning.

src/mem/cache/cache_impl.hh:
    Change target overflow from assertion to warning.

--HG--
extra : convert_revision : ceca990ed916bbf96dedd4836c40df522803f173
2007-06-26 18:01:22 -04:00
Steve Reinhardt 7dacbcf492 Handle replacement of block with pending upgrade.
src/mem/cache/tags/lru.cc:
    Add some replacement DPRINTFs

--HG--
extra : convert_revision : 7993ec24d6af7e7774d04ce36f20e3f43f887fd9
2007-06-26 14:53:15 -07:00
Steve Reinhardt f697e959a1 Couple minor bug fixes...
src/mem/cache/cache_impl.hh:
    Handle grants with no packet.
src/mem/cache/miss/mshr.cc:
    Fix MSHR snoop hit handling.

--HG--
extra : convert_revision : f365283afddaa07cb9e050b2981ad6a898c14451
2007-06-25 22:23:29 -07:00
Steve Reinhardt 529f12a531 Get rid of requestCauses. Use timestamped queue to make
sure we don't re-request bus prematurely.  Use callback to
avoid calling sendRetry() recursively within recvTiming.

--HG--
extra : convert_revision : a907a2781b4b00aa8eb1ea7147afc81d6b424140
2007-06-25 06:47:05 -07:00
Steve Reinhardt 47bce8ef78 Better handling of deferred targets.
--HG--
extra : convert_revision : 0fbc28c32c1eeb3dd672df14c1d53bd516f81d0f
2007-06-24 17:32:31 -07:00
Steve Reinhardt 57ff2604e5 Minor fix plus new assertion to catch similar bugs.
src/cpu/memtest/memtest.cc:
    Need to set packet source field so that response from cache
    doesn't run into assertion failure when copying source to dest.
src/mem/packet.hh:
    Copy source field when copying packets.
    Assert that source is valid before copying it to dest
    when turning packets around.

--HG--
extra : convert_revision : 09e3cfda424aa89fe170e21e955b295746832bf8
2007-06-23 13:24:33 -07:00
Steve Reinhardt bdd5fd20fb Fixes to hitLatency, blocking, buffer allocation.
Single-cpu timing mode seems to work now.

--HG--
extra : convert_revision : 720f6172df18a1c941e5bd0e8fdfbd686c13c7ad
2007-06-22 09:24:07 -07:00
Steve Reinhardt eff122797b Merge vm1.(none):/home/stever/bk/newmem-head
into  vm1.(none):/home/stever/bk/newmem-cache2

--HG--
extra : convert_revision : 9002940097a166c8442ae1adf41b974227968920
2007-06-21 12:03:22 -07:00
Steve Reinhardt 83af0fdcf5 Getting closer...
configs/example/memtest.py:
    Add progress interval option.
src/base/traceflags.py:
    Add MemTest flag.
src/cpu/memtest/memtest.cc:
    Clean up tracing.
src/cpu/memtest/memtest.hh:
    Get rid of unused code.

--HG--
extra : convert_revision : 92bd8241a6c90bfb6d908e5a5132cbdb500cbb87
2007-06-21 11:59:17 -07:00
Ali Saidi 5195500cdf Use FastAlloc for Packet, Request, CoherenceState, and SenderState so we don't spend so much time calling malloc()
--HG--
extra : convert_revision : a946564eee46ed7d2aed41c32d488ca7f036c32f
2007-06-21 13:50:35 -04:00
Vincentius Robby 4a7bc06553 Minor error.
--HG--
extra : convert_revision : 514032e21c8861f20fcbcae7204e132088cc7dbc
2007-06-20 15:04:36 -04:00
Vincentius Robby d540dde5b4 Removed "adding instead of dividing" trick.
Caused slowdown in performance instead of speeding up.

src/cpu/base.cc:
    Removed "adding instead of dividing" trick.
src/mem/bus.cc:
    Fixed spelling in comments.
    Removed "adding instead of dividing" trick.

--HG--
extra : convert_revision : 65a736f4f09a64e737dc7aeee53b117976330488
2007-06-20 14:54:17 -04:00
Nathan Binkert b47737dde7 Make sure all parameters have default values if they're
supposed to and make sure parameters have the right type.
Also make sure that any object that should be an intermediate
type has the right options set.

--HG--
extra : convert_revision : d56910628d9a067699827adbc0a26ab629d11e93
2007-06-20 08:14:11 -07:00
Steve Reinhardt d69a763833 Merge vm1.(none):/home/stever/bk/newmem-head
into  vm1.(none):/home/stever/bk/newmem-cache2

configs/example/memtest.py:
    Hand merge redundant changes.

--HG--
extra : convert_revision : a2e36be254bf052024f37bcb23b5209f367d37e1
2007-06-17 17:30:24 -07:00
Steve Reinhardt 35cf19d441 More major reorg of cache. Seems to work for atomic mode now,
timing mode still broken.

configs/example/memtest.py:
    Revamp options.
src/cpu/memtest/memtest.cc:
    No need for memory initialization.
    No need to make atomic response... memory system should do that now.
src/cpu/memtest/memtest.hh:
    MemTest really doesn't want to snoop.
src/mem/bridge.cc:
    checkFunctional() cleanup.
src/mem/bus.cc:
src/mem/bus.hh:
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache.cc:
src/mem/cache/cache.hh:
src/mem/cache/cache_blk.hh:
src/mem/cache/cache_builder.cc:
src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/coherence_protocol.cc:
src/mem/cache/coherence/coherence_protocol.hh:
src/mem/cache/coherence/simple_coherence.hh:
src/mem/cache/miss/SConscript:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr.hh:
src/mem/cache/miss/mshr_queue.cc:
src/mem/cache/miss/mshr_queue.hh:
src/mem/cache/prefetch/base_prefetcher.cc:
src/mem/cache/tags/fa_lru.cc:
src/mem/cache/tags/fa_lru.hh:
src/mem/cache/tags/iic.cc:
src/mem/cache/tags/iic.hh:
src/mem/cache/tags/lru.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/split.cc:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_lifo.cc:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.cc:
src/mem/cache/tags/split_lru.hh:
src/mem/packet.cc:
src/mem/packet.hh:
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/tport.cc:
    More major reorg.  Seems to work for atomic mode now,
    timing mode still broken.

--HG--
extra : convert_revision : 7e70dfc4a752393b911880ff028271433855ae87
2007-06-17 17:27:53 -07:00
Nathan Binkert fc4ab050b4 Add a startup function that will fast forward to the right clock edge
using a divide in order to not loop forever after resuming from a checkpoint

--HG--
extra : convert_revision : 4bbc70b1be4e5c4ed99d4f88418ab620d5ce475a
2007-06-09 23:01:47 -07:00
Nathan Binkert e9936a6250 More realistic parameters
--HG--
extra : convert_revision : aaa4ea2b7c97df3d6b731e9252984b45715e9d6f
2007-06-09 22:43:08 -07:00
Ali Saidi 85986e9dff Clean up some of vincent's code and commit it
Makes page table cache scheme actually work

src/mem/page_table.cc:
src/mem/page_table.hh:
    fix caching scheme to actually work and improve performance

--HG--
extra : convert_revision : 443a8d8acbee540b26affcfdfbf107b8e735d1bd
2007-06-05 01:03:35 -04:00
Steve Reinhardt a9b7c558fd Merge vm1.(none):/home/stever/bk/newmem-head
into  vm1.(none):/home/stever/bk/newmem-cache2

--HG--
extra : convert_revision : 26921dad179699b7868768361143aaa8d790b8fc
2007-05-29 22:59:20 -07:00
Steve Reinhardt 4e65d2678d tport.cc:
Oops... forgot to update call site after changing
function argument semantics.

src/mem/tport.cc:
    Oops... forgot to update call site after changing
    function argument semantics.

--HG--
extra : convert_revision : 9234b991dc678f062d268ace73c71b3d13dd17dc
2007-05-30 01:53:28 -04:00
Steve Reinhardt 94c19ad37d Merge vm1.(none):/home/stever/bk/newmem-head
into  vm1.(none):/home/stever/bk/newmem-cache2

--HG--
extra : convert_revision : 72c6f2ce7e9e2b46e59711a2c3cfe770c243018e
2007-05-29 22:25:57 -07:00
Steve Reinhardt 365e4ac374 A little more cleanup & refactoring of SimpleTimingPort.
Make it a better base class for cache ports.

--HG--
extra : convert_revision : 37d6de11545a68c1a7d11ce33fe5971c51434ee4
2007-05-29 22:23:41 -07:00
Steve Reinhardt 05915ed6f7 Merge vm1.(none):/home/stever/bk/newmem-head
into  vm1.(none):/home/stever/bk/newmem-cache2

--HG--
extra : convert_revision : 6f462916cb0eb309b6799e94fbf07629abb50eba
2007-05-28 08:13:40 -07:00
Steve Reinhardt 41f6cbce9a Restructure SimpleTimingPort a bit:
- factor out checkFunctional() code so it can be
called from derived classes
- use EventWrapper for sendEvent, move event handling
code from event to port where it belongs
- make sendEvent a pointer so derived classes can
override it
- replace std::pair with new class for readability

--HG--
extra : convert_revision : 5709de2daacfb751a440144ecaab5f9fc02e6b7a
2007-05-28 08:11:43 -07:00
Steve Reinhardt 04ac944920 Reformat comments to meet line length restriction.
--HG--
extra : convert_revision : 24c00ec4904d9fb4d6e39521e0ff8b8f60d60f6a
2007-05-28 08:04:33 -07:00
Steve Reinhardt 075f4b108a Merge vm1.(none):/home/stever/bk/newmem-head
into  vm1.(none):/home/stever/bk/newmem-cache2

--HG--
extra : convert_revision : fba7efd444e1ca9738385dd4662a33feab357e79
2007-05-27 21:34:37 -07:00
Nathan Binkert 35147170f9 Move SimObject python files alongside the C++ and fix
the SConscript files so that only the objects that are
actually available in a given build are compiled in.
Remove a bunch of files that aren't used anymore.

--HG--
rename : src/python/m5/objects/AlphaTLB.py => src/arch/alpha/AlphaTLB.py
rename : src/python/m5/objects/SparcTLB.py => src/arch/sparc/SparcTLB.py
rename : src/python/m5/objects/BaseCPU.py => src/cpu/BaseCPU.py
rename : src/python/m5/objects/FuncUnit.py => src/cpu/FuncUnit.py
rename : src/python/m5/objects/IntrControl.py => src/cpu/IntrControl.py
rename : src/python/m5/objects/MemTest.py => src/cpu/memtest/MemTest.py
rename : src/python/m5/objects/FUPool.py => src/cpu/o3/FUPool.py
rename : src/python/m5/objects/FuncUnitConfig.py => src/cpu/o3/FuncUnitConfig.py
rename : src/python/m5/objects/O3CPU.py => src/cpu/o3/O3CPU.py
rename : src/python/m5/objects/OzoneCPU.py => src/cpu/ozone/OzoneCPU.py
rename : src/python/m5/objects/SimpleOzoneCPU.py => src/cpu/ozone/SimpleOzoneCPU.py
rename : src/python/m5/objects/BadDevice.py => src/dev/BadDevice.py
rename : src/python/m5/objects/Device.py => src/dev/Device.py
rename : src/python/m5/objects/DiskImage.py => src/dev/DiskImage.py
rename : src/python/m5/objects/Ethernet.py => src/dev/Ethernet.py
rename : src/python/m5/objects/Ide.py => src/dev/Ide.py
rename : src/python/m5/objects/Pci.py => src/dev/Pci.py
rename : src/python/m5/objects/Platform.py => src/dev/Platform.py
rename : src/python/m5/objects/SimConsole.py => src/dev/SimConsole.py
rename : src/python/m5/objects/SimpleDisk.py => src/dev/SimpleDisk.py
rename : src/python/m5/objects/Uart.py => src/dev/Uart.py
rename : src/python/m5/objects/AlphaConsole.py => src/dev/alpha/AlphaConsole.py
rename : src/python/m5/objects/Tsunami.py => src/dev/alpha/Tsunami.py
rename : src/python/m5/objects/T1000.py => src/dev/sparc/T1000.py
rename : src/python/m5/objects/Bridge.py => src/mem/Bridge.py
rename : src/python/m5/objects/Bus.py => src/mem/Bus.py
rename : src/python/m5/objects/MemObject.py => src/mem/MemObject.py
rename : src/python/m5/objects/PhysicalMemory.py => src/mem/PhysicalMemory.py
rename : src/python/m5/objects/BaseCache.py => src/mem/cache/BaseCache.py
rename : src/python/m5/objects/CoherenceProtocol.py => src/mem/cache/coherence/CoherenceProtocol.py
rename : src/python/m5/objects/Repl.py => src/mem/cache/tags/Repl.py
rename : src/python/m5/objects/Process.py => src/sim/Process.py
rename : src/python/m5/objects/Root.py => src/sim/Root.py
rename : src/python/m5/objects/System.py => src/sim/System.py
extra : convert_revision : 173f8764bafa8ef899198438fa5573874e407321
2007-05-27 19:21:17 -07:00
Steve Reinhardt da46364b18 Fix getDeviceAddressRanges() to get snooping right.
--HG--
extra : convert_revision : 2aeab25ef955ab9db7b968786faff227239fbbe4
2007-05-22 07:30:55 -07:00
Steve Reinhardt 0484867d85 Merge vm1.(none):/home/stever/bk/newmem-head
into  vm1.(none):/home/stever/bk/newmem-cache2

src/mem/cache/base_cache.hh:
    Manual conflict resolution.

--HG--
extra : convert_revision : 5ebfd7abb4f978caa88bf43d25935869edfc6b9f
2007-05-22 06:36:01 -07:00
Steve Reinhardt 9048c695a0 Another pass of minor changes in preparation for new protocol.
src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/simple_coherence.hh:
    Get rid of old invalidate propagation logic in preparation
    for new multilevel snoop protocol.
src/mem/cache/coherence/coherence_protocol.cc:
    L2 cache now has protocol, so protocol must handle ReadExReq
    coming in from the CPU side.
src/mem/cache/miss/mshr_queue.cc:
    Assertion is failing, so let's take it out for now.
src/mem/packet.cc:
src/mem/packet.hh:
    Add WritebackAck command.
    Reorganize enum to put responses next to corresponding requests.
    Get rid of unused WriteReqNoAck.

--HG--
extra : convert_revision : 24c519846d161978123f9aa029ae358a41546c73
2007-05-22 06:29:48 -07:00
Steve Reinhardt 41241799ae Change getDeviceAddressRanges to use bool for snoop arg.
--HG--
extra : convert_revision : 832e52ba80cbab2f5bb6d5b5977a499d41b4d638
2007-05-21 23:36:09 -07:00
Steve Reinhardt 0a02e3a764 Merge vm1.(none):/home/stever/bk/newmem-head
into  vm1.(none):/home/stever/bk/newmem-cache2

--HG--
extra : convert_revision : a8efe71a50b9ae480c5ad0aabd7aa9ba22bc2968
2007-05-20 23:05:02 -07:00
Steve Reinhardt 87adc37e91 Insist that PhysicalMemory object have at least one connection.
--HG--
extra : convert_revision : 36c33d25a3b23ac2094577aa504c24fac0f3ffcc
2007-05-20 18:23:05 -07:00
Steve Reinhardt dcce351eaa Merge vm1.(none):/home/stever/bk/newmem-head
into  vm1.(none):/home/stever/bk/newmem-cache2

src/mem/bridge.cc:
    SCCS merged

--HG--
extra : convert_revision : 9492be56a305afe88f28a77c3b23e80ce6aa81b3
2007-05-18 22:37:32 -07:00
Steve Reinhardt 792d5b9e5e First set of changes for reorganized cache coherence support.
Compiles but doesn't work... committing just so I can merge
(stupid bk!).

src/mem/bridge.cc:
    Get rid of SNOOP_COMMIT.
src/mem/bus.cc:
src/mem/packet.hh:
    Get rid of SNOOP_COMMIT & two-pass snoop.
    First bits of EXPRESS_SNOOP support.
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/miss_queue.cc:
src/mem/cache/prefetch/base_prefetcher.cc:
    Big reorg of ports and port-related functions & events.
src/mem/cache/cache.cc:
src/mem/cache/cache_builder.cc:
src/mem/cache/coherence/SConscript:
    Get rid of UniCoherence object.

--HG--
extra : convert_revision : 7672434fa3115c9b1c94686f497e57e90413b7c3
2007-05-18 22:35:04 -07:00
Steve Reinhardt aa5b595f39 Oops... some places in C++ explicitly ask for a "functional"
port.  It would be better to move this to python IMO but for
now I'll stick in a compatibility hack.

--HG--
extra : convert_revision : a81a29cbd43becd0e485559eb7b2a31f7a0b082d
2007-05-19 01:20:58 -04:00