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cache
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Fixes to hitLatency, blocking, buffer allocation.
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2007-06-22 09:24:07 -07:00 |
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config
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Backing in more changsets, getting closer to compile
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2006-06-28 14:35:00 -04:00 |
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bridge.cc
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More major reorg of cache. Seems to work for atomic mode now,
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2007-06-17 17:27:53 -07:00 |
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bridge.hh
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Change getDeviceAddressRanges to use bool for snoop arg.
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2007-05-21 23:36:09 -07:00 |
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Bridge.py
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Move SimObject python files alongside the C++ and fix
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2007-05-27 19:21:17 -07:00 |
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bus.cc
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Merge vm1.(none):/home/stever/bk/newmem-head
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2007-06-21 12:03:22 -07:00 |
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bus.hh
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Merge vm1.(none):/home/stever/bk/newmem-head
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2007-06-17 17:30:24 -07:00 |
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Bus.py
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Move SimObject python files alongside the C++ and fix
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2007-05-27 19:21:17 -07:00 |
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dram.cc
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make our code a little more standards compliant
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2007-01-26 18:48:51 -05:00 |
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dram.hh
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Use PacketPtr everywhere
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2006-10-20 00:10:12 -07:00 |
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mem_object.cc
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stop m5 from leaking like a sieve
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2007-03-08 18:57:15 -05:00 |
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mem_object.hh
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stop m5 from leaking like a sieve
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2007-03-08 18:57:15 -05:00 |
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MemObject.py
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Move SimObject python files alongside the C++ and fix
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2007-05-27 19:21:17 -07:00 |
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packet.cc
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Getting closer...
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2007-06-21 11:59:17 -07:00 |
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packet.hh
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Merge vm1.(none):/home/stever/bk/newmem-head
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2007-06-21 12:03:22 -07:00 |
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packet_access.hh
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Make byteswap work correctly on Twin??_t types.
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2007-03-07 17:46:04 +00:00 |
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page_table.cc
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Clean up some of vincent's code and commit it
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2007-06-05 01:03:35 -04:00 |
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page_table.hh
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Clean up some of vincent's code and commit it
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2007-06-05 01:03:35 -04:00 |
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physical.cc
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More major reorg of cache. Seems to work for atomic mode now,
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2007-06-17 17:27:53 -07:00 |
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physical.hh
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More major reorg of cache. Seems to work for atomic mode now,
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2007-06-17 17:27:53 -07:00 |
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PhysicalMemory.py
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Move SimObject python files alongside the C++ and fix
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2007-05-27 19:21:17 -07:00 |
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port.cc
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The MemoryObject tha owns a port should delete it if it so chooses when deletePortRefs() is called on it with that port as a parameter.
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2007-04-04 13:56:38 -04:00 |
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port.hh
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Change getDeviceAddressRanges to use bool for snoop arg.
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2007-05-21 23:36:09 -07:00 |
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port_impl.hh
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Put the ProcessInfo and StackTrace objects into the ISA namespaces.
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2006-11-08 00:52:04 -05:00 |
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request.hh
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Use FastAlloc for Packet, Request, CoherenceState, and SenderState so we don't spend so much time calling malloc()
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2007-06-21 13:50:35 -04:00 |
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SConscript
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Move SimObject python files alongside the C++ and fix
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2007-05-27 19:21:17 -07:00 |
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tport.cc
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More major reorg of cache. Seems to work for atomic mode now,
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2007-06-17 17:27:53 -07:00 |
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tport.hh
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A little more cleanup & refactoring of SimpleTimingPort.
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2007-05-29 22:23:41 -07:00 |
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translating_port.cc
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fix the translating ports so it can add a page on a fault
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2007-05-09 15:37:46 -04:00 |
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translating_port.hh
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fix the translating ports so it can add a page on a fault
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2007-05-09 15:37:46 -04:00 |
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vport.cc
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implement vtophys and 32bit gdb support
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2007-02-18 19:57:46 -05:00 |
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vport.hh
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implement vtophys and 32bit gdb support
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2007-02-18 19:57:46 -05:00 |
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