Steve Reinhardt bdd5fd20fb Fixes to hitLatency, blocking, buffer allocation. ... Single-cpu timing mode seems to work now. --HG-- extra : convert_revision : 720f6172df18a1c941e5bd0e8fdfbd686c13c7ad		2007-06-22 09:24:07 -07:00
..
coherence	Getting closer...	2007-06-21 11:59:17 -07:00
miss	Fixes to hitLatency, blocking, buffer allocation.	2007-06-22 09:24:07 -07:00
prefetch	Getting closer...	2007-06-21 11:59:17 -07:00
tags	More major reorg of cache. Seems to work for atomic mode now,	2007-06-17 17:27:53 -07:00
base_cache.cc	Fixes to hitLatency, blocking, buffer allocation.	2007-06-22 09:24:07 -07:00
base_cache.hh	Fixes to hitLatency, blocking, buffer allocation.	2007-06-22 09:24:07 -07:00
BaseCache.py	Make sure all parameters have default values if they're	2007-06-20 08:14:11 -07:00
cache.cc	More major reorg of cache. Seems to work for atomic mode now,	2007-06-17 17:27:53 -07:00
cache.hh	Fixes to hitLatency, blocking, buffer allocation.	2007-06-22 09:24:07 -07:00
cache_blk.hh	More major reorg of cache. Seems to work for atomic mode now,	2007-06-17 17:27:53 -07:00
cache_builder.cc	More major reorg of cache. Seems to work for atomic mode now,	2007-06-17 17:27:53 -07:00
cache_impl.hh	Fixes to hitLatency, blocking, buffer allocation.	2007-06-22 09:24:07 -07:00
SConscript	Move SimObject python files alongside the C++ and fix	2007-05-27 19:21:17 -07:00