35cf19d441
timing mode still broken.
configs/example/memtest.py:
Revamp options.
src/cpu/memtest/memtest.cc:
No need for memory initialization.
No need to make atomic response... memory system should do that now.
src/cpu/memtest/memtest.hh:
MemTest really doesn't want to snoop.
src/mem/bridge.cc:
checkFunctional() cleanup.
src/mem/bus.cc:
src/mem/bus.hh:
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache.cc:
src/mem/cache/cache.hh:
src/mem/cache/cache_blk.hh:
src/mem/cache/cache_builder.cc:
src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/coherence_protocol.cc:
src/mem/cache/coherence/coherence_protocol.hh:
src/mem/cache/coherence/simple_coherence.hh:
src/mem/cache/miss/SConscript:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr.hh:
src/mem/cache/miss/mshr_queue.cc:
src/mem/cache/miss/mshr_queue.hh:
src/mem/cache/prefetch/base_prefetcher.cc:
src/mem/cache/tags/fa_lru.cc:
src/mem/cache/tags/fa_lru.hh:
src/mem/cache/tags/iic.cc:
src/mem/cache/tags/iic.hh:
src/mem/cache/tags/lru.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/split.cc:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_lifo.cc:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.cc:
src/mem/cache/tags/split_lru.hh:
src/mem/packet.cc:
src/mem/packet.hh:
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/tport.cc:
More major reorg. Seems to work for atomic mode now,
timing mode still broken.
--HG--
extra : convert_revision : 7e70dfc4a752393b911880ff028271433855ae87
410 lines
16 KiB
C++
410 lines
16 KiB
C++
/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Erik Hallnor
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* Nathan Binkert
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*/
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/**
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* @file
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* Simobject instatiation of caches.
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*/
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#include <vector>
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// Must be included first to determine which caches we want
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#include "mem/config/cache.hh"
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#include "mem/config/prefetch.hh"
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#include "mem/cache/base_cache.hh"
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#include "mem/cache/cache.hh"
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#include "mem/bus.hh"
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#include "mem/cache/coherence/coherence_protocol.hh"
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#include "sim/builder.hh"
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// Tag Templates
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#if defined(USE_CACHE_LRU)
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#include "mem/cache/tags/lru.hh"
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#endif
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#if defined(USE_CACHE_FALRU)
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#include "mem/cache/tags/fa_lru.hh"
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#endif
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#if defined(USE_CACHE_IIC)
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#include "mem/cache/tags/iic.hh"
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#endif
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#if defined(USE_CACHE_SPLIT)
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#include "mem/cache/tags/split.hh"
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#endif
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#if defined(USE_CACHE_SPLIT_LIFO)
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#include "mem/cache/tags/split_lifo.hh"
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#endif
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// Compression Templates
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#include "base/compression/null_compression.hh"
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#include "base/compression/lzss_compression.hh"
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// Coherence Templates
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#include "mem/cache/coherence/simple_coherence.hh"
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//Prefetcher Headers
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#if defined(USE_GHB)
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#include "mem/cache/prefetch/ghb_prefetcher.hh"
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#endif
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#if defined(USE_TAGGED)
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#include "mem/cache/prefetch/tagged_prefetcher.hh"
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#endif
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#if defined(USE_STRIDED)
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#include "mem/cache/prefetch/stride_prefetcher.hh"
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#endif
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using namespace std;
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using namespace TheISA;
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#ifndef DOXYGEN_SHOULD_SKIP_THIS
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(BaseCache)
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Param<int> size;
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Param<int> assoc;
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Param<int> block_size;
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Param<int> latency;
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Param<int> mshrs;
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Param<int> tgts_per_mshr;
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Param<int> write_buffers;
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Param<bool> prioritizeRequests;
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SimObjectParam<CoherenceProtocol *> protocol;
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Param<Addr> trace_addr;
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Param<int> hash_delay;
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#if defined(USE_CACHE_IIC)
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SimObjectParam<Repl *> repl;
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#endif
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Param<bool> compressed_bus;
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Param<bool> store_compressed;
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Param<bool> adaptive_compression;
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Param<int> compression_latency;
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Param<int> subblock_size;
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Param<Counter> max_miss_count;
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VectorParam<Range<Addr> > addr_range;
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// SimObjectParam<MemTraceWriter *> mem_trace;
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Param<bool> split;
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Param<int> split_size;
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Param<bool> lifo;
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Param<bool> two_queue;
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Param<bool> prefetch_miss;
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Param<bool> prefetch_access;
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Param<int> prefetcher_size;
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Param<bool> prefetch_past_page;
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Param<bool> prefetch_serial_squash;
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Param<Tick> prefetch_latency;
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Param<int> prefetch_degree;
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Param<string> prefetch_policy;
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Param<bool> prefetch_cache_check_push;
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Param<bool> prefetch_use_cpu_id;
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Param<bool> prefetch_data_accesses_only;
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END_DECLARE_SIM_OBJECT_PARAMS(BaseCache)
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BEGIN_INIT_SIM_OBJECT_PARAMS(BaseCache)
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INIT_PARAM(size, "capacity in bytes"),
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INIT_PARAM(assoc, "associativity"),
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INIT_PARAM(block_size, "block size in bytes"),
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INIT_PARAM(latency, "hit latency in CPU cycles"),
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INIT_PARAM(mshrs, "number of MSHRs (max outstanding requests)"),
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INIT_PARAM(tgts_per_mshr, "max number of accesses per MSHR"),
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INIT_PARAM_DFLT(write_buffers, "number of write buffers", 8),
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INIT_PARAM_DFLT(prioritizeRequests, "always service demand misses first",
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false),
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INIT_PARAM_DFLT(protocol, "coherence protocol to use in the cache", NULL),
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INIT_PARAM_DFLT(trace_addr, "address to trace", 0),
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INIT_PARAM_DFLT(hash_delay, "time in cycles of hash access",1),
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#if defined(USE_CACHE_IIC)
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INIT_PARAM_DFLT(repl, "replacement policy",NULL),
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#endif
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INIT_PARAM_DFLT(compressed_bus,
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"This cache connects to a compressed memory",
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false),
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INIT_PARAM_DFLT(store_compressed, "Store compressed data in the cache",
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false),
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INIT_PARAM_DFLT(adaptive_compression, "Use an adaptive compression scheme",
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false),
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INIT_PARAM_DFLT(compression_latency,
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"Latency in cycles of compression algorithm",
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0),
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INIT_PARAM_DFLT(subblock_size,
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"Size of subblock in IIC used for compression",
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0),
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INIT_PARAM_DFLT(max_miss_count,
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"The number of misses to handle before calling exit",
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0),
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INIT_PARAM_DFLT(addr_range, "The address range in bytes",
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vector<Range<Addr> >(1,RangeIn((Addr)0, MaxAddr))),
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// INIT_PARAM_DFLT(mem_trace, "Memory trace to write accesses to", NULL),
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INIT_PARAM_DFLT(split, "Whether this is a partitioned cache", false),
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INIT_PARAM_DFLT(split_size, "the number of \"ways\" belonging to the LRU partition", 0),
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INIT_PARAM_DFLT(lifo, "whether you are using a LIFO repl. policy", false),
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INIT_PARAM_DFLT(two_queue, "whether the lifo should have two queue replacement", false),
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INIT_PARAM_DFLT(prefetch_miss, "wheter you are using the hardware prefetcher from Miss stream", false),
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INIT_PARAM_DFLT(prefetch_access, "wheter you are using the hardware prefetcher from Access stream", false),
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INIT_PARAM_DFLT(prefetcher_size, "Number of entries in the harware prefetch queue", 100),
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INIT_PARAM_DFLT(prefetch_past_page, "Allow prefetches to cross virtual page boundaries", false),
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INIT_PARAM_DFLT(prefetch_serial_squash, "Squash prefetches with a later time on a subsequent miss", false),
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INIT_PARAM_DFLT(prefetch_latency, "Latency of the prefetcher", 10),
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INIT_PARAM_DFLT(prefetch_degree, "Degree of the prefetch depth", 1),
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INIT_PARAM_DFLT(prefetch_policy, "Type of prefetcher to use", "none"),
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INIT_PARAM_DFLT(prefetch_cache_check_push, "Check if in cash on push or pop of prefetch queue", true),
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INIT_PARAM_DFLT(prefetch_use_cpu_id, "Use the CPU ID to seperate calculations of prefetches", true),
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INIT_PARAM_DFLT(prefetch_data_accesses_only, "Only prefetch on data not on instruction accesses", false)
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END_INIT_SIM_OBJECT_PARAMS(BaseCache)
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#define BUILD_CACHE(TAGS, tags, c) \
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do { \
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BasePrefetcher *pf; \
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if (pf_policy == "tagged") { \
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BUILD_TAGGED_PREFETCHER(TAGS); \
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} \
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else if (pf_policy == "stride") { \
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BUILD_STRIDED_PREFETCHER(TAGS); \
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} \
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else if (pf_policy == "ghb") { \
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BUILD_GHB_PREFETCHER(TAGS); \
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} \
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else { \
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BUILD_NULL_PREFETCHER(TAGS); \
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} \
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Cache<TAGS, c>::Params params(tags, coh, base_params, \
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pf, prefetch_access, latency, \
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true, \
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prefetch_miss); \
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Cache<TAGS, c> *retval = \
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new Cache<TAGS, c>(getInstanceName(), params); \
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return retval; \
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} while (0)
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#define BUILD_CACHE_PANIC(x) do { \
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panic("%s not compiled into M5", x); \
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} while (0)
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#define BUILD_COMPRESSED_CACHE(TAGS, tags, c) \
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do { \
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CompressionAlgorithm *compAlg; \
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if (compressed_bus || store_compressed) { \
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compAlg = new LZSSCompression(); \
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} else { \
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compAlg = new NullCompression(); \
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} \
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BUILD_CACHE(TAGS, tags, c); \
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} while (0)
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#if defined(USE_CACHE_FALRU)
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#define BUILD_FALRU_CACHE(c) do { \
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FALRU *tags = new FALRU(block_size, size, latency); \
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BUILD_COMPRESSED_CACHE(FALRU, tags, c); \
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} while (0)
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#else
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#define BUILD_FALRU_CACHE(c) BUILD_CACHE_PANIC("falru cache")
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#endif
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#if defined(USE_CACHE_LRU)
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#define BUILD_LRU_CACHE(c) do { \
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LRU *tags = new LRU(numSets, block_size, assoc, latency); \
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BUILD_COMPRESSED_CACHE(LRU, tags, c); \
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} while (0)
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#else
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#define BUILD_LRU_CACHE(c) BUILD_CACHE_PANIC("lru cache")
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#endif
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#if defined(USE_CACHE_SPLIT)
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#define BUILD_SPLIT_CACHE(c) do { \
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Split *tags = new Split(numSets, block_size, assoc, split_size, lifo, \
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two_queue, latency); \
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BUILD_COMPRESSED_CACHE(Split, tags, c); \
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} while (0)
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#else
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#define BUILD_SPLIT_CACHE(c) BUILD_CACHE_PANIC("split cache")
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#endif
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#if defined(USE_CACHE_SPLIT_LIFO)
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#define BUILD_SPLIT_LIFO_CACHE(c) do { \
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SplitLIFO *tags = new SplitLIFO(block_size, size, assoc, \
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latency, two_queue, -1); \
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BUILD_COMPRESSED_CACHE(SplitLIFO, tags, c); \
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} while (0)
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#else
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#define BUILD_SPLIT_LIFO_CACHE(c) BUILD_CACHE_PANIC("lifo cache")
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#endif
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#if defined(USE_CACHE_IIC)
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#define BUILD_IIC_CACHE(c) do { \
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IIC *tags = new IIC(iic_params); \
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BUILD_COMPRESSED_CACHE(IIC, tags, c); \
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} while (0)
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#else
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#define BUILD_IIC_CACHE(c) BUILD_CACHE_PANIC("iic")
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#endif
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#define BUILD_CACHES(c) do { \
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if (repl == NULL) { \
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if (numSets == 1) { \
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BUILD_FALRU_CACHE(c); \
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} else { \
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if (split == true) { \
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BUILD_SPLIT_CACHE(c); \
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} else if (lifo == true) { \
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BUILD_SPLIT_LIFO_CACHE(c); \
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} else { \
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BUILD_LRU_CACHE(c); \
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} \
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} \
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} else { \
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BUILD_IIC_CACHE(c); \
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} \
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} while (0)
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#define BUILD_COHERENCE(b) do { \
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} while (0)
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#if defined(USE_TAGGED)
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#define BUILD_TAGGED_PREFETCHER(t) \
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pf = new TaggedPrefetcher(prefetcher_size, \
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!prefetch_past_page, \
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prefetch_serial_squash, \
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prefetch_cache_check_push, \
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prefetch_data_accesses_only, \
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prefetch_latency, \
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prefetch_degree)
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#else
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#define BUILD_TAGGED_PREFETCHER(t) BUILD_CACHE_PANIC("Tagged Prefetcher")
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#endif
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#if defined(USE_STRIDED)
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#define BUILD_STRIDED_PREFETCHER(t) \
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pf = new StridePrefetcher(prefetcher_size, \
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!prefetch_past_page, \
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prefetch_serial_squash, \
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prefetch_cache_check_push, \
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prefetch_data_accesses_only, \
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prefetch_latency, \
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prefetch_degree, \
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prefetch_use_cpu_id)
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#else
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#define BUILD_STRIDED_PREFETCHER(t) BUILD_CACHE_PANIC("Stride Prefetcher")
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#endif
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#if defined(USE_GHB)
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#define BUILD_GHB_PREFETCHER(t) \
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pf = new GHBPrefetcher(prefetcher_size, \
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!prefetch_past_page, \
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prefetch_serial_squash, \
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prefetch_cache_check_push, \
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prefetch_data_accesses_only, \
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prefetch_latency, \
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prefetch_degree, \
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prefetch_use_cpu_id)
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#else
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#define BUILD_GHB_PREFETCHER(t) BUILD_CACHE_PANIC("GHB Prefetcher")
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#endif
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#if defined(USE_TAGGED)
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#define BUILD_NULL_PREFETCHER(t) \
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pf = new TaggedPrefetcher(prefetcher_size, \
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!prefetch_past_page, \
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prefetch_serial_squash, \
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prefetch_cache_check_push, \
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prefetch_data_accesses_only, \
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prefetch_latency, \
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prefetch_degree)
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#else
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#define BUILD_NULL_PREFETCHER(t) BUILD_CACHE_PANIC("NULL Prefetcher (uses Tagged)")
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#endif
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CREATE_SIM_OBJECT(BaseCache)
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{
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string name = getInstanceName();
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int numSets = size / (assoc * block_size);
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string pf_policy = prefetch_policy;
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if (subblock_size == 0) {
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subblock_size = block_size;
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}
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// Build BaseCache param object
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BaseCache::Params base_params(latency, block_size,
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mshrs, tgts_per_mshr, write_buffers,
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max_miss_count);
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//Warnings about prefetcher policy
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if (pf_policy == "none" && (prefetch_miss || prefetch_access)) {
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panic("With no prefetcher, you shouldn't prefetch from"
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" either miss or access stream\n");
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}
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if ((pf_policy == "tagged" || pf_policy == "stride" ||
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pf_policy == "ghb") && !(prefetch_miss || prefetch_access)) {
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warn("With this prefetcher you should chose a prefetch"
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" stream (miss or access)\nNo Prefetching will occur\n");
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}
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if ((pf_policy == "tagged" || pf_policy == "stride" ||
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pf_policy == "ghb") && prefetch_miss && prefetch_access) {
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panic("Can't do prefetches from both miss and access"
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" stream\n");
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}
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if (pf_policy != "tagged" && pf_policy != "stride" &&
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pf_policy != "ghb" && pf_policy != "none") {
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panic("Unrecognized form of a prefetcher: %s, try using"
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"['none','stride','tagged','ghb']\n", pf_policy);
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}
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#if defined(USE_CACHE_IIC)
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// Build IIC params
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IIC::Params iic_params;
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iic_params.size = size;
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iic_params.numSets = numSets;
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iic_params.blkSize = block_size;
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iic_params.assoc = assoc;
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iic_params.hashDelay = hash_delay;
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iic_params.hitLatency = latency;
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iic_params.rp = repl;
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iic_params.subblockSize = subblock_size;
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#else
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const void *repl = NULL;
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#endif
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SimpleCoherence *coh = new SimpleCoherence(protocol);
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BUILD_CACHES(SimpleCoherence);
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return NULL;
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}
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REGISTER_SIM_OBJECT("BaseCache", BaseCache)
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#endif //DOXYGEN_SHOULD_SKIP_THIS
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