Steve Reinhardt 9048c695a0 Another pass of minor changes in preparation for new protocol. ... src/mem/cache/cache_impl.hh: src/mem/cache/coherence/simple_coherence.hh: Get rid of old invalidate propagation logic in preparation for new multilevel snoop protocol. src/mem/cache/coherence/coherence_protocol.cc: L2 cache now has protocol, so protocol must handle ReadExReq coming in from the CPU side. src/mem/cache/miss/mshr_queue.cc: Assertion is failing, so let's take it out for now. src/mem/packet.cc: src/mem/packet.hh: Add WritebackAck command. Reorganize enum to put responses next to corresponding requests. Get rid of unused WriteReqNoAck. --HG-- extra : convert_revision : 24c519846d161978123f9aa029ae358a41546c73		2007-05-22 06:29:48 -07:00
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cache	Another pass of minor changes in preparation for new protocol.	2007-05-22 06:29:48 -07:00
config	Backing in more changsets, getting closer to compile	2006-06-28 14:35:00 -04:00
bridge.cc	Merge vm1.(none):/home/stever/bk/newmem-head	2007-05-18 22:37:32 -07:00
bridge.hh	hopefully the final hacky change to make the bus bridge work ok	2007-05-15 17:39:50 -04:00
bus.cc	First set of changes for reorganized cache coherence support.	2007-05-18 22:35:04 -07:00
bus.hh	fix partial writes with a functional memory hack	2007-05-07 14:42:03 -04:00
dram.cc	make our code a little more standards compliant	2007-01-26 18:48:51 -05:00
dram.hh	Use PacketPtr everywhere	2006-10-20 00:10:12 -07:00
mem_object.cc	stop m5 from leaking like a sieve	2007-03-08 18:57:15 -05:00
mem_object.hh	stop m5 from leaking like a sieve	2007-03-08 18:57:15 -05:00
packet.cc	Another pass of minor changes in preparation for new protocol.	2007-05-22 06:29:48 -07:00
packet.hh	Another pass of minor changes in preparation for new protocol.	2007-05-22 06:29:48 -07:00
packet_access.hh	Make byteswap work correctly on Twin??_t types.	2007-03-07 17:46:04 +00:00
page_table.cc	Move the magic m5 PageTableFault into sim/faults.[hh,cc] since it's the same across all architectures.	2007-03-07 20:04:46 +00:00
page_table.hh	add code to serialize se structures. Lisa is working on the python side of things and will test	2006-10-17 19:38:36 -04:00
physical.cc	Insist that PhysicalMemory object have at least one connection.	2007-05-20 18:23:05 -07:00
physical.hh	PhysicalMemory has vector of uniform ports instead of one special one.	2007-05-19 00:24:34 -04:00
port.cc	The MemoryObject tha owns a port should delete it if it so chooses when deletePortRefs() is called on it with that port as a parameter.	2007-04-04 13:56:38 -04:00
port.hh	fix partial writes with a functional memory hack	2007-05-07 14:42:03 -04:00
port_impl.hh	Put the ProcessInfo and StackTrace objects into the ISA namespaces.	2006-11-08 00:52:04 -05:00
request.hh	Move all of the parameters of the Root SimObject so they are	2007-03-06 11:13:43 -08:00
SConscript	Rework the way SCons recurses into subdirectories, making it	2007-03-10 23:00:54 -08:00
tport.cc	add a backoff algorithm when nacks are received by devices	2007-05-09 18:20:24 -04:00
tport.hh	Merge ktlim@zizzer:/bk/newmem	2006-10-31 14:37:19 -05:00
translating_port.cc	fix the translating ports so it can add a page on a fault	2007-05-09 15:37:46 -04:00
translating_port.hh	fix the translating ports so it can add a page on a fault	2007-05-09 15:37:46 -04:00
vport.cc	implement vtophys and 32bit gdb support	2007-02-18 19:57:46 -05:00
vport.hh	implement vtophys and 32bit gdb support	2007-02-18 19:57:46 -05:00