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Author SHA1 Message Date
Nathan Binkert 9838be2521 When nesting if statements, use braces to avoid ambiguous else clauses. 2008-09-26 08:18:57 -07:00
Ali Saidi 3a3e356f4e style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs 2008-09-10 14:26:15 -04:00
Nathan Binkert 9cf8ad3a17 params: Get rid of the remnants of the old style parameter configuration stuff. 2008-08-11 12:22:17 -07:00
Steve Reinhardt 62c08a75ad Make default PhysicalMemory latency slightly more realistic. 
Also update stats to reflect change.
 2008-08-03 18:13:29 -04:00
Steve Reinhardt 8e7ddce284 Use ReadResp instead of LoadLockedResp for LoadLockedReq responses. 2008-07-15 14:38:51 -04:00
Steve Reinhardt 6262e0d909 Add missing newlines to Bus DPRINTFs. 2008-07-15 14:38:51 -04:00
Ali Saidi a4a7a09e96 Remove delVirtPort() and make getVirtPort() only return cached version. 2008-07-01 10:25:07 -04:00
Ali Saidi c5fbbf376a Change everything to use the cached virtPort rather than created their own each time. 
This appears to work, but I don't want to commit it until it gets tested a lot more.
I haven't deleted the functionality in this patch that will come later, but one question
is how to enforce encourage objects that call getVirtPort() to not cache the virtual port
since if the CPU changes out from under them it will be worse than useless. Perhaps a null
function like delVirtPort() is still useful in that case.
 2008-07-01 10:24:19 -04:00
Steve Reinhardt 96bbccc36b Automated merge after backout. 2008-06-28 13:20:00 -04:00
Steve Reinhardt caaac16803 Backed out changeset 94a7bb476fca: caused memory leak. 2008-06-28 13:19:38 -04:00
Steve Reinhardt 1434b86943 Make bus address conflict error more informative 2008-06-21 01:06:27 -04:00
Steve Reinhardt 6b45238316 Generate more useful error messages for unconnected ports. 
Force all non-default ports to provide a name and an
owner in the constructor.
 2008-06-21 01:04:43 -04:00
Nathan Binkert fa8f91fdc0 physmem: Add a null option to physical memory so it doesn't store data. 2008-06-15 21:39:29 -07:00
Nathan Binkert e3c267a3db port: Clean up default port setup and port switchover code. 2008-06-15 21:34:32 -07:00
Nathan Binkert fe325c7f43 MemReq: Add option to reset the time on a request. 2008-06-14 19:39:01 -07:00
Steve Reinhardt caccbd1edc Get rid of bogus bus assertion. 
It runs out that if a MemObject turns around and does a send in its
receive callback, and there are other sends already scheduled, then
it could observe a state where it's not at the head of the list but
the bus's sendEvent is not scheduled (because we're still in the
middle of processing the prior sendEvent).
 2008-06-13 01:33:49 -04:00
Steve Reinhardt 024ec4c5c3 Get rid of bogus cache assertion. 
I was asserting that the only reason you would defer targets is if
a write came in while you had an outstanding read miss, but there's
another case where you could get a read access after you've snooped
an invalidation and buffered it because it applies to a prior
outstanding miss.
 2008-06-13 01:29:20 -04:00
Ali Saidi e71a5270a2 Make sure that output files are always checked success before they're used. 
Make OutputDirectory::resolve() private and change the functions using
resolve() to instead use create().

--HG--
extra : convert_revision : 36d4be629764d0c4c708cec8aa712cd15f966453
 2008-05-15 19:10:26 -04:00
Ali Saidi 8af6dc118c SCons: add comments to SConscript documenting bug workaround 
--HG--
extra : convert_revision : e6cdffe953d56b96c76c7ff14d2dcc3de3ccfcc3
 2008-04-10 15:38:10 -04:00
Ali Saidi fe12f38353 PhysicalMemory: Add parameter for variance in memory delay. 
--HG--
extra : convert_revision : b931472e81dedb650b7accb9061cb426f1c32e66
 2008-04-10 14:44:52 -04:00
Ali Saidi ed27c4c521 SCons: Manually specifying header only directories with Dir() works around the problem 
--HG--
extra : convert_revision : d9713228d934cf4a45114a972603b8bca2bd27d3
 2008-04-08 11:08:26 -04:00
Steve Reinhardt 29be31ce31 Fix handling of writeback-induced writebacks in atomic mode. 
--HG--
extra : convert_revision : 4fa64f8a929f1aa36a9d5a71b8d1816b497aca4c
 2008-03-25 10:01:21 -04:00
Steve Reinhardt 623dd7ed3a Delete the Request for a no-response Packet 
when the Packet is deleted, since the requester
can't possibly do it.

--HG--
extra : convert_revision : 8571b144ecb3c70efc06d09faa8b3161fb58352d
 2008-03-24 01:08:02 -04:00
Steve Reinhardt 93ab43288a Don't FastAlloc MSHRs since we don't allocate them on the fly. 
--HG--
extra : convert_revision : 02775cfb460afe6df0df0938c62cccd93a71e775
 2008-03-24 01:08:02 -04:00
Steve Reinhardt 407710d387 Fix cache problem with writes to tempBlock 
getting wrong writeback address.

--HG--
extra : convert_revision : 023dfb69c227c13a69bfe2744c6af75a45828b0b
 2008-03-22 22:17:15 -04:00
Steve Reinhardt b051ae6acc Fix a few Packet memory leaks. 
--HG--
extra : convert_revision : 00db19f0698c0786f0dff561eea9217860a5a05a
 2008-03-17 03:08:28 -04:00
Steve Reinhardt 131c65f429 Restructure bus timing calcs to cope with pkt being deleted by target. 
--HG--
extra : convert_revision : db8497e73a44f2a06aab121e797e88b4c0c31330
 2008-03-17 03:07:38 -04:00
Steve Reinhardt 19c367fa8f Fix subtle cache bug where read could return stale data 
if a prior write miss arrived while an even earlier
read miss was still outstanding.

--HG--
extra : convert_revision : 4924e145829b2ecf4610b88d33f4773510c6801a
 2008-03-15 05:03:55 -07:00
Steve Reinhardt e6d6adc731 Revamp cache timing access mshr check to make stats sane again. 
--HG--
extra : convert_revision : 37009b8ee536807073b5a5ca07ed1d097a496aea
 2008-02-26 22:03:28 -08:00
Steve Reinhardt bdf3323915 Cache: better comments particularly regarding writeback situation. 
--HG--
extra : convert_revision : 59ff9ee63ee0fec5a7dfc27b485b737455ccf362
 2008-02-26 20:17:26 -08:00
Gabe Black ec1a4cbbc7 Bus: Fix the bus timing to be more realistic. 
--HG--
extra : convert_revision : acd70dc98ab840e55b114706fbb6afb2a95e54bc
 2008-02-26 02:20:08 -05:00
Steve Reinhardt 4597a71cef Make L2+ caches allocate new block for writeback misses 
instead of forwarding down the line.

--HG--
extra : convert_revision : b0d6e7862c92ea7a2d21f817d30398735e7bb8ba
 2008-02-16 14:58:03 -05:00
Nicolas Zea 4c7eb21119 Bus: Only update port cache when there is an item to update it with. 
--HG--
extra : convert_revision : 84848fd48bb9e6693a0518c862364142b1969aa8
 2008-02-10 19:41:03 -05:00
Steve Reinhardt 9d7a69c582 Fix #include lines for renamed cache files. 
--HG--
extra : convert_revision : b5008115dc5b34958246608757e69a3fa43b85c5
 2008-02-10 14:45:25 -08:00
Steve Reinhardt d56e77c180 Rename cache files for brevity and consistency with rest of tree. 
--HG--
rename : src/mem/cache/base_cache.cc => src/mem/cache/base.cc
rename : src/mem/cache/base_cache.hh => src/mem/cache/base.hh
rename : src/mem/cache/cache_blk.cc => src/mem/cache/blk.cc
rename : src/mem/cache/cache_blk.hh => src/mem/cache/blk.hh
rename : src/mem/cache/cache_builder.cc => src/mem/cache/builder.cc
rename : src/mem/cache/miss/mshr.cc => src/mem/cache/mshr.cc
rename : src/mem/cache/miss/mshr.hh => src/mem/cache/mshr.hh
rename : src/mem/cache/miss/mshr_queue.cc => src/mem/cache/mshr_queue.cc
rename : src/mem/cache/miss/mshr_queue.hh => src/mem/cache/mshr_queue.hh
rename : src/mem/cache/prefetch/base_prefetcher.cc => src/mem/cache/prefetch/base.cc
rename : src/mem/cache/prefetch/base_prefetcher.hh => src/mem/cache/prefetch/base.hh
rename : src/mem/cache/prefetch/ghb_prefetcher.cc => src/mem/cache/prefetch/ghb.cc
rename : src/mem/cache/prefetch/ghb_prefetcher.hh => src/mem/cache/prefetch/ghb.hh
rename : src/mem/cache/prefetch/stride_prefetcher.cc => src/mem/cache/prefetch/stride.cc
rename : src/mem/cache/prefetch/stride_prefetcher.hh => src/mem/cache/prefetch/stride.hh
rename : src/mem/cache/prefetch/tagged_prefetcher.cc => src/mem/cache/prefetch/tagged.cc
rename : src/mem/cache/prefetch/tagged_prefetcher.hh => src/mem/cache/prefetch/tagged.hh
rename : src/mem/cache/tags/base_tags.cc => src/mem/cache/tags/base.cc
rename : src/mem/cache/tags/base_tags.hh => src/mem/cache/tags/base.hh
rename : src/mem/cache/tags/Repl.py => src/mem/cache/tags/iic_repl/Repl.py
rename : src/mem/cache/tags/repl/gen.cc => src/mem/cache/tags/iic_repl/gen.cc
rename : src/mem/cache/tags/repl/gen.hh => src/mem/cache/tags/iic_repl/gen.hh
rename : src/mem/cache/tags/repl/repl.hh => src/mem/cache/tags/iic_repl/repl.hh
extra : convert_revision : ff7a35cc155a8d80317563c45cebe405984eac62
 2008-02-10 14:15:42 -08:00
Stephen Hines 6cc1573923 Make the Event::description() a const function 
--HG--
extra : convert_revision : c7768d54d3f78685e93920069f5485083ca989c0
 2008-02-06 16:32:40 -05:00
Geoffrey Blake f9c54d5a4b Temporary fix for ll/sc bug see flyspray task for more info: 
http://www.m5sim.org/flyspray/task/197

Signed-off by: Ali Saidi <saidi@eecs.umich.edu>

--HG--
extra : convert_revision : cdeece7e3163de9abf2c6c7435f1bc93570fab81
 2008-01-06 00:19:45 -05:00
Steve Reinhardt 6c5a3ab8b2 Add ReadRespWithInvalidate to handle multi-level coherence situation 
where we defer a response to a read from a far-away cache A, then later
defer a ReadExcl from a cache B on the same bus as us.  We'll assert
MemInhibit in both cases, but in the latter case MemInhibit will keep
the invalidation from reaching cache A.  This special response tells
cache A that it gets the block to satisfy its read, but must immediately
invalidate it.

--HG--
extra : convert_revision : f85c8b47bb30232da37ac861b50a6539dc81161b
 2008-01-02 15:22:38 -08:00
Steve Reinhardt bf9b3821bd Mark cache-to-cache MSHRs as downstreamPending when necessary. 
Don't mark upstream MSHR as pending if downstream MSHR is already in service.

--HG--
extra : convert_revision : e1c135ff00217291db58ce8a06ccde34c403d37f
 2008-01-02 15:18:33 -08:00
Steve Reinhardt 538da9e24d Don't DPRINTF in the middle of a PrintReq. 
--HG--
extra : convert_revision : 6358c014d14a19a34111c39827b05987507544bb
 2008-01-02 14:42:42 -08:00
Steve Reinhardt 87e5fd1755 Bug fix: functional cache port now needs otherPort set. 
--HG--
extra : convert_revision : fb007df73a77535a5dba19341f7b0b32e8c99548
 2008-01-02 14:42:24 -08:00
Steve Reinhardt cde5a79eab Additional comments and helper functions for PrintReq. 
--HG--
extra : convert_revision : 7eadf9b7db8c0289480f771271b6efe2400006d4
 2008-01-02 13:46:22 -08:00
Steve Reinhardt 3952e41ab1 Add functional PrintReq command for memory-system debugging. 
--HG--
extra : convert_revision : 73b753e57c355b7e6873f047ddc8cb371c3136b7
 2008-01-02 12:20:15 -08:00
Steve Reinhardt 659aef3eb8 Fix formatting and comments in cache_impl.hh 
--HG--
extra : convert_revision : 26d71cca5420ad03e16bf174e15dabe7f902da41
 2008-01-02 12:15:48 -08:00
Gabe Black 8a020d40d3 Make ports that aren't connected to anything fail more gracefully. 
--HG--
extra : convert_revision : 3803b28fb2fdfd729f01f1a44df2ae02ef83a2fc
 2007-11-28 14:39:19 -08:00
Ali Saidi 8026ecbb8e Memory: Cache the physical memory start and size so we don't need a dynamic cast on every access. 
--HG--
extra : convert_revision : d6c3e93718991e7b68248242c80d8e6ac637ac51
 2007-11-19 18:23:43 -05:00
Steve Reinhardt 7d83cf35e1 Tweak check for writable block fill. 
--HG--
extra : convert_revision : c04281bcfc4cd23c7613aeccb21dc74452bcc951
 2007-11-16 20:10:33 -08:00
Steve Reinhardt f03a62008a Fix bug on exclusive response to ReadReq with pending WriteReq. 
--HG--
extra : convert_revision : 5429cd7ca84cf6348813a4607fa16f76aa5df7e0
 2007-11-16 20:10:32 -08:00
Korey Sewell 375ddf8d25 branch merge 
--HG--
extra : convert_revision : 1c56f3c6f2c50d642d2de5ddde83a55234455cec
 2007-11-15 00:14:20 -05:00
Ali Saidi 7c8e4ca3a3 Checkpointing: Name SE page table entries better so that there isn't a problem if multiple workloads are being run at once. 
--HG--
extra : convert_revision : 3bac9bd7fd93fcadf764e2991c5b029f2c745c08
 2007-11-14 23:42:08 -05:00