gem5/src/mem
Ali Saidi 0711f4f17a SE: Fix page table and system serialization, don't reinit process if this is a checkpoint restore.
--HG--
extra : convert_revision : 03dcf3c088e57b7abab60efe700d947117888306
2007-10-25 20:13:35 -04:00
..
cache params: Deprecate old-style constructors; update most SimObject constructors. 2007-08-30 15:16:59 -04:00
config Backing in more changsets, getting closer to compile 2006-06-28 14:35:00 -04:00
bridge.cc params: Deprecate old-style constructors; update most SimObject constructors. 2007-08-30 15:16:59 -04:00
bridge.hh Merge with head 2007-08-26 21:45:40 -07:00
Bridge.py DMA: Add IOCache and fix bus bridge to optionally only send requests one 2007-08-10 16:14:01 -04:00
bus.cc Bus: Fix drain code; old method could return 1 in atomic mode and never call de->process(). 2007-09-05 17:12:41 -04:00
bus.hh params: Deprecate old-style constructors; update most SimObject constructors. 2007-08-30 15:16:59 -04:00
Bus.py Move SimObject python files alongside the C++ and fix 2007-05-27 19:21:17 -07:00
dram.cc Major changes to how SimObjects are created and initialized. Almost all 2007-07-23 21:51:38 -07:00
dram.hh Major changes to how SimObjects are created and initialized. Almost all 2007-07-23 21:51:38 -07:00
mem_object.cc params: Deprecate old-style constructors; update most SimObject constructors. 2007-08-30 15:16:59 -04:00
mem_object.hh params: Deprecate old-style constructors; update most SimObject constructors. 2007-08-30 15:16:59 -04:00
MemObject.py Major changes to how SimObjects are created and initialized. Almost all 2007-07-23 21:51:38 -07:00
packet.cc Merge with head 2007-08-26 21:45:40 -07:00
packet.hh Merge with head 2007-08-26 21:45:40 -07:00
packet_access.hh Make byteswap work correctly on Twin??_t types. 2007-03-07 17:46:04 +00:00
page_table.cc SE: Fix page table and system serialization, don't reinit process if this is a checkpoint restore. 2007-10-25 20:13:35 -04:00
page_table.hh Address translation: Make the page table more flexible. 2007-08-26 20:33:57 -07:00
physical.cc memory system: fix functional access bug. 2007-07-29 20:17:03 -07:00
physical.hh Merge python and x86 changes with cache branch 2007-07-26 23:15:49 -07:00
PhysicalMemory.py Move SimObject python files alongside the C++ and fix 2007-05-27 19:21:17 -07:00
port.cc Get rid of Packet result field. Error responses are 2007-06-30 10:16:18 -07:00
port.hh Change getDeviceAddressRanges to use bool for snoop arg. 2007-05-21 23:36:09 -07:00
port_impl.hh Put the ProcessInfo and StackTrace objects into the ISA namespaces. 2006-11-08 00:52:04 -05:00
request.hh Use FastAlloc for Packet, Request, CoherenceState, and SenderState so we don't spend so much time calling malloc() 2007-06-21 13:50:35 -04:00
SConscript Move SimObject python files alongside the C++ and fix 2007-05-27 19:21:17 -07:00
tport.cc MemorySystem: Fix the use of ?: to produce correct results. 2007-08-12 19:43:54 -04:00
tport.hh memory system: fix functional access bug. 2007-07-29 20:17:03 -07:00
translating_port.cc fix the translating ports so it can add a page on a fault 2007-05-09 15:37:46 -04:00
translating_port.hh fix the translating ports so it can add a page on a fault 2007-05-09 15:37:46 -04:00
vport.cc implement vtophys and 32bit gdb support 2007-02-18 19:57:46 -05:00
vport.hh implement vtophys and 32bit gdb support 2007-02-18 19:57:46 -05:00