Commit graph

334 commits

Author SHA1 Message Date
Korey Sewell
0d8cfed042 Merge zizzer:/bk/newmem
into  zazzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem

--HG--
extra : convert_revision : 054833d2f7019b9a1247efc4451ccb143242059d
2006-03-14 18:30:09 -05:00
Korey Sewell
6547e8882b Minor Sconscript edit ... mips decoder changes ... initialize NNPC and output fault name in simple cpu
SConscript:
    Separate Alpha EIO from syscall building for other architectures
arch/isa_specific.hh:
    change MIPS constant to 34k
arch/mips/isa/decoder.isa:
    Allow sll,ssnop,nop, and ehb to be determined through decoder using
    the different types of default cases
arch/mips/isa/formats/branch.isa:
    Delete debug code
arch/mips/isa/formats/noop.isa:
    add a Nop format
arch/mips/isa_traits.hh:
    use constants instead of enums
arch/mips/process.cc:
    point to the correct header file
cpu/simple/cpu.cc:
    Output the actual fault name
sim/process.cc:
    Inititalize NNPC

--HG--
extra : convert_revision : adb0026dfad25b14c98fb03c98bfe9c681bba6f8
2006-03-14 18:28:51 -05:00
Gabe Black
fa763d2ecf Merge m5.eecs.umich.edu:/bk/newmem
into  ewok.(none):/home/gblack/m5/newmem

cpu/cpu_exec_context.cc:
    Hand merge

--HG--
rename : arch/alpha/registerfile.hh => arch/alpha/regfile.hh
extra : convert_revision : bd18966f7c37c67c2bc7ca2633b58f70ce64409c
2006-03-14 16:08:32 -05:00
Gabe Black
8e4ec55703 Changed the floating point register file into a class with appropriate accessor functions. The width of the floating point register to access can be specified, and if not, it will be accessed at its "natural" width. That is, the width of each individual register. Also, the functions which access the bit representation of floating point registers can use the blahblahBits functions now instead of blahblahInt.
arch/alpha/arguments.cc:
    Renamed readFloatRegInt to readFloatRegBits
arch/alpha/ev5.cc:
    Removed the Double from setFloatRegDouble
arch/alpha/registerfile.hh:
    Changed the floating point register file from a union of arrays to a class with appropriate accessor functions. The interface is necessary for SPARC.
arch/alpha/types.hh:
    Changed the FloatReg type from a union of uint64_t and double to a double, and defined a new type FloatRegBits which is a uint64_t and is used to return the bits which compose a floating point register rather than the value of the register.
arch/isa_parser.py:
    Adjusted the makeRead and makeWrite functions to generate the new versions of readFloatReg and setFloatReg.
base/remote_gdb.cc:
kern/tru64/tru64.hh:
    Replaced setFloatRegInt with setFloatRegBits
cpu/cpu_exec_context.cc:
    Removed the duplicated code for setting the floating point registers, and renamed the function to setFloatRegBits and readFloatRegBits.
cpu/cpu_exec_context.hh:
cpu/exec_context.hh:
cpu/o3/alpha_cpu_impl.hh:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
cpu/o3/regfile.hh:
cpu/ozone/cpu.hh:
cpu/simple/cpu.hh:
    Implemented the new versions of the floating point read and set functions.
cpu/simple/cpu.cc:
    Replaced setFloatRegDouble with setFloatReg

--HG--
extra : convert_revision : 3dad06224723137f6033c335fb8f6395636767f2
2006-03-14 15:55:00 -05:00
Kevin Lim
f045b110cf Have a copyRegs function defined in the ISA that copies registers from one ExecContext to another ExecContext. This makes it easier for anything that needs to copy architected registers to do so in an ISA independent fashion.
arch/alpha/ev5.cc:
    copyIprs now copies from a source ExecContext to a destination ExecContext.
arch/alpha/registerfile.hh:
    Have ISA specific functions to copy all architected registers from one ExecContext to another.
cpu/cpu_exec_context.cc:
    Call the ISA in order to copy any architected registers.

--HG--
extra : convert_revision : 056cc3b3a9f345535d5a57c6524b114bbd5ae3c8
2006-03-13 17:04:24 -05:00
Steve Reinhardt
e2b329d574 Replace Memory with MemObject; no need for two different levels of hierarchy there.
Get rid of addPort().
Change getPort() behavior on PhysicalMemory.

SConscript:
cpu/simple/cpu.hh:
sim/system.cc:
sim/system.hh:
    Replace Memory with MemObject.
cpu/base.hh:
    No need to declare Port here anymore.
cpu/cpu_exec_context.hh:
    Need PageTable definition.
cpu/simple/cpu.cc:
mem/physical.cc:
mem/physical.hh:
    Replace Memory with MemObject.
    Get rid of addPort(); allow getting anonymous ports with getPort().
mem/translating_port.hh:
    Remove unneeded header.
sim/process.cc:
    Replace Memory with MemObject.
    Change how initialization port gets set up to deal with change in
    addPort()/getPort().  Current solution is not ideal but it works.
sim/process.hh:
    Remove unneeded headers and declarations.
    Make LiveProcess::getDesc() abstract instead of panicing if called.
sim/syscall_emul.hh:
    Fix includes.

--HG--
extra : convert_revision : 11d4ffb54230038afcf7219cc46e51f809329a2f
2006-03-12 17:21:59 -05:00
Steve Reinhardt
37c860d334 Get rid of validInstAddr() & validDataAddr().
SE mode can now use page tables to determine which addresses are valid.

sim/process.cc:
sim/process.hh:
    Get rid of validInstAddr() & validDataAddr().
    SE mode can now use page tables to determine which addresses are valid.
    Also get rid of some Process object fields that were only used by those functions.

--HG--
extra : convert_revision : 74a25c0c2453bfc598eedacdbfccea1cf6493ba6
2006-03-12 16:01:41 -05:00
Steve Reinhardt
71c2c962db Clean up "using" declarations.
arch/alpha/isa_traits.hh:
    No unprotected "using" in header files.
cpu/simple/cpu.cc:
    Fix ISA namespace "using" statement.

--HG--
extra : convert_revision : 317ea40f8de00748d7613a0116edab05770bdc72
2006-03-12 15:14:07 -05:00
Korey Sewell
57d53f8a9d Merge zizzer:/bk/newmem
into  zazzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem

--HG--
extra : convert_revision : b101fa550567d5a9f5de6c2d8c3f67829ae050c1
2006-03-12 05:58:28 -05:00
Korey Sewell
4d19bbeeeb MIPS is back to compiling and building now!
arch/alpha/isa_traits.hh:
    used for SimpleCPU instead of explicitly calling the namespace we declare in isa_traits.hhs
    so other archs. can use SimpleCPU
arch/mips/SConscript:
    dont include common_syscall or tru64
arch/mips/faults.cc:
arch/mips/faults.hh:
arch/mips/isa/formats/unimp.isa:
arch/mips/isa/formats/unknown.isa:
    Change Faults to new format
arch/mips/isa/decoder.isa:
    Fix readMiscReg access
    Made change so that you cant explicitly tell if a instruction nop,ehb,or ssnop... These are all variants
    of the sll instruction so I may need to make a separte class of instructions to handle thse better
arch/mips/isa/includes.isa:
    add isa_traits.hh and MipsISA included into every auto-gen file
arch/mips/isa_traits.cc:
    create copyMiscRegs function...
    delete useless code
arch/mips/isa_traits.hh:
    clean up for build
arch/mips/linux_process.cc:
    mem is now getMemPort(), linux process objects now take in a system argument
arch/mips/linux_process.hh:
    new argument for linux process
arch/mips/process.cc:
    add system
arch/mips/process.hh:
    add system variable
cpu/cpu_exec_context.cc:
    Change AlphaISA to TheISA
cpu/exec_context.hh:
    add readNextNPC and setNextNPC functions
cpu/simple/cpu.cc:
    include isa_traits for namespace declariation
cpu/simple/cpu.hh:
    PC & NPC access/modify functions
arch/mips/utility.hh:
    file needed for compile

--HG--
extra : convert_revision : 29a327e79c51c6174a6e526aa68c7aab7e7eb535
2006-03-12 05:57:34 -05:00
Steve Reinhardt
1f5266e79d Minor fix to fault message in SimpleCPU.
cpu/simple/cpu.cc:
    Fix up fault message... 0x prefix is redundant when using %p.

--HG--
extra : convert_revision : 329d4417287a036a0f24544f73f48c0e19059425
2006-03-12 00:34:02 -05:00
Gabe Black
3ed62ad025 Work towards factoring isa_traits.hh into smaller, more specialized files.
arch/SConscript:
    Sorted the switch headers, and added registerfile.hh, constants.hh, types.hh, and utility.hh.
arch/alpha/isa_traits.hh:
    Moved the register file types to registerfile.hh, small functions to utility.hh, and cleaned out alot of stuff that isn't necessary anymore.
base/loader/ecoff_object.cc:
base/loader/elf_object.cc:
cpu/pc_event.hh:
cpu/static_inst.hh:
mem/port.hh:
sim/faults.cc:
sim/system.hh:
    base/misc.hh isn't included through isa_traits.hh anymore.
cpu/simple/cpu.cc:
    Added include for arch/utility.hh

--HG--
extra : convert_revision : 24f65f330f87e3c909c939596cfcf48336022eaf
2006-03-10 19:11:27 -05:00
Gabe Black
2952ea7c82 Merge m5.eecs.umich.edu:/bk/newmem
into  ewok.(none):/home/gblack/m5/newmem

--HG--
extra : convert_revision : 58a5ae14fc8ac697206a3bfa1cf543a3579123d4
2006-03-10 17:01:58 -05:00
Ron Dreslinski
d07115f972 Add getMemPort to exec context proxy
--HG--
extra : convert_revision : a28c0410a63745b7455ad957c582c38319901cf0
2006-03-10 16:51:52 -05:00
Gabe Black
68d7382cf3 Eliminated TARGET_ALPHA, since THE_ISA provides the same function.
--HG--
extra : convert_revision : eb173a553b0782891e8b4a8e227bfb647390883a
2006-03-10 16:26:31 -05:00
Gabe Black
f102365bfe SimpleCPU compiles with merge.
arch/alpha/isa_traits.hh:
arch/alpha/linux/process.cc:
arch/alpha/process.cc:
arch/alpha/process.hh:
arch/alpha/tru64/process.cc:
base/chunk_generator.hh:
base/loader/elf_object.cc:
cpu/cpu_exec_context.cc:
cpu/cpu_exec_context.hh:
cpu/exec_context.hh:
cpu/simple/cpu.cc:
kern/linux/linux.hh:
kern/tru64/tru64.hh:
mem/packet.hh:
mem/page_table.cc:
mem/page_table.hh:
mem/physical.cc:
mem/request.hh:
mem/translating_port.cc:
sim/process.hh:
sim/system.cc:
    Fixing merged changes.

--HG--
extra : convert_revision : 2e94f21009395db654880fcb94ec806b6f5772c3
2006-03-09 19:21:35 -05:00
Gabe Black
872bbdfc33 Hand merge. Stuff probably doesn't compile.
--HG--
rename : arch/alpha/isa_desc => arch/alpha/isa/main.isa
rename : arch/alpha/alpha_linux_process.cc => arch/alpha/linux/process.cc
rename : arch/alpha/alpha_linux_process.hh => arch/alpha/linux/process.hh
rename : arch/alpha/alpha_tru64_process.cc => arch/alpha/tru64/process.cc
rename : arch/alpha/alpha_tru64_process.hh => arch/alpha/tru64/process.hh
rename : cpu/exec_context.cc => cpu/cpu_exec_context.cc
rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh
extra : convert_revision : 7d1efcedd708815d985a951f6f010fbd83dc27e8
2006-03-09 18:35:28 -05:00
Ali Saidi
56cc760f6f Merge zizzer:/bk/multiarch
into  zeep.eecs.umich.edu:/z/saidi/work/m5.ma2

arch/alpha/isa_traits.hh:
arch/alpha/linux/process.cc:
arch/sparc/isa_traits.hh:
arch/sparc/linux/process.cc:
sim/process.cc:
    merge

--HG--
rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh
extra : convert_revision : fea0155c8e23abbd0d5d5251abbd0f4d223fe935
2006-03-09 15:56:42 -05:00
Ali Saidi
ce3a6343b6 no more common syscall emulation, now common for everyone
check abi-tag note section of elf binary for OS
add pseudo functions (moved from alpha and made to be generic)
move setsyscallreturn into isa traits

arch/alpha/SConscript:
    no more common syscall emulation, now common for everyone
arch/alpha/isa_traits.hh:
    move setsyscallreturn into isa description
arch/alpha/linux/process.cc:
arch/alpha/tru64/process.cc:
    use generic functions rather than alpha specific ones
arch/sparc/isa_traits.hh:
    have consts for generic pseudo syscalls
arch/sparc/linux/process.cc:
    use generic functions
base/loader/elf_object.cc:
    check abi-tag note section of elf binary for OS
cpu/exec_context.hh:
    move syssyscallreturn into isa traits
sim/process.cc:
    find call num with a more generic
sim/syscall_emul.cc:
sim/syscall_emul.hh:
    add pseudo functions (moved from alpha and made to be generic)

--HG--
extra : convert_revision : 5a31024ecde7e39b830365ddd84593ea501a34d2
2006-03-09 15:42:09 -05:00
Gabe Black
91545ac2bf Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into  zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch

cpu/simple/cpu.cc:
    Hand Merge

--HG--
rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh
extra : convert_revision : bf664b092f993d0f4675ce8e7df13645a920c1f4
2006-03-09 15:15:55 -05:00
Kevin Lim
e30bce8f8e Use functions to access XC.
cpu/exec_context.hh:
    Include readNextNPC function.
cpu/simple/cpu.cc:
    Use functions to set and access nextPC, nextNPC.

--HG--
extra : convert_revision : 22622b9c110e1d99cc9106a2a27c479579d7e1ad
2006-03-09 15:10:55 -05:00
Korey Sewell
a3aae21d03 last changes before big merge
arch/alpha/isa_traits.hh:
arch/sparc/isa_traits.hh:
    add nnpc for compiling purposes in exec_context setNextNPC function
cpu/exec_context.hh:
    set NNPC function
cpu/simple/cpu.cc:
    use NNPC in determining what PC we are using

--HG--
extra : convert_revision : e810cfbc5dc31879b20d2cc40bf9871613203532
2006-03-09 03:27:51 -05:00
Kevin Lim
77e40756b7 Include ability to copy all misc regs.
arch/alpha/ev5.cc:
    Include function for the MiscRegFile to copy all of the Iprs from an ExecContext.
arch/alpha/isa_traits.hh:
    Include functions to copy MiscRegs from an ExecContext.
cpu/cpu_exec_context.cc:
    Be sure to copy all of the misc regs when copying all architectural state.

--HG--
extra : convert_revision : cb948b5ff141ea0f739a1016f98236bd2a512f76
2006-03-08 15:10:47 -05:00
Kevin Lim
67732a7b28 Merge ktlim@zizzer:/bk/m5
into  zamp.eecs.umich.edu:/z/ktlim2/m5-proxyxc

arch/alpha/ev5.cc:
cpu/o3/cpu.hh:
    SCCS merged

--HG--
extra : convert_revision : 38889011ea02005c8fd3a7f3b0be3395223f6166
2006-03-08 13:26:30 -05:00
Kevin Lim
556d069e77 Fixes for accesses to the misc regs.
--HG--
extra : convert_revision : 47c7d90be5a147cb644f11980adcf8165b0ab3bb
2006-03-07 22:24:37 -05:00
Kevin Lim
7712232e55 Fixes to allow the ExecContext to be used for profiling.
cpu/base.cc:
    Change to be calls through the ExecContext instead of accessing the profile object directly.
cpu/cpu_exec_context.cc:
    Add functions to clear and sample the profile object.
cpu/cpu_exec_context.hh:
    Add functions to clear and sample the profile object.  These are not the most flexible functions; it might be better to eventually move the quiesce, profile, and store conditional stuff out of ExecContext so they don't clutter the interface.
cpu/exec_context.hh:
    Include functions to support using the profile object to clear itself and take samples.

--HG--
extra : convert_revision : 40849915fd51303673451515debb9ecdc7afb8c8
2006-03-07 22:21:39 -05:00
Kevin Lim
11aead894d Updates for the quiesceEvent that was added to the XC.
Also several files need to include system.hh or symtab.hh.  This is because exec_context.hh has less #includes than before, requiring some of the files that include it to include some other files as well.

arch/alpha/faults.cc:
    Avoid accessing XC directly.
arch/alpha/stacktrace.cc:
    StackTrace needs to include system.hh.
cpu/cpu_exec_context.cc:
    Update for change to CPUExecContext.
cpu/cpu_exec_context.hh:
    Make quiesce events use CPUExecContext instead of ExecContext.  Include functions to allow the quiesce event and last activate/suspend be accessed.
cpu/exec_context.hh:
    Include functions for quiesceEvent.
cpu/intr_control.cc:
    Needs to include cpu/exec_context.hh.
cpu/profile.cc:
    Needs to include symtab.hh for the symbol table.
cpu/profile.hh:
    Needs forward declare of ExecContext.
cpu/simple/cpu.cc:
    Rename xc to cpuXC.
dev/tsunami_cchip.cc:
    Needs to include exec_context.hh.
kern/kernel_stats.cc:
    Needs to include system.hh.
kern/linux/events.cc:
    Needs to include system.hh.

    Also avoid accessing objects directly from the XC.
kern/tru64/dump_mbuf.cc:
    Include symtab.hh for the SymbolTable and system.hh.
kern/tru64/tru64_events.cc:
    Include system.hh
sim/pseudo_inst.cc:
    Avoid accessing objects directly within the XC.

--HG--
extra : convert_revision : 78fe30d98cd20f7403fa216f772071458b675c84
2006-03-07 19:59:12 -05:00
Gabe Black
8106a80450 Pushed ev5.hh out of the non-alpha code.
arch/SConscript:
    ev5 should now be contained within alpha specific code.
arch/alpha/ev5.cc:
arch/alpha/isa_traits.hh:
    Added getInstAsid and getDataAsid functions. These should be removed when the SimpleScalar cpu model is removed.
arch/sparc/isa_traits.hh:
    Added getInstAsid and getDataAsid functions. These should be removed when the SimpleScalar cpu model is removed. Also made some small fixes.
cpu/o3/alpha_cpu.hh:
    Added typedefs which are required now that there isn't a using namespace EV5.
cpu/o3/alpha_cpu_impl.hh:
    Some small changes so that ev5.hh isn't needed directly.
cpu/o3/cpu.hh:
    Removed including ev5.hh, and pushed retrieving the Asid into the MiscRegFile.
cpu/o3/regfile.hh:
    Removed the include of ev5.hh, using namespace EV5, and the now redundant ipr array.

--HG--
extra : convert_revision : 5ef8f69435a3a888a3f06d0095d89326dafb33fd
2006-03-07 14:08:01 -05:00
Kevin Lim
20eced3ea0 Merge ktlim@zizzer:/bk/m5
into  zamp.eecs.umich.edu:/z/ktlim2/m5-proxyxc

Further changes still need to be made to the XC code.

arch/alpha/ev5.cc:
arch/alpha/freebsd/system.cc:
arch/alpha/linux/system.cc:
base/remote_gdb.cc:
cpu/cpu_exec_context.cc:
cpu/cpu_exec_context.hh:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
kern/kernel_stats.cc:
sim/pseudo_inst.cc:
    Hand merge.

--HG--
rename : kern/freebsd/freebsd_system.cc => arch/alpha/freebsd/system.cc
rename : kern/linux/linux_system.cc => arch/alpha/linux/system.cc
rename : kern/linux/linux_threadinfo.hh => arch/alpha/linux/threadinfo.hh
rename : arch/alpha/alpha_linux_process.cc => arch/alpha/linux_process.cc
rename : arch/alpha/alpha_memory.cc => arch/alpha/tlb.cc
rename : arch/alpha/alpha_tru64_process.cc => arch/alpha/tru64_process.cc
rename : cpu/exec_context.cc => cpu/cpu_exec_context.cc
rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh
extra : convert_revision : c1fe71fdd87d1fcd376f4feec69fc3fa29152e3e
2006-03-05 00:34:54 -05:00
Kevin Lim
f15e492375 Steps towards setting up the infrastructure to allow the new CPU model to work in full system mode.
The major change is renaming the old ExecContext to CPUExecContext, and creating two new classes, ExecContext (an abstract class), and ProxyExecContext (a templated class that derives from ExecContext).

Code outside of the CPU continues to use ExecContext as normal (other than not being able to access variables within the XC).  The CPU uses the CPUExecContext, or however else it stores its own state.  It then creates a ProxyExecContext, templated on the class used to hold its state.  This proxy is passed to any code outside of the CPU that needs to access the XC.  This allows code outside of the CPU to use the ExecContext interface to access any state needed, without knowledge of how that state is laid out.

Note that these changes will not compile without the accompanying revision to automatically rename the shadow registers.

SConscript:
    Include new file, cpu_exec_context.cc.
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_tru64_process.cc:
arch/alpha/arguments.cc:
arch/alpha/isa/decoder.isa:
arch/alpha/stacktrace.cc:
arch/alpha/vtophys.cc:
base/remote_gdb.cc:
cpu/intr_control.cc:
    Avoid directly accessing objects within the XC.
arch/alpha/ev5.cc:
    Avoid directly accessing objects within the XC.

    KernelStats have been moved to the BaseCPU instead of the XC.
arch/alpha/isa_traits.hh:
    Remove clearIprs().  It wasn't used very often and it did not work well with the proxy ExecContext.
cpu/base.cc:
    Place kernel stats within the BaseCPU instead of the ExecContext.

    For now comment out the profiling code sampling until its exact location is decided upon.
cpu/base.hh:
    Kernel stats are now in the BaseCPU instead of the ExecContext.
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
cpu/memtest/memtest.cc:
cpu/memtest/memtest.hh:
    Changes to support rename of old ExecContext to CPUExecContext.  See changeset for more details.
cpu/exetrace.cc:
    Remove unneeded include of exec_context.hh.
cpu/intr_control.hh:
cpu/o3/alpha_cpu_builder.cc:
    Remove unneeded include of exec_context.hh
cpu/o3/alpha_cpu.hh:
cpu/o3/alpha_cpu_impl.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
    Changes to support rename of old ExecContext to CPUExecContext.  See changeset for more details.

    Also avoid accessing anything directly from the XC.
cpu/pc_event.cc:
    Avoid accessing objects directly from the XC.
dev/tsunami_cchip.cc:
    Avoid accessing objects directly within the XC>
kern/freebsd/freebsd_system.cc:
kern/linux/linux_system.cc:
kern/linux/linux_threadinfo.hh:
kern/tru64/dump_mbuf.cc:
kern/tru64/tru64.hh:
kern/tru64/tru64_events.cc:
sim/syscall_emul.cc:
sim/syscall_emul.hh:
    Avoid accessing objects directly within the XC.
kern/kernel_stats.cc:
kern/kernel_stats.hh:
    Kernel stats no longer exist within the XC.
kern/system_events.cc:
    Avoid accessing objects directly within the XC.  Also kernel stats are now in the BaseCPU.
sim/process.cc:
sim/process.hh:
    Avoid accessing regs directly within an ExecContext.  Instead use a CPUExecContext to initialize the registers and copy them over.
cpu/cpu_exec_context.cc:
    Rename old ExecContext to CPUExecContext.  This is used by the old CPU models to store any necessary architectural state.  Also include the ProxyExecContext, which is used to access the CPUExecContext's state in code outside of the CPU.
cpu/cpu_exec_context.hh:
    Rename old ExecContext to CPUExecContext.  This is used by the old CPU models to store any necessary architectural state.  Also include the ProxyExecContext, which is used to access the CPUExecContext's state in code outside of the CPU.

    Remove kernel stats from the ExecContext.
sim/pseudo_inst.cc:
    Kernel stats now live within the CPU.

    Avoid accessing objects directly within the XC.

--HG--
rename : cpu/exec_context.cc => cpu/cpu_exec_context.cc
rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh
extra : convert_revision : a75393a8945c80cca225b5e9d9c22a16609efb85
2006-03-04 15:18:40 -05:00
Kevin Lim
5790e295a9 Merge ktlim@zizzer:/bk/m5
into  zamp.eecs.umich.edu:/z/ktlim2/m5-shadowregs

arch/alpha/ev5.cc:
    Remove intr_post, it is no longer used.
arch/alpha/isa_traits.hh:
    Hand merge.

--HG--
extra : convert_revision : 94f14539a9e5646f8c368b15b2dff18ab2f492cf
2006-03-04 13:06:24 -05:00
Kevin Lim
fc664f7ca6 Merge ktlim@zizzer:/bk/m5
into  zamp.eecs.umich.edu:/z/ktlim2/m5-shadowregs

--HG--
extra : convert_revision : 979ab1fc4e1ea4d6a78ac9a2ec894f0be4feb01d
2006-03-03 16:04:34 -05:00
Kevin Lim
e7825aab59 Changes to support automatic renaming of the shadow registers at decode time. This requires using an ExtMachInst (uint64_t) instead of the normal MachInst; the ExtMachInst is packed with extra decode context information. In the case of Alpha, the PAL mode is included.
The shadow registers are folded into the normal integer registers to ease renaming indexing.

Include the removed Opcdec class of instructions for faulting when a pal mode only instruction is decoded in non-pal mode.

arch/alpha/ev5.cc:
    Changes to automatically map the shadow registers if the instruction is in PAL mode.
arch/alpha/isa/branch.isa:
arch/alpha/isa/decoder.isa:
arch/alpha/isa/fp.isa:
arch/alpha/isa/int.isa:
arch/alpha/isa/mem.isa:
arch/alpha/isa/pal.isa:
arch/alpha/isa/unimp.isa:
    Changes for automatically using the shadow registers.  Now instructions must decode based on an ExtMachInst, which is a MachInst with any decode context information concatenated onto the higher order bits.
arch/alpha/isa/main.isa:
    Changes for automatically using the shadow registers.  Now instructions must decode based on an ExtMachInst, which is a MachInst with any decode context information concatenated onto the higher order bits.

    The decoder (for Alpha) uses the 32nd bit in order to determine if the machine is in PAL mode.  If it is, then it refers to the reg_redir table to determine the true index of the register it is using.

    Also include the opcdec instruction definition.
arch/alpha/isa_traits.hh:
    Define ExtMachInst type that is used by the static inst in order to decode the instruction, given the context of being in pal mode or not.

    Redefine the number of Int registers, splitting it into NumIntArchRegs (32) and NumIntRegs (32 + 8 shadow registers).

    Change the dependence tags to reflect the integer registers include the 8 shadow registers.

    Define function to make an ExtMachInst.  Currently it is somewhat specific to Alpha; in the future it must be decided to make this more generic and possibly slower, or leave it specific to each architecture and ifdef it within the CPU.
arch/isa_parser.py:
    Have static insts decode on the ExtMachInst.
base/remote_gdb.cc:
    Support the automatic remapping of shadow registers.  Remote GDB must now look at the PC being read in order to tell if it should use the normal register indices or the shadow register indices.
cpu/o3/regfile.hh:
    Comment out the pal registers; they are now a part of the integer registers.
cpu/simple/cpu.cc:
    Create an ExtMachInst to decode on, based on the normal MachInst and the PC of the instructoin.
cpu/static_inst.hh:
    Change from MachInst to ExtMachInst to support shadow register renaming.

--HG--
extra : convert_revision : 1d23eabf735e297068e1917445a6348e9f8c88d5
2006-03-03 15:28:25 -05:00
Gabe Black
dd0d8e6287 Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into  ewok.(none):/home/gblack/m5/multiarch

--HG--
extra : convert_revision : f6db244a66431dd6b8c5ba251ed02d76cd509cff
2006-03-02 21:44:43 -05:00
Ali Saidi
0fed64a6a4 Fix fault handling, dereferincing a null pointer is bad.
--HG--
extra : convert_revision : a4f658bfd39b7f1d219ad8929b8f45457f49299f
2006-03-02 17:49:12 -05:00
Steve Reinhardt
e7f442d527 Simple program runs with sendAtomic!
Ignoring returned latency for now.
Refactored loadSections in ObjectFile hierarchy.

base/loader/aout_object.cc:
base/loader/aout_object.hh:
base/loader/ecoff_object.cc:
base/loader/ecoff_object.hh:
base/loader/elf_object.cc:
base/loader/elf_object.hh:
base/loader/object_file.hh:
    Have each section record a pointer to image data.
    This allows us to move common loadSections code into ObjectFile.
base/loader/object_file.cc:
    Have each section record a pointer to image data.
    This allows us to move common loadSections code into ObjectFile.
    Also explicitly load BSS now since we need to allocate the
    translations for it in syscall emulation.
cpu/base.hh:
    Don't need memPort (just pass port in to ExecContext constructor).
cpu/exec_context.cc:
cpu/exec_context.hh:
mem/port.cc:
mem/translating_port.cc:
mem/translating_port.hh:
    Pass syscall emulation Port into constructor instead of
    getting it from BaseCPU.
cpu/simple/cpu.cc:
    Explicitly choose one of three timing models.
    Statically allocate request and packet objects when possible.
    Several more minor bug fixes.
    Works for simple program with SIMPLE_CPU_MEM_IMMEDIATE model now.
    Probably have memory leaks with SIMPLE_CPU_MEM_TIMING (if it works at all).
    Pass syscall emulation Port into constructor instead of
    getting it from BaseCPU.
cpu/simple/cpu.hh:
    Explicitly choose one of three timing models.
    Statically allocate request and packet objects when possible.
    Pass syscall emulation Port into constructor instead of
    getting it from BaseCPU.
mem/physical.cc:
    Set packet result field.

--HG--
extra : convert_revision : 359d0ebe4b4665867f4e26e7394ec0f1d17cfc26
2006-03-02 10:31:48 -05:00
Steve Reinhardt
0c2c7171a8 More progress... run a few instructions now, but die on the second
memory access (I think because we're deallocating our one and only
CpuRequest object).

base/loader/aout_object.cc:
base/loader/ecoff_object.cc:
base/loader/elf_object.cc:
    Add flag to force allocation of new pages on data writes.
cpu/simple/cpu.cc:
    Several minor fixes.
    Switch to atomic mode for now.
mem/physical.hh:
    Don't copy the packet to the response event, just keep a reference
    to the original.
mem/translating_port.cc:
mem/translating_port.hh:
    Add parameter to writeBlobFunctional() to force allocation of
    unallocated pages on writes.

--HG--
extra : convert_revision : 05cb31c7b0047b492dcfa0d12ddee690ef762b44
2006-03-02 01:01:03 -05:00
Steve Reinhardt
22504f8b48 More progress toward actually running a program.
See configs/test.py for test config (using simple
binary in my home directory on zizzer).

base/chunk_generator.hh:
    Fix assertion for chunkSize == 0 (not a power of 2)
base/intmath.hh:
    Fix roundDown to take integer alignments.
cpu/base.cc:
    Register exec contexts regardless of state (not sure why
    this check was in here in the first place).
mem/physical.cc:
    Add breaks to switch.
python/m5/objects/BaseCPU.py:
    Default mem to Parent.any (e.g. get from System).
python/m5/objects/Ethernet.py:
python/m5/objects/Root.py:
    HierParams is gone.
python/m5/objects/PhysicalMemory.py:
    mmu param is full-system only.
sim/process.cc:
    Stack mapping request must be page-aligned and page-sized.
    Don't delete objFile object in create since we are counting
    on it being around for startup().

--HG--
extra : convert_revision : 90c43ee927e7d82a045d6e10302d965797d006f7
2006-03-01 18:45:50 -05:00
Ali Saidi
1624d9e545 Merge zizzer:/bk/m5
into  zeep.eecs.umich.edu:/z/saidi/work/m5.q

--HG--
extra : convert_revision : 4855ecfb3de652456a8be413c9e538c91709dcb6
2006-03-01 12:43:04 -05:00
Gabe Black
2eff368dd0 Cleaned up some of the Fault system.
arch/alpha/ev5.cc:
    Commented out the intr_post function since it's not used. If this really -is- needed, it should be moved into the fault class.
arch/alpha/faults.cc:
arch/alpha/faults.hh:
    Moved the fault invocation code into the fault class fully, and got rid of the need for isA.
cpu/exec_context.cc:
cpu/exec_context.hh:
    Removed the trap function from the ExecContext. The faults will execute normally in full system mode, but always panic in syscall emulation mode.
cpu/ozone/cpu.hh:
cpu/simple/cpu.hh:
    Changed the execution context executing a fault to a fault executing on the execution context.
sim/faults.cc:
    If not in full system mode, trying to invoke a fault causes a panic.
sim/faults.hh:
    Removed the isA function.

--HG--
extra : convert_revision : 894dc8f0755c8efc4b7ef5a09fb2cf7373042395
2006-03-01 05:26:08 -05:00
Gabe Black
e08cf8fee0 Changed the name of the fault's invocation method from ev5_trap to invoke.
--HG--
extra : convert_revision : b7ab14ac644f6a38c69aaa5372b3002b21f34af0
2006-03-01 01:23:10 -05:00
Gabe Black
d6c0657116 Used the Fault constructor to create Interrupt faults. Using the pointer directly prevents reference counting from working correctly.
cpu/simple/cpu.cc:
    Used the Fault constructor to create an Interrupt fault.

--HG--
extra : convert_revision : ec2ef7e3cd04ee9a44628877dc6e770fb907104b
2006-03-01 00:14:09 -05:00
Gabe Black
69e91d7617 moved ev5_trap fully into the fault class.
--HG--
extra : convert_revision : 182cdec9a4e05f55edff0c6a114844b9ad2ca8db
2006-03-01 00:09:08 -05:00
Ali Saidi
26d7b5a4d1 Add quiesceNs, quiesceTime, quiesceCycles, and m5panic pseudo ops.
This changeset removes a check that prevents quiescing when an
interrupt is pending. *** You should only call quiesce if that
isn't a problem. ***

arch/alpha/isa/decoder.isa:
sim/pseudo_inst.cc:
sim/pseudo_inst.hh:
    Add quiesceNs, quiesceCycles, quisceTime and m5panic pseudo ops.
    These quiesce for a number of ns, cycles, report how long
    we were quiesced for, and panic the simulator respectively.
    The latter is added to the panic() function in the console and linux
    kernel instead of executing an infinite loop until someone notices.
cpu/exec_context.cc:
cpu/exec_context.hh:
    Add a quiesce end event to the execution contexted which upon
    executing wakes up a CPU for quiesceCycles/quiesceNs.
util/m5/Makefile:
    Make the makefile more reasonable
util/m5/m5.c:
    update the m5op executable to use the files from the linux tree
util/m5/m5op.S:
    update m5op.S from linux tree
util/m5/m5op.h:
    update m5op.h from linux tree

--HG--
rename : util/m5/m5op.s => util/m5/m5op.S
extra : convert_revision : 3be18525e811405b112e33f24a8c4e772d15462d
2006-02-28 18:41:04 -05:00
Kevin Lim
34da58a698 Merge ktlim@zizzer:/bk/m5
into  zamp.eecs.umich.edu:/z/ktlim2/clean/m5-clean

arch/alpha/ev5.cc:
cpu/o3/regfile.hh:
    Hand merge.

--HG--
rename : arch/alpha/alpha_memory.cc => arch/alpha/tlb.cc
extra : convert_revision : c941dd2198851398820b38a66471372ed8454891
2006-02-28 15:16:24 -05:00
Gabe Black
f7360d5bca Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into  ewok.(none):/home/gblack/m5/multiarch

--HG--
extra : convert_revision : 0b3ffc0605c9043d7f5bf6c15f4a3c68846a732a
2006-02-28 06:13:35 -05:00
Gabe Black
d207168eda Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into  zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch

--HG--
extra : convert_revision : 3a3ff8fcf472db385219a00ae434d1f3fea43b18
2006-02-28 06:03:57 -05:00
Gabe Black
299efffaf5 Cleaned up and slightly reorganized the Fault class heirarchy.
arch/alpha/ev5.cc:
    Changed c style casts of Faults to dynamic_casts
arch/alpha/faults.cc:
    AlphaFault is now an abstract class.
arch/alpha/faults.hh:
    AlphaFault is now an abstract class. Also, AlphaMachineCheckFault and AlphaAlignmentFault multiply inherit from both AlphaFault and from MachineCheckFault and AlignmentFault respectively. These classes get their name from the generic classes.
cpu/o3/alpha_cpu_impl.hh:
    Changed a c style cast to a dynamic_cast for a Fault
sim/faults.hh:
    All generic Fault classes are now abstract. Also, MachineCheckFault and AlignmentFault inherit FaultBase as a virtual base class to help resolve ambiguities when they are multiply inherited in ISA specific classes. The override the isMachineCheckFault and isAlignmentFault functions appropriately, and provide a standard name for these faults.

--HG--
extra : convert_revision : 2cb906708e3eaec4a12587484c09e50ed6ef88fc
2006-02-28 06:02:18 -05:00
Gabe Black
6165419d35 Changed ev5_trap from a function of the execution context to a function of the fault. The actual function still resides in the execution context.
--HG--
extra : convert_revision : 56e33536cdd9079ace03896b85ea3c84b6eb4e57
2006-02-27 23:26:13 -05:00
Gabe Black
2f7b8ab1ec Got rid of the fault_addr function.
--HG--
extra : convert_revision : deb54cd82db47abb6d9bac76e072f2a4b1c883b2
2006-02-27 16:27:01 -05:00