Replace Memory with MemObject; no need for two different levels of hierarchy there.
Get rid of addPort(). Change getPort() behavior on PhysicalMemory. SConscript: cpu/simple/cpu.hh: sim/system.cc: sim/system.hh: Replace Memory with MemObject. cpu/base.hh: No need to declare Port here anymore. cpu/cpu_exec_context.hh: Need PageTable definition. cpu/simple/cpu.cc: mem/physical.cc: mem/physical.hh: Replace Memory with MemObject. Get rid of addPort(); allow getting anonymous ports with getPort(). mem/translating_port.hh: Remove unneeded header. sim/process.cc: Replace Memory with MemObject. Change how initialization port gets set up to deal with change in addPort()/getPort(). Current solution is not ideal but it works. sim/process.hh: Remove unneeded headers and declarations. Make LiveProcess::getDesc() abstract instead of panicing if called. sim/syscall_emul.hh: Fix includes. --HG-- extra : convert_revision : 11d4ffb54230038afcf7219cc46e51f809329a2f
This commit is contained in:
parent
2d9c9dba37
commit
e2b329d574
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@ -88,7 +88,7 @@ base_sources = Split('''
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cpu/static_inst.cc
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cpu/sampler/sampler.cc
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mem/memory.cc
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mem/mem_object.cc
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mem/page_table.cc
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mem/physical.cc
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mem/port.cc
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@ -42,7 +42,6 @@ class System;
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namespace Kernel { class Statistics; }
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class BranchPred;
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class ExecContext;
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class Port;
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class BaseCPU : public SimObject
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{
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@ -53,6 +53,7 @@ class MemoryController;
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#else // !FULL_SYSTEM
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#include "sim/process.hh"
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#include "mem/page_table.hh"
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class TranslatingPort;
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#endif // FULL_SYSTEM
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@ -71,7 +71,7 @@
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#include "arch/stacktrace.hh"
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#include "arch/vtophys.hh"
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#else // !FULL_SYSTEM
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#include "mem/memory.hh"
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#include "mem/mem_object.hh"
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#endif // FULL_SYSTEM
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using namespace std;
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@ -152,13 +152,13 @@ SimpleCPU::SimpleCPU(Params *p)
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_status = Idle;
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//Create Memory Ports (conect them up)
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p->mem->addPort("DCACHE");
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dcachePort.setPeer(p->mem->getPort("DCACHE"));
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(p->mem->getPort("DCACHE"))->setPeer(&dcachePort);
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Port *mem_dport = p->mem->getPort();
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dcachePort.setPeer(mem_dport);
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mem_dport->setPeer(&dcachePort);
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p->mem->addPort("ICACHE");
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icachePort.setPeer(p->mem->getPort("ICACHE"));
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(p->mem->getPort("ICACHE"))->setPeer(&icachePort);
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Port *mem_iport = p->mem->getPort();
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icachePort.setPeer(mem_iport);
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mem_iport->setPeer(&icachePort);
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#if FULL_SYSTEM
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cpuXC = new CPUExecContext(this, 0, p->system, p->itb, p->dtb, p->mem);
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@ -1128,7 +1128,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
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Param<int> cpu_id;
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Param<Tick> profile;
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#else
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SimObjectParam<Memory *> mem;
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SimObjectParam<MemObject *> mem;
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SimObjectParam<Process *> workload;
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#endif // FULL_SYSTEM
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@ -46,7 +46,7 @@
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class Processor;
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class AlphaITB;
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class AlphaDTB;
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class Memory;
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class MemObject;
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class RemoteGDB;
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class GDBListener;
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@ -58,7 +58,6 @@ class Process;
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#endif // FULL_SYSTEM
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class ExecContext;
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class MemInterface;
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class Checkpoint;
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namespace Trace {
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@ -180,7 +179,7 @@ class SimpleCPU : public BaseCPU
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AlphaITB *itb;
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AlphaDTB *dtb;
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#else
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Memory *mem;
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MemObject *mem;
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Process *process;
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#endif
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};
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37
mem/mem_object.cc
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37
mem/mem_object.cc
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@ -0,0 +1,37 @@
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/*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "mem/mem_object.hh"
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#include "sim/param.hh"
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MemObject::MemObject(const std::string &name)
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: SimObject(name)
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{
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}
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DEFINE_SIM_OBJECT_CLASS_NAME("MemObject", MemObject)
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@ -70,7 +70,7 @@ PhysicalMemory::MemResponseEvent::description()
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}
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PhysicalMemory::PhysicalMemory(const string &n)
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: Memory(n), base_addr(0), pmem_addr(NULL)
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: MemObject(n), base_addr(0), pmem_addr(NULL)
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{
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// Hardcoded to 128 MB for now.
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pmem_size = 1 << 27;
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return return_addr;
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}
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Port *
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PhysicalMemory::addPort(std::string portName)
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{
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memoryPortList[portName] = new MemoryPort(this);
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return memoryPortList[portName];
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}
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int
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PhysicalMemory::deviceBlockSize()
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{
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Port *
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PhysicalMemory::getPort(const char *if_name)
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{
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if (memoryPortList.find(if_name) != memoryPortList.end())
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return memoryPortList[if_name];
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else
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panic("Looking for a port that didn't exist\n");
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if (if_name == NULL) {
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return new MemoryPort(this);
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} else {
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panic("PhysicalMemory::getPort: unknown port %s requested", if_name);
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}
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}
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void
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#define __PHYSICAL_MEMORY_HH__
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#include "base/range.hh"
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#include "mem/memory.hh"
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#include "mem/mem_object.hh"
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#include "mem/packet.hh"
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#include "mem/port.hh"
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#include "sim/eventq.hh"
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#include <map>
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#include <string>
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//
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// Functional model for a contiguous block of physical memory. (i.e. RAM)
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//
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class PhysicalMemory : public Memory
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class PhysicalMemory : public MemObject
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{
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class MemoryPort : public Port
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{
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virtual int deviceBlockSize();
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};
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std::map<std::string, MemoryPort*> memoryPortList;
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virtual Port * getPort(const char *if_name);
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virtual Port * addPort(std::string portName);
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int numPorts;
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int lat;
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#ifndef __MEM_TRANSLATING_PROT_HH__
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#define __MEM_TRANSLATING_PROT_HH__
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#include "mem/memory.hh"
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class Port;
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class PageTable;
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@ -39,7 +39,7 @@
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#include "config/full_system.hh"
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#include "cpu/exec_context.hh"
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#include "mem/page_table.hh"
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#include "mem/memory.hh"
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#include "mem/mem_object.hh"
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#include "mem/translating_port.hh"
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#include "sim/builder.hh"
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#include "sim/process.hh"
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if (execContexts.empty())
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fatal("Process %s is not associated with any CPUs!\n", name());
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initVirtMem = new TranslatingPort((system->physmem->getPort("DCACHE"))->getPeer(), pTable);
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// first exec context for this process... initialize & enable
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ExecContext *xc = execContexts[0];
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// mark this context as active so it will start ticking.
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xc->activate(0);
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// Here we are grabbing the memory port of the CPU hosting the
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// initial execution context for initialization. In the long run
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// this is not what we want, since it means that all
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// initialization accesses (e.g., loading object file sections)
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// will be done a cache block at a time through the CPU's cache.
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// We really want something more like:
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//
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// memport = system->physmem->getPort();
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// myPort.setPeer(memport);
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// memport->setPeer(&myPort);
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// initVirtMem = new TranslatingPort(myPort, pTable);
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//
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// but we need our own dummy port "myPort" that doesn't exist.
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// In the short term it works just fine though.
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initVirtMem = xc->getMemPort();
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}
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void
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desc->doSyscall(callnum, this, xc);
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}
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LiveProcess *
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LiveProcess::create(const string &nm, System *system,
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int stdin_fd, int stdout_fd, int stderr_fd,
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@ -40,27 +40,18 @@
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#include <vector>
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#include "arch/isa_traits.hh"
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#include "base/statistics.hh"
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#include "base/trace.hh"
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#include "mem/memory.hh"
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//#include "mem/mem_interface.hh"
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#include "mem/page_table.hh"
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#include "sim/sim_object.hh"
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#include "sim/stats.hh"
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#include "arch/isa_traits.hh"
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class CPUExecContext;
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class ExecContext;
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class SyscallDesc;
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class PageTable;
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class TranslatingPort;
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class System;
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class Process : public SimObject
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{
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protected:
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typedef TheISA::RegFile RegFile;
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typedef TheISA::MachInst MachInst;
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public:
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/// Pointer to object representing the system this process is
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virtual void syscall(ExecContext *xc);
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virtual SyscallDesc* getDesc(int callnum) { panic("Must be implemented."); }
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virtual SyscallDesc* getDesc(int callnum) = 0;
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};
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@ -48,7 +48,7 @@
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#include "base/intmath.hh" // for RoundUp
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#include "mem/translating_port.hh"
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#include "arch/isa_traits.hh" // for Addr
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#include "base/misc.hh"
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#include "base/trace.hh"
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#include "cpu/exec_context.hh"
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#include "cpu/base.hh"
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@ -1,12 +1,12 @@
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#include "base/loader/object_file.hh"
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#include "base/loader/symtab.hh"
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#include "cpu/exec_context.hh"
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#include "mem/memory.hh"
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#include "sim/builder.hh"
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#include "arch/isa_traits.hh"
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#include "sim/byteswap.hh"
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#include "sim/system.hh"
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#include "base/trace.hh"
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#include "mem/mem_object.hh"
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#if FULL_SYSTEM
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#include "base/remote_gdb.hh"
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#include "kern/kernel_stats.hh"
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(System)
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SimObjectParam<Memory *> physmem;
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SimObjectParam<MemObject *> physmem;
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END_DECLARE_SIM_OBJECT_PARAMS(System)
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@ -45,7 +45,7 @@ class BaseCPU;
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class ExecContext;
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class MemoryController;
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class ObjectFile;
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class Memory;
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class MemObject;
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#if FULL_SYSTEM
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class Platform;
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class System : public SimObject
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{
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public:
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Memory *physmem;
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MemObject *physmem;
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PCEventQueue pcEventQueue;
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std::vector<ExecContext *> execContexts;
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struct Params
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{
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std::string name;
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Memory *physmem;
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MemObject *physmem;
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#if FULL_SYSTEM
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Tick boot_cpu_frequency;
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