2008-10-21 01:00:07 +02:00
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---------- Begin Simulation Statistics ----------
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2014-09-20 23:18:53 +02:00
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sim_seconds 1.859039 # Number of seconds simulated
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sim_ticks 1859038679000 # Number of ticks simulated
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final_tick 1859038679000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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2008-10-21 01:00:07 +02:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2014-09-20 23:18:53 +02:00
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host_inst_rate 164972 # Simulator instruction rate (inst/s)
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host_op_rate 164972 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 5794497034 # Simulator tick rate (ticks/s)
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host_mem_usage 371088 # Number of bytes of host memory used
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host_seconds 320.83 # Real time elapsed on the host
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sim_insts 52927600 # Number of instructions simulated
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sim_ops 52927600 # Number of ops (including micro ops) simulated
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2014-01-24 22:29:33 +01:00
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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2014-09-20 23:18:53 +02:00
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system.physmem.bytes_read::cpu.inst 968256 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 24892608 # Number of bytes read from this memory
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2014-09-03 13:42:59 +02:00
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system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
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2014-09-20 23:18:53 +02:00
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system.physmem.bytes_read::total 25861824 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 968256 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 968256 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 4860032 # Number of bytes written to this memory
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2014-09-03 13:42:59 +02:00
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system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory
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2014-09-20 23:18:53 +02:00
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system.physmem.bytes_written::total 7519360 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 15129 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 388947 # Number of read requests responded to by this memory
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2014-09-03 13:42:59 +02:00
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system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
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2014-09-20 23:18:53 +02:00
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system.physmem.num_reads::total 404091 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 75938 # Number of write requests responded to by this memory
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2014-09-03 13:42:59 +02:00
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system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory
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2014-09-20 23:18:53 +02:00
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system.physmem.num_writes::total 117490 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 520837 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 13390043 # Total read bandwidth from this memory (bytes/s)
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2014-09-03 13:42:59 +02:00
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system.physmem.bw_read::tsunami.ide 516 # Total read bandwidth from this memory (bytes/s)
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2014-09-20 23:18:53 +02:00
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system.physmem.bw_read::total 13911396 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 520837 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 520837 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 2614272 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::tsunami.ide 1430486 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 4044757 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 2614272 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 520837 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 13390043 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::tsunami.ide 1431002 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 17956154 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 404091 # Number of read requests accepted
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system.physmem.writeReqs 117490 # Number of write requests accepted
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system.physmem.readBursts 404091 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 117490 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 25850368 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 11456 # Total number of bytes read from write queue
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system.physmem.bytesWritten 7517888 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 25861824 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 7519360 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 179 # Number of DRAM read bursts serviced by the write queue
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2013-11-01 16:56:34 +01:00
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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2014-09-20 23:18:53 +02:00
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system.physmem.neitherReadNorWriteReqs 193 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 25747 # Per bank write bursts
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system.physmem.perBankRdBursts::1 25572 # Per bank write bursts
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system.physmem.perBankRdBursts::2 25523 # Per bank write bursts
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system.physmem.perBankRdBursts::3 25355 # Per bank write bursts
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system.physmem.perBankRdBursts::4 25392 # Per bank write bursts
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system.physmem.perBankRdBursts::5 24811 # Per bank write bursts
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system.physmem.perBankRdBursts::6 25029 # Per bank write bursts
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system.physmem.perBankRdBursts::7 25134 # Per bank write bursts
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system.physmem.perBankRdBursts::8 24968 # Per bank write bursts
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system.physmem.perBankRdBursts::9 25052 # Per bank write bursts
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system.physmem.perBankRdBursts::10 25439 # Per bank write bursts
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system.physmem.perBankRdBursts::11 24779 # Per bank write bursts
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system.physmem.perBankRdBursts::12 24568 # Per bank write bursts
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system.physmem.perBankRdBursts::13 25250 # Per bank write bursts
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system.physmem.perBankRdBursts::14 25688 # Per bank write bursts
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system.physmem.perBankRdBursts::15 25605 # Per bank write bursts
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system.physmem.perBankWrBursts::0 8041 # Per bank write bursts
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system.physmem.perBankWrBursts::1 7603 # Per bank write bursts
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system.physmem.perBankWrBursts::2 7894 # Per bank write bursts
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system.physmem.perBankWrBursts::3 7385 # Per bank write bursts
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system.physmem.perBankWrBursts::4 7327 # Per bank write bursts
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system.physmem.perBankWrBursts::5 6730 # Per bank write bursts
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system.physmem.perBankWrBursts::6 6858 # Per bank write bursts
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system.physmem.perBankWrBursts::7 6765 # Per bank write bursts
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system.physmem.perBankWrBursts::8 7133 # Per bank write bursts
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system.physmem.perBankWrBursts::9 6722 # Per bank write bursts
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system.physmem.perBankWrBursts::10 7301 # Per bank write bursts
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system.physmem.perBankWrBursts::11 6871 # Per bank write bursts
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system.physmem.perBankWrBursts::12 7190 # Per bank write bursts
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system.physmem.perBankWrBursts::13 7853 # Per bank write bursts
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system.physmem.perBankWrBursts::14 7964 # Per bank write bursts
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system.physmem.perBankWrBursts::15 7830 # Per bank write bursts
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2013-11-01 16:56:34 +01:00
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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2014-09-03 13:42:59 +02:00
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system.physmem.numWrRetry 9 # Number of times write queue was full causing retry
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2014-09-20 23:18:53 +02:00
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system.physmem.totGap 1859033424000 # Total gap between requests
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2013-11-01 16:56:34 +01:00
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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2014-09-20 23:18:53 +02:00
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system.physmem.readPktSize::6 404091 # Read request sizes (log2)
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2013-11-01 16:56:34 +01:00
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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2014-09-20 23:18:53 +02:00
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system.physmem.writePktSize::6 117490 # Write request sizes (log2)
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2014-09-03 13:42:59 +02:00
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system.physmem.rdQLenPdf::0 315071 # What read queue length does an incoming req see
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2014-09-20 23:18:53 +02:00
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system.physmem.rdQLenPdf::1 37620 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 42963 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 8182 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 59 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 8 # What read queue length does an incoming req see
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2014-09-03 13:42:59 +02:00
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system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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2013-11-01 16:56:34 +01:00
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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2012-10-25 19:14:42 +02:00
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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2014-03-23 16:12:19 +01:00
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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2014-09-20 23:18:53 +02:00
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system.physmem.wrQLenPdf::15 1544 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 2141 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 3054 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 4174 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 5440 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 6763 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 7142 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 8408 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 8810 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 9005 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 8758 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 8976 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 7859 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 7939 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 6211 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 6103 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 6088 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 5604 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 243 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 171 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 158 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 154 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 160 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 126 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 113 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 117 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 141 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 120 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 129 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 155 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 167 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 146 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 136 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 137 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 88 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 88 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 84 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 87 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 95 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 92 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 84 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 92 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 82 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 56 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 52 # What write queue length does an incoming req see
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|
|
system.physmem.wrQLenPdf::61 32 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::62 19 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::63 22 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.bytesPerActivate::samples 61280 # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::mean 544.521149 # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::gmean 334.160448 # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::stdev 418.029082 # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::0-127 13483 22.00% 22.00% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::128-255 10372 16.93% 38.93% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::256-383 4758 7.76% 46.69% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::384-511 2785 4.54% 51.24% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::512-639 2293 3.74% 54.98% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::640-767 1673 2.73% 57.71% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::768-895 1477 2.41% 60.12% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::896-1023 1592 2.60% 62.72% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::1024-1151 22847 37.28% 100.00% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::total 61280 # Bytes accessed per row activation
|
|
|
|
|
system.physmem.rdPerTurnAround::samples 5232 # Reads before turning the bus around for writes
|
|
|
|
|
system.physmem.rdPerTurnAround::mean 77.198394 # Reads before turning the bus around for writes
|
|
|
|
|
system.physmem.rdPerTurnAround::stdev 2919.153555 # Reads before turning the bus around for writes
|
|
|
|
|
system.physmem.rdPerTurnAround::0-8191 5229 99.94% 99.94% # Reads before turning the bus around for writes
|
2014-09-03 13:42:59 +02:00
|
|
|
system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
|
|
|
|
|
system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
|
|
|
|
|
system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
|
2014-09-20 23:18:53 +02:00
|
|
|
system.physmem.rdPerTurnAround::total 5232 # Reads before turning the bus around for writes
|
|
|
|
|
system.physmem.wrPerTurnAround::samples 5232 # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::mean 22.451644 # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::gmean 19.067800 # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::stdev 21.155033 # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::16-19 4469 85.42% 85.42% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::20-23 138 2.64% 88.05% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::24-27 12 0.23% 88.28% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::28-31 232 4.43% 92.72% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::32-35 44 0.84% 93.56% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::36-39 2 0.04% 93.60% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::40-43 5 0.10% 93.69% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::44-47 10 0.19% 93.88% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::48-51 17 0.32% 94.21% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::52-55 2 0.04% 94.25% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::56-59 1 0.02% 94.27% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::60-63 2 0.04% 94.30% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::64-67 7 0.13% 94.44% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::68-71 3 0.06% 94.50% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::72-75 4 0.08% 94.57% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::76-79 1 0.02% 94.59% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::80-83 28 0.54% 95.13% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::84-87 15 0.29% 95.41% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::92-95 15 0.29% 95.70% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::96-99 171 3.27% 98.97% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::100-103 6 0.11% 99.08% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::108-111 1 0.02% 99.10% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::116-119 2 0.04% 99.14% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::120-123 2 0.04% 99.18% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::124-127 1 0.02% 99.20% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::128-131 5 0.10% 99.29% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::132-135 1 0.02% 99.31% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::136-139 6 0.11% 99.43% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::140-143 4 0.08% 99.50% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::144-147 11 0.21% 99.71% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::148-151 1 0.02% 99.73% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::152-155 2 0.04% 99.77% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::156-159 1 0.02% 99.79% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::160-163 1 0.02% 99.81% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::172-175 1 0.02% 99.83% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::176-179 1 0.02% 99.85% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::184-187 1 0.02% 99.87% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::224-227 7 0.13% 100.00% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::total 5232 # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.totQLat 3681492750 # Total ticks spent queuing
|
|
|
|
|
system.physmem.totMemAccLat 11254842750 # Total ticks spent from burst creation until serviced by the DRAM
|
|
|
|
|
system.physmem.totBusLat 2019560000 # Total ticks spent in databus transfers
|
|
|
|
|
system.physmem.avgQLat 9114.59 # Average queueing delay per DRAM burst
|
2013-11-01 16:56:34 +01:00
|
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
2014-09-20 23:18:53 +02:00
|
|
|
system.physmem.avgMemAccLat 27864.59 # Average memory access latency per DRAM burst
|
|
|
|
|
system.physmem.avgRdBW 13.91 # Average DRAM read bandwidth in MiByte/s
|
2013-11-01 16:56:34 +01:00
|
|
|
system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s
|
2014-09-03 13:42:59 +02:00
|
|
|
system.physmem.avgRdBWSys 13.91 # Average system read bandwidth in MiByte/s
|
2014-09-20 23:18:53 +02:00
|
|
|
system.physmem.avgWrBWSys 4.04 # Average system write bandwidth in MiByte/s
|
2013-11-01 16:56:34 +01:00
|
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
2014-09-03 13:42:59 +02:00
|
|
|
system.physmem.busUtil 0.14 # Data bus utilization in percentage
|
|
|
|
|
system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads
|
2013-11-01 16:56:34 +01:00
|
|
|
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
|
2014-09-20 23:18:53 +02:00
|
|
|
system.physmem.avgRdQLen 1.92 # Average read queue length when enqueuing
|
|
|
|
|
system.physmem.avgWrQLen 24.45 # Average write queue length when enqueuing
|
|
|
|
|
system.physmem.readRowHits 364830 # Number of row buffer hits during reads
|
|
|
|
|
system.physmem.writeRowHits 95269 # Number of row buffer hits during writes
|
|
|
|
|
system.physmem.readRowHitRate 90.32 # Row buffer hit rate for reads
|
|
|
|
|
system.physmem.writeRowHitRate 81.09 # Row buffer hit rate for writes
|
|
|
|
|
system.physmem.avgGap 3564227.65 # Average gap between requests
|
|
|
|
|
system.physmem.pageHitRate 88.24 # Row buffer hit rate, read and write combined
|
|
|
|
|
system.physmem.memoryStateTime::IDLE 1761056207000 # Time in different power states
|
|
|
|
|
system.physmem.memoryStateTime::REF 62077340000 # Time in different power states
|
2014-05-10 00:58:50 +02:00
|
|
|
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
2014-09-20 23:18:53 +02:00
|
|
|
system.physmem.memoryStateTime::ACT 35903990500 # Time in different power states
|
2014-05-10 00:58:50 +02:00
|
|
|
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
2014-09-20 23:18:53 +02:00
|
|
|
system.membus.trans_dist::ReadReq 296046 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::ReadResp 295957 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::WriteReq 9597 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::WriteResp 9597 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::Writeback 75938 # Transaction distribution
|
2014-09-03 13:42:59 +02:00
|
|
|
system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
|
2014-09-20 23:18:53 +02:00
|
|
|
system.membus.trans_dist::UpgradeReq 188 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::SCUpgradeReq 5 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::UpgradeResp 193 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::ReadExReq 115222 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::ReadExResp 115222 # Transaction distribution
|
2014-09-03 13:42:59 +02:00
|
|
|
system.membus.trans_dist::BadAddressError 89 # Transaction distribution
|
2014-09-20 23:18:53 +02:00
|
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33054 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884476 # Packet count per connected master and slave (bytes)
|
2014-09-03 13:42:59 +02:00
|
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 178 # Packet count per connected master and slave (bytes)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917708 # Packet count per connected master and slave (bytes)
|
2014-09-03 13:42:59 +02:00
|
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83292 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_count_system.iocache.mem_side::total 83292 # Packet count per connected master and slave (bytes)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.membus.pkt_count::total 1001000 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44140 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30720896 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30765036 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size::total 33425324 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.snoops 158 # Total snoops (count)
|
|
|
|
|
system.membus.snoop_fanout::samples 522030 # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::1 522030 100.00% 100.00% # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::total 522030 # Request fanout histogram
|
|
|
|
|
system.membus.reqLayer0.occupancy 31457000 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.membus.reqLayer1.occupancy 1484421249 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.membus.reqLayer2.occupancy 110500 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.membus.respLayer1.occupancy 3754388311 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
|
2014-09-03 13:42:59 +02:00
|
|
|
system.membus.respLayer2.occupancy 43151211 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
2013-08-19 09:52:36 +02:00
|
|
|
system.iocache.tags.replacements 41685 # number of replacements
|
2014-09-20 23:18:53 +02:00
|
|
|
system.iocache.tags.tagsinuse 1.260487 # Cycle average of tags in use
|
2013-08-19 09:52:36 +02:00
|
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
|
|
|
system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
|
|
|
|
|
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
2014-09-20 23:18:53 +02:00
|
|
|
system.iocache.tags.warmup_cycle 1709355301000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.iocache.tags.occ_blocks::tsunami.ide 1.260487 # Average occupied blocks per requestor
|
|
|
|
|
system.iocache.tags.occ_percent::tsunami.ide 0.078780 # Average percentage of cache occupancy
|
|
|
|
|
system.iocache.tags.occ_percent::total 0.078780 # Average percentage of cache occupancy
|
2014-01-24 22:29:33 +01:00
|
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
|
|
|
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
|
|
|
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
2014-09-20 23:18:53 +02:00
|
|
|
system.iocache.tags.tag_accesses 376213 # Number of tag accesses
|
|
|
|
|
system.iocache.tags.data_accesses 376213 # Number of data accesses
|
2014-09-03 13:42:59 +02:00
|
|
|
system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits
|
|
|
|
|
system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
|
2014-09-20 23:18:53 +02:00
|
|
|
system.iocache.WriteInvalidateReq_misses::tsunami.ide 86 # number of WriteInvalidateReq misses
|
|
|
|
|
system.iocache.WriteInvalidateReq_misses::total 86 # number of WriteInvalidateReq misses
|
2014-09-03 13:42:59 +02:00
|
|
|
system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses
|
|
|
|
|
system.iocache.demand_misses::total 173 # number of demand (read+write) misses
|
|
|
|
|
system.iocache.overall_misses::tsunami.ide 173 # number of overall misses
|
|
|
|
|
system.iocache.overall_misses::total 173 # number of overall misses
|
|
|
|
|
system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles
|
|
|
|
|
system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles
|
|
|
|
|
system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles
|
|
|
|
|
system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles
|
|
|
|
|
system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles
|
|
|
|
|
system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
|
2011-07-10 19:56:09 +02:00
|
|
|
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41638 # number of WriteInvalidateReq accesses(hits+misses)
|
|
|
|
|
system.iocache.WriteInvalidateReq_accesses::total 41638 # number of WriteInvalidateReq accesses(hits+misses)
|
2014-09-03 13:42:59 +02:00
|
|
|
system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses
|
|
|
|
|
system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses
|
|
|
|
|
system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses
|
|
|
|
|
system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
2014-09-20 23:18:53 +02:00
|
|
|
system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 0.002065 # miss rate for WriteInvalidateReq accesses
|
|
|
|
|
system.iocache.WriteInvalidateReq_miss_rate::total 0.002065 # miss rate for WriteInvalidateReq accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
2014-09-03 13:42:59 +02:00
|
|
|
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency
|
|
|
|
|
system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency
|
|
|
|
|
system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency
|
|
|
|
|
system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency
|
|
|
|
|
system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency
|
|
|
|
|
system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency
|
|
|
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2014-09-03 13:42:59 +02:00
|
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
2014-09-03 13:42:59 +02:00
|
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2014-09-03 13:42:59 +02:00
|
|
|
system.iocache.fast_writes 41552 # number of fast writes performed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
|
|
|
|
|
system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
|
2014-09-03 13:42:59 +02:00
|
|
|
system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses
|
|
|
|
|
system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses
|
|
|
|
|
system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses
|
|
|
|
|
system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses
|
|
|
|
|
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles
|
2014-09-20 23:18:53 +02:00
|
|
|
system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2529714027 # number of WriteInvalidateReq MSHR miss cycles
|
|
|
|
|
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2529714027 # number of WriteInvalidateReq MSHR miss cycles
|
2014-09-03 13:42:59 +02:00
|
|
|
system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles
|
|
|
|
|
system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
2014-09-20 23:18:53 +02:00
|
|
|
system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.997935 # mshr miss rate for WriteInvalidateReq accesses
|
|
|
|
|
system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.997935 # mshr miss rate for WriteInvalidateReq accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
2014-09-03 13:42:59 +02:00
|
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency
|
|
|
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency
|
2014-09-20 23:18:53 +02:00
|
|
|
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60880.680280 # average WriteInvalidateReq mshr miss latency
|
|
|
|
|
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60880.680280 # average WriteInvalidateReq mshr miss latency
|
2014-09-03 13:42:59 +02:00
|
|
|
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency
|
|
|
|
|
system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency
|
|
|
|
|
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency
|
|
|
|
|
system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency
|
2011-07-10 19:56:09 +02:00
|
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
|
|
|
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
|
|
|
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
|
|
|
|
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
|
|
|
|
|
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
|
|
|
|
|
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
|
|
|
|
|
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
|
|
|
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
|
|
|
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
|
|
|
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
|
|
|
|
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
|
|
|
|
|
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.branchPred.lookups 17804968 # Number of BP lookups
|
|
|
|
|
system.cpu.branchPred.condPredicted 15499600 # Number of conditional branches predicted
|
|
|
|
|
system.cpu.branchPred.condIncorrect 379466 # Number of conditional branches incorrect
|
|
|
|
|
system.cpu.branchPred.BTBLookups 11923628 # Number of BTB lookups
|
|
|
|
|
system.cpu.branchPred.BTBHits 5932721 # Number of BTB hits
|
2013-01-24 19:29:00 +01:00
|
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.branchPred.BTBHitPct 49.756005 # BTB Hit Percentage
|
|
|
|
|
system.cpu.branchPred.usedRAS 914118 # Number of times the RAS was used to get a target.
|
|
|
|
|
system.cpu.branchPred.RASInCorrect 21281 # Number of incorrect RAS predictions.
|
2014-01-24 22:29:33 +01:00
|
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
2009-04-09 07:21:30 +02:00
|
|
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
|
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
|
|
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.dtb.read_hits 10302215 # DTB read hits
|
|
|
|
|
system.cpu.dtb.read_misses 41309 # DTB read misses
|
|
|
|
|
system.cpu.dtb.read_acv 513 # DTB read access violations
|
|
|
|
|
system.cpu.dtb.read_accesses 965594 # DTB read accesses
|
|
|
|
|
system.cpu.dtb.write_hits 6646492 # DTB write hits
|
|
|
|
|
system.cpu.dtb.write_misses 9371 # DTB write misses
|
|
|
|
|
system.cpu.dtb.write_acv 419 # DTB write access violations
|
|
|
|
|
system.cpu.dtb.write_accesses 342338 # DTB write accesses
|
|
|
|
|
system.cpu.dtb.data_hits 16948707 # DTB hits
|
|
|
|
|
system.cpu.dtb.data_misses 50680 # DTB misses
|
|
|
|
|
system.cpu.dtb.data_acv 932 # DTB access violations
|
|
|
|
|
system.cpu.dtb.data_accesses 1307932 # DTB accesses
|
|
|
|
|
system.cpu.itb.fetch_hits 1774610 # ITB hits
|
|
|
|
|
system.cpu.itb.fetch_misses 34401 # ITB misses
|
|
|
|
|
system.cpu.itb.fetch_acv 653 # ITB acv
|
|
|
|
|
system.cpu.itb.fetch_accesses 1809011 # ITB accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
|
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
|
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
|
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
|
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
|
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.numCycles 118301061 # number of cpu cycles simulated
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
|
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.fetch.icacheStallCycles 29562966 # Number of cycles fetch is stalled on an Icache miss
|
|
|
|
|
system.cpu.fetch.Insts 78094807 # Number of instructions fetch has processed
|
|
|
|
|
system.cpu.fetch.Branches 17804968 # Number of branches that fetch encountered
|
|
|
|
|
system.cpu.fetch.predictedBranches 6846839 # Number of branches that fetch has predicted taken
|
|
|
|
|
system.cpu.fetch.Cycles 80553195 # Number of cycles fetch has run and was not squashing or blocked
|
|
|
|
|
system.cpu.fetch.SquashCycles 1252096 # Number of cycles fetch has spent squashing
|
|
|
|
|
system.cpu.fetch.TlbCycles 1416 # Number of cycles fetch has spent waiting for tlb
|
|
|
|
|
system.cpu.fetch.MiscStallCycles 27926 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
|
|
|
system.cpu.fetch.PendingTrapStallCycles 1649882 # Number of stall cycles due to pending traps
|
|
|
|
|
system.cpu.fetch.PendingQuiesceStallCycles 450417 # Number of stall cycles due to pending quiesce instructions
|
|
|
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 232 # Number of stall cycles due to full MSHR
|
|
|
|
|
system.cpu.fetch.CacheLines 9025532 # Number of cache lines fetched
|
|
|
|
|
system.cpu.fetch.IcacheSquashes 274121 # Number of outstanding Icache misses that were squashed
|
|
|
|
|
system.cpu.fetch.ItlbSquashes 3 # Number of outstanding ITLB misses that were squashed
|
|
|
|
|
system.cpu.fetch.rateDist::samples 112872082 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::mean 0.691888 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::stdev 2.011514 # Number of instructions fetched each cycle (Total)
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.fetch.rateDist::0 98296528 87.09% 87.09% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::1 933530 0.83% 87.91% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::2 1975700 1.75% 89.66% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::3 908755 0.81% 90.47% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::4 2800334 2.48% 92.95% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::5 638924 0.57% 93.52% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::6 725896 0.64% 94.16% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::7 1007040 0.89% 95.05% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::8 5585375 4.95% 100.00% # Number of instructions fetched each cycle (Total)
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.fetch.rateDist::total 112872082 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.branchRate 0.150506 # Number of branch fetches per cycle
|
|
|
|
|
system.cpu.fetch.rate 0.660136 # Number of inst fetches per cycle
|
|
|
|
|
system.cpu.decode.IdleCycles 24068860 # Number of cycles decode is idle
|
|
|
|
|
system.cpu.decode.BlockedCycles 76820836 # Number of cycles decode is blocked
|
|
|
|
|
system.cpu.decode.RunCycles 9500551 # Number of cycles decode is running
|
|
|
|
|
system.cpu.decode.UnblockCycles 1898196 # Number of cycles decode is unblocking
|
|
|
|
|
system.cpu.decode.SquashCycles 583638 # Number of cycles decode is squashing
|
|
|
|
|
system.cpu.decode.BranchResolved 588301 # Number of times decode resolved a branch
|
|
|
|
|
system.cpu.decode.BranchMispred 42850 # Number of times decode detected a branch misprediction
|
|
|
|
|
system.cpu.decode.DecodedInsts 68299285 # Number of instructions handled by decode
|
|
|
|
|
system.cpu.decode.SquashedInsts 133126 # Number of squashed instructions handled by decode
|
|
|
|
|
system.cpu.rename.SquashCycles 583638 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu.rename.IdleCycles 24994916 # Number of cycles rename is idle
|
|
|
|
|
system.cpu.rename.BlockCycles 47249741 # Number of cycles rename is blocking
|
|
|
|
|
system.cpu.rename.serializeStallCycles 20742683 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu.rename.RunCycles 10385328 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.UnblockCycles 8915774 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu.rename.RenamedInsts 65865702 # Number of instructions processed by rename
|
|
|
|
|
system.cpu.rename.ROBFullEvents 202022 # Number of times rename has blocked due to ROB full
|
|
|
|
|
system.cpu.rename.IQFullEvents 2036806 # Number of times rename has blocked due to IQ full
|
|
|
|
|
system.cpu.rename.LQFullEvents 141544 # Number of times rename has blocked due to LQ full
|
|
|
|
|
system.cpu.rename.SQFullEvents 4770005 # Number of times rename has blocked due to SQ full
|
|
|
|
|
system.cpu.rename.RenamedOperands 43944287 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu.rename.RenameLookups 79812474 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.int_rename_lookups 79631676 # Number of integer rename lookups
|
|
|
|
|
system.cpu.rename.fp_rename_lookups 168345 # Number of floating rename lookups
|
|
|
|
|
system.cpu.rename.CommittedMaps 38137411 # Number of HB maps that are committed
|
|
|
|
|
system.cpu.rename.UndoneMaps 5806868 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu.rename.serializingInsts 1690855 # count of serializing insts renamed
|
|
|
|
|
system.cpu.rename.tempSerializingInsts 241233 # count of temporary serializing insts renamed
|
|
|
|
|
system.cpu.rename.skidInsts 13548292 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu.memDep0.insertedLoads 10425085 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.memDep0.insertedStores 6927485 # Number of stores inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.memDep0.conflictingLoads 1490397 # Number of conflicting loads.
|
|
|
|
|
system.cpu.memDep0.conflictingStores 1054253 # Number of conflicting stores.
|
|
|
|
|
system.cpu.iq.iqInstsAdded 58626057 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 2139161 # Number of non-speculative instructions added to the IQ
|
|
|
|
|
system.cpu.iq.iqInstsIssued 57592696 # Number of instructions issued
|
|
|
|
|
system.cpu.iq.iqSquashedInstsIssued 51229 # Number of squashed instructions issued
|
|
|
|
|
system.cpu.iq.iqSquashedInstsExamined 7502337 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 3486338 # Number of squashed operands that are examined and possibly removed from graph
|
|
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 1478017 # Number of squashed non-spec instructions that were removed
|
|
|
|
|
system.cpu.iq.issued_per_cycle::samples 112872082 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::mean 0.510247 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::stdev 1.252928 # Number of insts issued each cycle
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::0 89394835 79.20% 79.20% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::1 10016384 8.87% 88.07% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::2 4304507 3.81% 91.89% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::3 2950730 2.61% 94.50% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::4 3082787 2.73% 97.23% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::5 1592384 1.41% 98.64% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::6 1013037 0.90% 99.54% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::7 395526 0.35% 99.89% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::8 121892 0.11% 100.00% # Number of insts issued each cycle
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::total 112872082 # Number of insts issued each cycle
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.iq.fu_full::IntAlu 212963 18.82% 18.82% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 18.82% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 18.82% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.82% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.82% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.82% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 18.82% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.82% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.82% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.82% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.82% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.82% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.82% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.82% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.82% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 18.82% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.82% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 18.82% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.82% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.82% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.82% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.82% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.82% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.82% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.82% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.82% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.82% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.82% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.82% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::MemRead 545078 48.16% 66.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::MemWrite 373836 33.03% 100.00% # attempts to use FU when none available
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.iq.FU_type_0::IntAlu 39097776 67.89% 67.90% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntMult 61804 0.11% 68.01% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.01% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatAdd 38376 0.07% 68.07% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.07% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.07% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.07% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemRead 10712581 18.60% 86.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 6722276 11.67% 98.35% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IprAccess 948961 1.65% 100.00% # Type of FU issued
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.iq.FU_type_0::total 57592696 # Type of FU issued
|
|
|
|
|
system.cpu.iq.rate 0.486832 # Inst issue rate
|
|
|
|
|
system.cpu.iq.fu_busy_cnt 1131877 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.019653 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 228528169 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 67952558 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 55916727 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 712410 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 334609 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 328997 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.int_alu_accesses 58334880 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.fp_alu_accesses 382407 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 639606 # Number of loads that had data forwarded from stores
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 1340629 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 4088 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 20047 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 553798 # Number of stores squashed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 18287 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 539247 # Number of times an access to memory failed due to the cache being blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.iew.iewSquashCycles 583638 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 44307486 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 616008 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 64468948 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 145079 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 10425085 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 6927485 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 1890835 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 42893 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 369751 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 20047 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 190429 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 410127 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 600556 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 57009373 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 10371242 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 583322 # Number of squashed instructions skipped in execute
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.iew.exec_nop 3703730 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.exec_refs 17042240 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 8981920 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 6670998 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 0.481901 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 56380366 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 56245724 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 28936691 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 40310167 # num instructions consuming a value
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.iew.wb_rate 0.475446 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.717851 # average fanout of values written-back
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.commit.commitSquashedInsts 8239182 # The number of squashed insts skipped by commit
|
|
|
|
|
system.cpu.commit.commitNonSpecStalls 661144 # The number of times commit has been forced to stall to communicate backwards
|
|
|
|
|
system.cpu.commit.branchMispredicts 548042 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 111437316 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 0.503568 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 1.455315 # Number of insts commited each cycle
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::0 91810154 82.39% 82.39% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 7802563 7.00% 89.39% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 4132031 3.71% 93.10% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 2155493 1.93% 95.03% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 1853584 1.66% 96.69% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 616181 0.55% 97.25% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 467348 0.42% 97.67% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 515869 0.46% 98.13% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 2084093 1.87% 100.00% # Number of insts commited each cycle
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::total 111437316 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committedInsts 56116260 # Number of instructions committed
|
|
|
|
|
system.cpu.commit.committedOps 56116260 # Number of ops (including micro ops) committed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.commit.refs 15458143 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.loads 9084456 # Number of loads committed
|
|
|
|
|
system.cpu.commit.membars 226334 # Number of memory barriers committed
|
|
|
|
|
system.cpu.commit.branches 8434463 # Number of branches committed
|
|
|
|
|
system.cpu.commit.fp_insts 324518 # Number of committed floating point instructions.
|
|
|
|
|
system.cpu.commit.int_insts 51967854 # Number of committed integer instructions.
|
|
|
|
|
system.cpu.commit.function_calls 739911 # Number of function calls committed.
|
|
|
|
|
system.cpu.commit.op_class_0::No_OpClass 3195933 5.70% 5.70% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::IntAlu 36178550 64.47% 70.17% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::IntMult 60663 0.11% 70.27% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.27% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::FloatAdd 38089 0.07% 70.34% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.34% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.34% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.34% # Class of committed instruction
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.commit.op_class_0::MemRead 9310790 16.59% 86.94% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::MemWrite 6379639 11.37% 98.31% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::IprAccess 948960 1.69% 100.00% # Class of committed instruction
|
2014-05-10 00:58:50 +02:00
|
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.commit.op_class_0::total 56116260 # Class of committed instruction
|
|
|
|
|
system.cpu.commit.bw_lim_events 2084093 # number cycles where commit BW limit reached
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.rob.rob_reads 173459156 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 130141826 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 576115 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 5428979 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.quiesceCycles 3599776298 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
|
|
|
system.cpu.committedInsts 52927600 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedOps 52927600 # Number of Ops (including micro ops) Simulated
|
|
|
|
|
system.cpu.cpi 2.235149 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 2.235149 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 0.447398 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 0.447398 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.int_regfile_reads 74648651 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 40584029 # number of integer regfile writes
|
|
|
|
|
system.cpu.fp_regfile_reads 166982 # number of floating regfile reads
|
|
|
|
|
system.cpu.fp_regfile_writes 167600 # number of floating regfile writes
|
|
|
|
|
system.cpu.misc_regfile_reads 2029015 # number of misc regfile reads
|
|
|
|
|
system.cpu.misc_regfile_writes 939371 # number of misc regfile writes
|
2011-07-10 19:56:09 +02:00
|
|
|
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
|
|
|
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
|
|
|
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
|
|
|
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
|
|
|
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
2012-05-09 20:52:14 +02:00
|
|
|
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
2011-07-10 19:56:09 +02:00
|
|
|
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
|
|
|
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
2012-05-09 20:52:14 +02:00
|
|
|
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
2011-07-10 19:56:09 +02:00
|
|
|
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
|
|
|
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
2012-05-09 20:52:14 +02:00
|
|
|
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
2011-07-10 19:56:09 +02:00
|
|
|
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
|
|
|
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
2012-05-09 20:52:14 +02:00
|
|
|
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
2011-07-10 19:56:09 +02:00
|
|
|
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
|
|
|
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
2012-05-09 20:52:14 +02:00
|
|
|
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
2011-07-10 19:56:09 +02:00
|
|
|
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
|
|
|
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
2012-05-09 20:52:14 +02:00
|
|
|
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
2011-07-10 19:56:09 +02:00
|
|
|
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
|
|
|
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
2012-05-09 20:52:14 +02:00
|
|
|
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
2011-07-10 19:56:09 +02:00
|
|
|
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
|
|
|
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
2012-05-09 20:52:14 +02:00
|
|
|
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
2011-07-10 19:56:09 +02:00
|
|
|
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
2012-05-09 20:52:14 +02:00
|
|
|
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
2011-07-10 19:56:09 +02:00
|
|
|
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
|
|
|
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
2013-05-30 18:54:18 +02:00
|
|
|
system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
|
|
|
|
|
system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
|
2014-09-20 23:18:53 +02:00
|
|
|
system.iobus.trans_dist::WriteReq 51063 # Transaction distribution
|
|
|
|
|
system.iobus.trans_dist::WriteResp 51149 # Transaction distribution
|
|
|
|
|
system.iobus.trans_dist::WriteInvalidateReq 86 # Transaction distribution
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5050 # Packet count per connected master and slave (bytes)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.iobus.pkt_count_system.bridge.master::total 33054 # Packet count per connected master and slave (bytes)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.iobus.pkt_count::total 116504 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20200 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::total 44140 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size::total 2705748 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.reqLayer0.occupancy 4661000 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.iobus.reqLayer29.occupancy 374547621 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.iobus.respLayer0.occupancy 23457000 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
2014-09-03 13:42:59 +02:00
|
|
|
system.iobus.respLayer1.occupancy 42014789 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 2147499 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 2147393 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::WriteReq 9597 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::WriteResp 9597 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::Writeback 842679 # Transaction distribution
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41561 # Transaction distribution
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 81 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 26 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 107 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 301934 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 301934 # Transaction distribution
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.toL2Bus.trans_dist::BadAddressError 89 # Transaction distribution
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2074254 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3686339 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_count::total 5760593 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66370688 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143907436 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_size::total 210278124 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.snoops 42060 # Total snoops (count)
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::samples 3326850 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::mean 1.012545 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.111298 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::1 3285116 98.75% 98.75% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::2 41734 1.25% 100.00% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::total 3326850 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 2498300996 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.toL2Bus.respLayer0.occupancy 1559854344 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.toL2Bus.respLayer1.occupancy 2189806641 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.icache.tags.replacements 1036451 # number of replacements
|
|
|
|
|
system.cpu.icache.tags.tagsinuse 509.402237 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.tags.total_refs 7937240 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.tags.sampled_refs 1036959 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.tags.avg_refs 7.654343 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.tags.warmup_cycle 26422155250 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 509.402237 # Average occupied blocks per requestor
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.994926 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.tags.occ_percent::total 0.994926 # Average percentage of cache occupancy
|
2014-01-24 22:29:33 +01:00
|
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id
|
|
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 299 # Occupied blocks per task id
|
2014-01-24 22:29:33 +01:00
|
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.icache.tags.tag_accesses 10062742 # Number of tag accesses
|
|
|
|
|
system.cpu.icache.tags.data_accesses 10062742 # Number of data accesses
|
|
|
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 7937241 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_hits::total 7937241 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits::cpu.inst 7937241 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_hits::total 7937241 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits::cpu.inst 7937241 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_hits::total 7937241 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1088289 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_misses::total 1088289 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses::cpu.inst 1088289 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_misses::total 1088289 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses::cpu.inst 1088289 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_misses::total 1088289 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 15130440508 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::total 15130440508 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 15130440508 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::total 15130440508 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 15130440508 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::total 15130440508 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 9025530 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::total 9025530 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses::cpu.inst 9025530 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_accesses::total 9025530 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::cpu.inst 9025530 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::total 9025530 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.120579 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.120579 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.120579 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::total 0.120579 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.120579 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::total 0.120579 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13902.961904 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 13902.961904 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13902.961904 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::total 13902.961904 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13902.961904 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::total 13902.961904 # average overall miss latency
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 4627 # number of cycles access was blocked
|
2014-05-10 00:58:50 +02:00
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.icache.blocked::no_mshrs 203 # number of cycles access was blocked
|
2014-05-10 00:58:50 +02:00
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 22.793103 # average number of cycles each access was blocked
|
2014-05-10 00:58:50 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 51077 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits::total 51077 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 51077 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits::total 51077 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 51077 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits::total 51077 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1037212 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses::total 1037212 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 1037212 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::total 1037212 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 1037212 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::total 1037212 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12445124401 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 12445124401 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12445124401 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::total 12445124401 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12445124401 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::total 12445124401 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114920 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114920 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114920 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.114920 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114920 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.114920 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11998.631332 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11998.631332 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11998.631332 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 11998.631332 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11998.631332 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 11998.631332 # average overall mshr miss latency
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.tags.replacements 338311 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tags.tagsinuse 65336.723406 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.tags.total_refs 2577279 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.tags.sampled_refs 403479 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.tags.avg_refs 6.387641 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.tags.warmup_cycle 5538371750 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 53740.150485 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 5341.296148 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 6255.276773 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.820010 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081502 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.095448 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.tags.occ_percent::total 0.996959 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65168 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 497 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3500 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3328 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2421 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55422 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994385 # Percentage of cache occupancy per task id
|
|
|
|
|
system.cpu.l2cache.tags.tag_accesses 26985288 # Number of tag accesses
|
|
|
|
|
system.cpu.l2cache.tags.data_accesses 26985288 # Number of data accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 1021912 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 829370 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::total 1851282 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::writebacks 842679 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::total 842679 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 33 # number of UpgradeReq hits
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_hits::total 33 # number of UpgradeReq hits
|
|
|
|
|
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 21 # number of SCUpgradeReq hits
|
|
|
|
|
system.cpu.l2cache.SCUpgradeReq_hits::total 21 # number of SCUpgradeReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 186572 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::total 186572 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.inst 1021912 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.data 1015942 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::total 2037854 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.inst 1021912 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.data 1015942 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::total 2037854 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 15130 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 273814 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::total 288944 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 48 # number of UpgradeReq misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_misses::total 48 # number of UpgradeReq misses
|
|
|
|
|
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 5 # number of SCUpgradeReq misses
|
|
|
|
|
system.cpu.l2cache.SCUpgradeReq_misses::total 5 # number of SCUpgradeReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 115362 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::total 115362 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.inst 15130 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.data 389176 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::total 404306 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.inst 15130 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.data 389176 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::total 404306 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1158124750 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17992143250 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 19150268000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 194993 # number of UpgradeReq miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::total 194993 # number of UpgradeReq miss cycles
|
|
|
|
|
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 69497 # number of SCUpgradeReq miss cycles
|
|
|
|
|
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 69497 # number of SCUpgradeReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9692879611 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 9692879611 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 1158124750 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 27685022861 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::total 28843147611 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 1158124750 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 27685022861 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::total 28843147611 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1037042 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 1103184 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::total 2140226 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 842679 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::total 842679 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 81 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 81 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 26 # number of SCUpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.SCUpgradeReq_accesses::total 26 # number of SCUpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 301934 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::total 301934 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 1037042 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.data 1405118 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::total 2442160 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 1037042 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.data 1405118 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::total 2442160 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014590 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248203 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.135006 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.592593 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.592593 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.192308 # miss rate for SCUpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.192308 # miss rate for SCUpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382077 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.382077 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014590 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.276970 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::total 0.165553 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014590 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.276970 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::total 0.165553 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76544.927297 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65709.362012 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 66276.745667 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4062.354167 # average UpgradeReq miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 4062.354167 # average UpgradeReq miss latency
|
|
|
|
|
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 13899.400000 # average SCUpgradeReq miss latency
|
|
|
|
|
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 13899.400000 # average SCUpgradeReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84021.424828 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84021.424828 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76544.927297 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71137.538957 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 71339.895057 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76544.927297 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71137.538957 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 71339.895057 # average overall miss latency
|
2012-10-15 14:09:54 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.writebacks::writebacks 75938 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.writebacks::total 75938 # number of writebacks
|
2012-10-15 14:09:54 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15129 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273814 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 288943 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 48 # number of UpgradeReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 48 # number of UpgradeReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 5 # number of SCUpgradeReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 5 # number of SCUpgradeReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115362 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 115362 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 15129 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 389176 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::total 404305 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 15129 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 389176 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::total 404305 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 967311000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14580972250 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15548283250 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 493045 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 493045 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 50005 # number of SCUpgradeReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 50005 # number of SCUpgradeReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8286916389 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8286916389 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 967311000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22867888639 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 23835199639 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 967311000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22867888639 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 23835199639 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333507000 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333507000 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1884436000 # number of WriteReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1884436000 # number of WriteReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3217943000 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3217943000 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014589 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248203 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.135006 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.592593 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.592593 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.192308 # mshr miss rate for SCUpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.192308 # mshr miss rate for SCUpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382077 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382077 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014589 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.276970 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.165552 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014589 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.276970 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.165552 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63937.537180 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 53251.375934 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53810.901285 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10271.770833 # average UpgradeReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10271.770833 # average UpgradeReq mshr miss latency
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71834.021506 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71834.021506 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63937.537180 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58759.760723 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58953.511925 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63937.537180 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58759.760723 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58953.511925 # average overall mshr miss latency
|
2012-10-15 14:09:54 +02:00
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.dcache.tags.replacements 1404516 # number of replacements
|
|
|
|
|
system.cpu.dcache.tags.tagsinuse 511.994651 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.tags.total_refs 11877087 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.tags.sampled_refs 1405028 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.tags.avg_refs 8.453274 # Average number of references to valid blocks.
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.dcache.tags.warmup_cycle 25219000 # Cycle when the warmup percentage was hit.
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 511.994651 # Average occupied blocks per requestor
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.tags.occ_percent::total 0.999990 # Average percentage of cache occupancy
|
2014-01-24 22:29:33 +01:00
|
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 415 # Occupied blocks per task id
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id
|
|
|
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
|
2014-01-24 22:29:33 +01:00
|
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.dcache.tags.tag_accesses 63934725 # Number of tag accesses
|
|
|
|
|
system.cpu.dcache.tags.data_accesses 63934725 # Number of data accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 7287009 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::total 7287009 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 4187789 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::total 4187789 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 186297 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits::total 186297 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 215715 # number of StoreCondReq hits
|
|
|
|
|
system.cpu.dcache.StoreCondReq_hits::total 215715 # number of StoreCondReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits::cpu.data 11474798 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_hits::total 11474798 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits::cpu.data 11474798 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_hits::total 11474798 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1776849 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::total 1776849 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 1955456 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::total 1955456 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 23283 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_misses::total 23283 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu.dcache.StoreCondReq_misses::cpu.data 26 # number of StoreCondReq misses
|
|
|
|
|
system.cpu.dcache.StoreCondReq_misses::total 26 # number of StoreCondReq misses
|
|
|
|
|
system.cpu.dcache.demand_misses::cpu.data 3732305 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_misses::total 3732305 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses::cpu.data 3732305 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_misses::total 3732305 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 39503001495 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::total 39503001495 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 78159072008 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::total 78159072008 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 364867750 # number of LoadLockedReq miss cycles
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 364867750 # number of LoadLockedReq miss cycles
|
|
|
|
|
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 402005 # number of StoreCondReq miss cycles
|
|
|
|
|
system.cpu.dcache.StoreCondReq_miss_latency::total 402005 # number of StoreCondReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 117662073503 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::total 117662073503 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 117662073503 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::total 117662073503 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 9063858 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::total 9063858 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 6143245 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::total 6143245 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209580 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 209580 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 215741 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.StoreCondReq_accesses::total 215741 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.demand_accesses::cpu.data 15207103 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_accesses::total 15207103 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::cpu.data 15207103 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::total 15207103 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.196037 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.196037 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318310 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.318310 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111094 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.111094 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000121 # miss rate for StoreCondReq accesses
|
|
|
|
|
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000121 # miss rate for StoreCondReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.245432 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::total 0.245432 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.245432 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::total 0.245432 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22232.053199 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 22232.053199 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39969.742100 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 39969.742100 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15670.993858 # average LoadLockedReq miss latency
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15670.993858 # average LoadLockedReq miss latency
|
|
|
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15461.730769 # average StoreCondReq miss latency
|
|
|
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15461.730769 # average StoreCondReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 31525.310365 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::total 31525.310365 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31525.310365 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::total 31525.310365 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 3999248 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 1376 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_mshrs 180044 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 22 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.212615 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 62.545455 # average number of cycles each access was blocked
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.dcache.writebacks::writebacks 842679 # number of writebacks
|
|
|
|
|
system.cpu.dcache.writebacks::total 842679 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 680758 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 680758 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1664340 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 1664340 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5292 # number of LoadLockedReq MSHR hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 5292 # number of LoadLockedReq MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 2345098 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits::total 2345098 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 2345098 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::total 2345098 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1096091 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 1096091 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 291116 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 291116 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17991 # number of LoadLockedReq MSHR misses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::total 17991 # number of LoadLockedReq MSHR misses
|
|
|
|
|
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 26 # number of StoreCondReq MSHR misses
|
|
|
|
|
system.cpu.dcache.StoreCondReq_mshr_misses::total 26 # number of StoreCondReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 1387207 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::total 1387207 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 1387207 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::total 1387207 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27515724784 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 27515724784 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11792803134 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 11792803134 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 204517750 # number of LoadLockedReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 204517750 # number of LoadLockedReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 349995 # number of StoreCondReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 349995 # number of StoreCondReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 39308527918 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 39308527918 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 39308527918 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 39308527918 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423597000 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423597000 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1999614498 # number of WriteReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1999614498 # number of WriteReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3423211498 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::total 3423211498 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120930 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120930 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047388 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047388 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085843 # mshr miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085843 # mshr miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000121 # mshr miss rate for StoreCondReq accesses
|
|
|
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000121 # mshr miss rate for StoreCondReq accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091221 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.091221 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091221 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.091221 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25103.503983 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25103.503983 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40508.948783 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40508.948783 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11367.781113 # average LoadLockedReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11367.781113 # average LoadLockedReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13461.346154 # average StoreCondReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13461.346154 # average StoreCondReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28336.454414 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 28336.454414 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28336.454414 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 28336.454414 # average overall mshr miss latency
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2008-10-21 01:00:07 +02:00
|
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.kern.inst.quiesce 6442 # number of quiesce instructions executed
|
|
|
|
|
system.cpu.kern.inst.hwrei 210986 # number of hwrei instructions executed
|
|
|
|
|
system.cpu.kern.ipl_count::0 74656 40.97% 40.97% # number of times we switched to this ipl
|
2012-10-15 14:09:54 +02:00
|
|
|
system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl
|
|
|
|
|
system.cpu.kern.ipl_count::31 105550 57.93% 100.00% # number of times we switched to this ipl
|
|
|
|
|
system.cpu.kern.ipl_count::total 182216 # number of times we switched to this ipl
|
|
|
|
|
system.cpu.kern.ipl_good::0 73289 49.32% 49.32% # number of times we switched to this ipl from a different ipl
|
2012-10-15 14:09:54 +02:00
|
|
|
system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl
|
|
|
|
|
system.cpu.kern.ipl_good::31 73289 49.32% 100.00% # number of times we switched to this ipl from a different ipl
|
|
|
|
|
system.cpu.kern.ipl_good::total 148588 # number of times we switched to this ipl from a different ipl
|
|
|
|
|
system.cpu.kern.ipl_ticks::0 1817327743500 97.76% 97.76% # number of cycles we spent at this ipl
|
|
|
|
|
system.cpu.kern.ipl_ticks::21 61881000 0.00% 97.76% # number of cycles we spent at this ipl
|
|
|
|
|
system.cpu.kern.ipl_ticks::22 521765000 0.03% 97.79% # number of cycles we spent at this ipl
|
|
|
|
|
system.cpu.kern.ipl_ticks::31 41126450000 2.21% 100.00% # number of cycles we spent at this ipl
|
|
|
|
|
system.cpu.kern.ipl_ticks::total 1859037839500 # number of cycles we spent at this ipl
|
|
|
|
|
system.cpu.kern.ipl_used::0 0.981689 # fraction of swpipl calls that actually changed the ipl
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
|
|
|
|
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.kern.ipl_used::31 0.694353 # fraction of swpipl calls that actually changed the ipl
|
|
|
|
|
system.cpu.kern.ipl_used::total 0.815450 # fraction of swpipl calls that actually changed the ipl
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.kern.syscall::total 326 # number of syscalls executed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
|
|
|
|
|
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
|
|
|
|
|
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
|
|
|
|
|
system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.kern.callpal::swpctx 4178 2.18% 2.18% # number of callpals executed
|
2012-10-15 14:09:54 +02:00
|
|
|
system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed
|
2012-09-10 17:57:37 +02:00
|
|
|
system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.kern.callpal::swpipl 175101 91.22% 93.43% # number of callpals executed
|
|
|
|
|
system.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed
|
2012-10-15 14:09:54 +02:00
|
|
|
system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed
|
2012-09-10 17:57:37 +02:00
|
|
|
system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed
|
2012-10-15 14:09:54 +02:00
|
|
|
system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed
|
|
|
|
|
system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
|
|
|
|
|
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.kern.callpal::total 191946 # number of callpals executed
|
|
|
|
|
system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.kern.mode_switch::user 1740 # number of protection mode switches
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.kern.mode_good::kernel 1910
|
|
|
|
|
system.cpu.kern.mode_good::user 1740
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.kern.mode_good::idle 170
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.kern.mode_switch_good::kernel 0.326440 # fraction of useful protection mode switches
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.kern.mode_switch_good::total 0.394302 # fraction of useful protection mode switches
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.kern.mode_ticks::kernel 29097785000 1.57% 1.57% # number of ticks spent at the given mode
|
|
|
|
|
system.cpu.kern.mode_ticks::user 2655967500 0.14% 1.71% # number of ticks spent at the given mode
|
|
|
|
|
system.cpu.kern.mode_ticks::idle 1827284079000 98.29% 100.00% # number of ticks spent at the given mode
|
|
|
|
|
system.cpu.kern.swap_context 4179 # number of times the context was actually changed
|
2008-10-21 01:00:07 +02:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
