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gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt

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Stats: Back out broken update.
2011-02-08 04:23:11 +01:00
---------- Begin Simulation Statistics ----------
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
sim_seconds 2.616230 # Number of seconds simulated
sim_ticks 2616229847000 # Number of ticks simulated
final_tick 2616229847000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
Stats: Back out broken update.
2011-02-08 04:23:11 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
host_inst_rate 375445 # Simulator instruction rate (inst/s)
host_op_rate 477768 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 16316419265 # Simulator tick rate (ticks/s)
host_mem_usage 464828 # Number of bytes of host memory used
host_seconds 160.34 # Real time elapsed on the host
sim_insts 60200042 # Number of instructions simulated
sim_ops 76606857 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.bytes_read::cpu.inst 703560 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9089944 # Number of bytes read from this memory
system.physmem.bytes_read::total 132477344 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 703560 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 703560 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3706304 # Number of bytes written to this memory
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.bytes_written::total 6722376 # Number of bytes written to this memory
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.num_reads::cpu.inst 17205 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 142066 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15494702 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 57911 # Number of write requests responded to by this memory
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.num_writes::total 811929 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 46893201 # Total read bandwidth from this memory (bytes/s)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.bw_read::cpu.inst 268921 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3474444 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 50636737 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 268921 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 268921 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1416658 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1152831 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2569490 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1416658 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 46893201 # Total bandwidth to/from this memory (bytes/s)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.bw_total::cpu.inst 268921 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4627275 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 53206227 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 15494702 # Number of read requests accepted
system.physmem.writeReqs 811929 # Number of write requests accepted
system.physmem.readBursts 15494702 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 811929 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 991533248 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 127680 # Total number of bytes read from write queue
system.physmem.bytesWritten 6729728 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 132477344 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 6722376 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 1995 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 706751 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 4516 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 967982 # Per bank write bursts
arm: Bump stats after FS config script update This patch updates the stats to reflect the change in kernel options needed for armv8 (but used for all FS regressions).
2014-02-19 13:59:46 +01:00
system.physmem.perBankRdBursts::1 967715 # Per bank write bursts
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.perBankRdBursts::2 967669 # Per bank write bursts
system.physmem.perBankRdBursts::3 967754 # Per bank write bursts
system.physmem.perBankRdBursts::4 974564 # Per bank write bursts
system.physmem.perBankRdBursts::5 968184 # Per bank write bursts
system.physmem.perBankRdBursts::6 967779 # Per bank write bursts
system.physmem.perBankRdBursts::7 967692 # Per bank write bursts
system.physmem.perBankRdBursts::8 968544 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.perBankRdBursts::9 968137 # Per bank write bursts
system.physmem.perBankRdBursts::10 967949 # Per bank write bursts
system.physmem.perBankRdBursts::11 967746 # Per bank write bursts
system.physmem.perBankRdBursts::12 967851 # Per bank write bursts
system.physmem.perBankRdBursts::13 967741 # Per bank write bursts
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.perBankRdBursts::14 967800 # Per bank write bursts
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.perBankRdBursts::15 967600 # Per bank write bursts
system.physmem.perBankWrBursts::0 6503 # Per bank write bursts
system.physmem.perBankWrBursts::1 6305 # Per bank write bursts
system.physmem.perBankWrBursts::2 6309 # Per bank write bursts
system.physmem.perBankWrBursts::3 6231 # Per bank write bursts
system.physmem.perBankWrBursts::4 6800 # Per bank write bursts
system.physmem.perBankWrBursts::5 6982 # Per bank write bursts
system.physmem.perBankWrBursts::6 6786 # Per bank write bursts
system.physmem.perBankWrBursts::7 6777 # Per bank write bursts
system.physmem.perBankWrBursts::8 7080 # Per bank write bursts
system.physmem.perBankWrBursts::9 6733 # Per bank write bursts
system.physmem.perBankWrBursts::10 6548 # Per bank write bursts
system.physmem.perBankWrBursts::11 6441 # Per bank write bursts
system.physmem.perBankWrBursts::12 6486 # Per bank write bursts
system.physmem.perBankWrBursts::13 6281 # Per bank write bursts
system.physmem.perBankWrBursts::14 6425 # Per bank write bursts
system.physmem.perBankWrBursts::15 6465 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.totGap 2616225486000 # Total gap between requests
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.physmem.readPktSize::2 6664 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::3 15335424 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.readPktSize::6 152614 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 754018 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.writePktSize::6 57911 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 1126567 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 970563 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 976518 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 1090618 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 986596 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1051326 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 2724005 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 2632042 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 3421723 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 136210 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 113171 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 104737 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 101252 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 19730 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 18895 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 18668 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 86 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.wrQLenPdf::15 3804 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 3835 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 6081 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 6095 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 6100 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 6096 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 6099 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 6095 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 6098 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 6095 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 6095 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 6095 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 6101 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 6096 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 6095 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 6094 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 6095 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 6094 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.bytesPerActivate::samples 1027354 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 971.683544 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 905.447521 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 204.224200 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 22943 2.23% 2.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 22460 2.19% 4.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 8461 0.82% 5.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 2563 0.25% 5.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2504 0.24% 5.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1783 0.17% 5.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 8706 0.85% 6.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 969 0.09% 6.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 956965 93.15% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1027354 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 6094 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 2542.286675 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 118884.715097 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-524287 6090 99.93% 99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2.09715e+06-2.62144e+06 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 6094 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 6094 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 17.255005 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 17.227328 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 0.967528 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 2261 37.10% 37.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17 29 0.48% 37.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 3794 62.26% 99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 9 0.15% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 6094 # Writes before turning the bus around for reads
system.physmem.totQLat 400062590250 # Total ticks spent queuing
system.physmem.totMemAccLat 690550846500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 77463535000 # Total ticks spent in databus transfers
system.physmem.avgQLat 25822.64 # Average queueing delay per DRAM burst
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.avgMemAccLat 44572.64 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 378.99 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.57 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 50.64 # Average system read bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBWSys 2.57 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 2.98 # Data bus utilization in percentage
system.physmem.busUtilRead 2.96 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.avgRdQLen 6.59 # Average read queue length when enqueuing
system.physmem.avgWrQLen 24.10 # Average write queue length when enqueuing
system.physmem.readRowHits 14482119 # Number of row buffer hits during reads
system.physmem.writeRowHits 88386 # Number of row buffer hits during writes
system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 84.03 # Row buffer hit rate for writes
system.physmem.avgGap 160439.36 # Average gap between requests
system.physmem.pageHitRate 93.41 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 2245273695250 # Time in different power states
system.physmem.memoryStateTime::REF 87361560000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 283591722250 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
system.membus.throughput 54122917 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 16546592 # Transaction distribution
system.membus.trans_dist::ReadResp 16546592 # Transaction distribution
arm: Bump stats after FS config script update This patch updates the stats to reflect the change in kernel options needed for armv8 (but used for all FS regressions).
2014-02-19 13:59:46 +01:00
system.membus.trans_dist::WriteReq 763385 # Transaction distribution
system.membus.trans_dist::WriteResp 763385 # Transaction distribution
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.membus.trans_dist::Writeback 57911 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4516 # Transaction distribution
system.membus.trans_dist::UpgradeResp 4516 # Transaction distribution
system.membus.trans_dist::ReadExReq 132219 # Transaction distribution
system.membus.trans_dist::ReadExResp 132219 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383090 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893535 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280487 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.membus.pkt_count::total 34951335 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390546 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16516328 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18914598 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.membus.tot_pkt_size::total 141597990 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 141597990 # Total data (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.membus.reqLayer0.occupancy 1206224000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.membus.reqLayer2.occupancy 3616500 # Layer occupancy (ticks)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks)
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.membus.reqLayer6.occupancy 17911182500 # Layer occupancy (ticks)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.membus.respLayer1.occupancy 4951111812 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.membus.respLayer2.occupancy 37928474750 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 1.4 # Layer utilization (%)
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iobus.throughput 47806938 # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq 16518786 # Transaction distribution
system.iobus.trans_dist::ReadResp 16518786 # Transaction distribution
arm: Bump stats after FS config script update This patch updates the stats to reflect the change in kernel options needed for armv8 (but used for all FS regressions).
2014-02-19 13:59:46 +01:00
system.iobus.trans_dist::WriteReq 8183 # Transaction distribution
system.iobus.trans_dist::WriteResp 8183 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 534 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iobus.pkt_count_system.bridge.master::total 2383090 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iobus.pkt_count::total 33053938 # Packet count per connected master and slave (bytes)
arm: Bump stats after FS config script update This patch updates the stats to reflect the change in kernel options needed for armv8 (but used for all FS regressions).
2014-02-19 13:59:46 +01:00
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1068 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iobus.tot_pkt_size_system.bridge.master::total 2390546 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iobus.tot_pkt_size::total 125073938 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 125073938 # Total data (bytes)
arm: Bump stats after FS config script update This patch updates the stats to reflect the change in kernel options needed for armv8 (but used for all FS regressions).
2014-02-19 13:59:46 +01:00
system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iobus.reqLayer1.occupancy 3978000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 534000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 527000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 15335424000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iobus.respLayer0.occupancy 2374907000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iobus.respLayer1.occupancy 38686102250 # Layer occupancy (ticks)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.dtb.read_hits 14996190 # DTB read hits
system.cpu.dtb.read_misses 7339 # DTB read misses
system.cpu.dtb.write_hits 11230344 # DTB write hits
system.cpu.dtb.write_misses 2214 # DTB write misses
Stats: Back out broken update.
2011-02-08 04:23:11 +01:00
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.dtb.flush_entries 3405 # Number of entries that have been flushed from TLB
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.dtb.prefetch_faults 192 # Number of TLB faults due to prefetch
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.dtb.read_accesses 15003529 # DTB read accesses
system.cpu.dtb.write_accesses 11232558 # DTB write accesses
Stats: Back out broken update.
2011-02-08 04:23:11 +01:00
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.dtb.hits 26226534 # DTB hits
system.cpu.dtb.misses 9553 # DTB misses
system.cpu.dtb.accesses 26236087 # DTB accesses
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.itb.inst_hits 61493913 # ITB inst hits
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.itb.inst_misses 4471 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.itb.flush_entries 2370 # Number of entries that have been flushed from TLB
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.itb.inst_accesses 61498384 # ITB inst accesses
system.cpu.itb.hits 61493913 # DTB hits
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.itb.misses 4471 # DTB misses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.itb.accesses 61498384 # DTB accesses
system.cpu.numCycles 5232459694 # number of cpu cycles simulated
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.committedInsts 60200042 # Number of instructions committed
system.cpu.committedOps 76606857 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 69208585 # Number of integer alu accesses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.num_func_calls 2140468 # number of times a function call or return occured
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.num_conditional_control_insts 7948679 # number of instructions that are conditional controls
system.cpu.num_int_insts 69208585 # number of integer instructions
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.num_fp_insts 10269 # number of float instructions
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.num_int_register_reads 401368270 # number of times the integer registers were read
system.cpu.num_int_register_writes 74518872 # number of times the integer registers were written
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.num_mem_refs 27394017 # number of memory refs
system.cpu.num_load_insts 15660224 # Number of load instructions
system.cpu.num_store_insts 11733793 # Number of store instructions
system.cpu.num_idle_cycles 4581582300.610249 # Number of idle cycles
system.cpu.num_busy_cycles 650877393.389751 # Number of busy cycles
system.cpu.not_idle_fraction 0.124392 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.875608 # Percentage of idle cycles
system.cpu.Branches 10308802 # Number of branches fetched
system.cpu.op_class::No_OpClass 28518 0.04% 0.04% # Class of executed instruction
system.cpu.op_class::IntAlu 50389316 64.68% 64.72% # Class of executed instruction
system.cpu.op_class::IntMult 87585 0.11% 64.83% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 64.83% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 64.83% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 64.83% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 64.83% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 64.83% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 64.83% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 64.83% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 64.83% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 64.83% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 64.83% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 64.83% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 64.83% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 64.83% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 64.83% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 64.83% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 64.83% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 64.83% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 64.83% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 64.83% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 64.83% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 64.83% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 64.83% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 64.83% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 2109 0.00% 64.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 64.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.84% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.84% # Class of executed instruction
system.cpu.op_class::MemRead 15660224 20.10% 84.94% # Class of executed instruction
system.cpu.op_class::MemWrite 11733793 15.06% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 77901545 # Class of executed instruction
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.kern.inst.arm 0 # number of arm instructions executed
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.kern.inst.quiesce 83017 # number of quiesce instructions executed
system.cpu.icache.tags.replacements 856351 # number of replacements
system.cpu.icache.tags.tagsinuse 510.866135 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 60637050 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 856863 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 70.766330 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 20005377250 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 510.866135 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.997785 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.997785 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::1 193 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 269 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.icache.tags.tag_accesses 62350776 # Number of tag accesses
system.cpu.icache.tags.data_accesses 62350776 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 60637050 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 60637050 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 60637050 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 60637050 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 60637050 # number of overall hits
system.cpu.icache.overall_hits::total 60637050 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 856863 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 856863 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 856863 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 856863 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 856863 # number of overall misses
system.cpu.icache.overall_misses::total 856863 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 11766560750 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 11766560750 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 11766560750 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 11766560750 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 11766560750 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 11766560750 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 61493913 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 61493913 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 61493913 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 61493913 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 61493913 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 61493913 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013934 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.013934 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.013934 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.013934 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.013934 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.013934 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13732.137751 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13732.137751 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13732.137751 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13732.137751 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13732.137751 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13732.137751 # average overall miss latency
Stats: Back out broken update.
2011-02-08 04:23:11 +01:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
Stats: Back out broken update.
2011-02-08 04:23:11 +01:00
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856863 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 856863 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 856863 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 856863 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 856863 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 856863 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10048829250 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 10048829250 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10048829250 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 10048829250 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10048829250 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 10048829250 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 441046000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 441046000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 441046000 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total 441046000 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013934 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013934 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013934 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.013934 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013934 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.013934 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11727.463142 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11727.463142 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11727.463142 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11727.463142 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11727.463142 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11727.463142 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.tags.replacements 62506 # number of replacements
system.cpu.l2cache.tags.tagsinuse 50753.322403 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1682121 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 127886 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 13.153285 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 2565374310000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 37717.253716 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.884318 # Average occupied blocks per requestor
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000703 # Average occupied blocks per requestor
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.tags.occ_blocks::cpu.inst 6993.225103 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 6038.958564 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.575520 # Average percentage of cache occupancy
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.106708 # Average percentage of cache occupancy
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.tags.occ_percent::cpu.data 0.092147 # Average percentage of cache occupancy
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.tags.occ_percent::total 0.774434 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.l2cache.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65376 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2163 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6647 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56517 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997559 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 17140869 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 17140869 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8713 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3537 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst 844650 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 369794 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1226694 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 595396 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 595396 # number of Writeback hits
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.ReadExReq_hits::cpu.data 113396 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 113396 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 8713 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 3537 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 844650 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 483190 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1340090 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 8713 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 3537 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 844650 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 483190 # number of overall hits
system.cpu.l2cache.overall_hits::total 1340090 # number of overall hits
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.ReadReq_misses::cpu.inst 10579 # number of ReadReq misses
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.ReadReq_misses::cpu.data 9809 # number of ReadReq misses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.ReadReq_misses::total 20395 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2902 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 2902 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 133833 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 133833 # number of ReadExReq misses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.demand_misses::cpu.inst 10579 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 143642 # number of demand (read+write) misses
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.l2cache.demand_misses::total 154228 # number of demand (read+write) misses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.overall_misses::cpu.inst 10579 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 143642 # number of overall misses
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.l2cache.overall_misses::total 154228 # number of overall misses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 305250 # number of ReadReq miss cycles
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 150000 # number of ReadReq miss cycles
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 743832250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 729584000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 1473871500 # number of ReadReq miss cycles
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 469980 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 469980 # number of UpgradeReq miss cycles
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9271605886 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 9271605886 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 305250 # number of demand (read+write) miss cycles
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 150000 # number of demand (read+write) miss cycles
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.demand_miss_latency::cpu.inst 743832250 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 10001189886 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 10745477386 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 305250 # number of overall miss cycles
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 150000 # number of overall miss cycles
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.overall_miss_latency::cpu.inst 743832250 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 10001189886 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 10745477386 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8718 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3539 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst 855229 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 379603 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1247089 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 595396 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 595396 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2928 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 2928 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 247229 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 247229 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8718 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 3539 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 855229 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 626832 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 1494318 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8718 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 3539 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 855229 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 626832 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 1494318 # number of overall (read+write) accesses
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000574 # miss rate for ReadReq accesses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000565 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012370 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025840 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.016354 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991120 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991120 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541332 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.541332 # miss rate for ReadExReq accesses
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000574 # miss rate for demand accesses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000565 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012370 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.229155 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.103210 # miss rate for demand accesses
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000574 # miss rate for overall accesses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000565 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012370 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.229155 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.103210 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 61050 # average ReadReq miss latency
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 75000 # average ReadReq miss latency
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70312.151432 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74379.039657 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 72266.315273 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 161.950379 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 161.950379 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69277.426987 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69277.426987 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 61050 # average overall miss latency
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 75000 # average overall miss latency
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70312.151432 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69625.805029 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 69672.675429 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 61050 # average overall miss latency
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 75000 # average overall miss latency
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70312.151432 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69625.805029 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 69672.675429 # average overall miss latency
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.writebacks::writebacks 57911 # number of writebacks
system.cpu.l2cache.writebacks::total 57911 # number of writebacks
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5 # number of ReadReq MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10579 # number of ReadReq MSHR misses
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9809 # number of ReadReq MSHR misses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.ReadReq_mshr_misses::total 20395 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2902 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 2902 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133833 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 133833 # number of ReadExReq MSHR misses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5 # number of demand (read+write) MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.demand_mshr_misses::cpu.inst 10579 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 143642 # number of demand (read+write) MSHR misses
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.l2cache.demand_mshr_misses::total 154228 # number of demand (read+write) MSHR misses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5 # number of overall MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.overall_mshr_misses::cpu.inst 10579 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 143642 # number of overall MSHR misses
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.l2cache.overall_mshr_misses::total 154228 # number of overall MSHR misses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 242750 # number of ReadReq MSHR miss cycles
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 125000 # number of ReadReq MSHR miss cycles
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 611350250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 606711500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1218429500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29025902 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29025902 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7597036114 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7597036114 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 242750 # number of demand (read+write) MSHR miss cycles
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 611350250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8203747614 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 8815465614 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 242750 # number of overall MSHR miss cycles
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 611350250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8203747614 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 8815465614 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 349718500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166664427750 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167014146250 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 16706100672 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16706100672 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 349718500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183370528422 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183720246922 # number of overall MSHR uncacheable cycles
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for ReadReq accesses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000565 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012370 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025840 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016354 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991120 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991120 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541332 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541332 # mshr miss rate for ReadExReq accesses
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for demand accesses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000565 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012370 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229155 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.103210 # mshr miss rate for demand accesses
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for overall accesses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000565 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012370 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229155 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.103210 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average ReadReq mshr miss latency
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57789.039607 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61852.533388 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59741.578818 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.033770 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.033770 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56765.043853 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56765.043853 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average overall mshr miss latency
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57789.039607 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57112.457457 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57158.658700 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average overall mshr miss latency
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57789.039607 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57112.457457 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57158.658700 # average overall mshr miss latency
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.dcache.tags.replacements 626320 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.875633 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 23655948 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 626832 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 37.738897 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 669376250 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.875633 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999757 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999757 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 105 # Occupied blocks per task id
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.dcache.tags.tag_accesses 97757952 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 97757952 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 13196101 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 13196101 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 9972757 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 9972757 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 236378 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 236378 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 247784 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 247784 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 23168858 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 23168858 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 23168858 # number of overall hits
system.cpu.dcache.overall_hits::total 23168858 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 368196 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 368196 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 250157 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 250157 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 11407 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 11407 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 618353 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 618353 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 618353 # number of overall misses
system.cpu.dcache.overall_misses::total 618353 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5410361250 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 5410361250 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 11271639016 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 11271639016 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 158326750 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 158326750 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 16682000266 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 16682000266 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 16682000266 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 16682000266 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 13564297 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 13564297 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 10222914 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 10222914 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247785 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 247785 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 247784 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 247784 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 23787211 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 23787211 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 23787211 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 23787211 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027144 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.027144 # miss rate for ReadReq accesses
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024470 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.024470 # miss rate for WriteReq accesses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046036 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046036 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.025995 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.025995 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.025995 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.025995 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14694.242333 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14694.242333 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45058.259477 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 45058.259477 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13879.788726 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13879.788726 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 26978.118107 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 26978.118107 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 26978.118107 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 26978.118107 # average overall miss latency
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.dcache.writebacks::writebacks 595396 # number of writebacks
system.cpu.dcache.writebacks::total 595396 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368196 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 368196 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250157 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 250157 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11407 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 11407 # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 618353 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 618353 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 618353 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 618353 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4671668750 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4671668750 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10721268984 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 10721268984 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135458250 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135458250 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15392937734 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 15392937734 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15392937734 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 15392937734 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182058578250 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182058578250 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26242925328 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26242925328 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208301503578 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 208301503578 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027144 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027144 # mshr miss rate for ReadReq accesses
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024470 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024470 # mshr miss rate for WriteReq accesses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046036 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046036 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025995 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.025995 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025995 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.025995 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12687.994302 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12687.994302 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42858.161011 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42858.161011 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11875.010958 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11875.010958 # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24893.447164 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 24893.447164 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24893.447164 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 24893.447164 # average overall mshr miss latency
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.toL2Bus.throughput 52982138 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 2454896 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 2454896 # Transaction distribution
arm: Bump stats after FS config script update This patch updates the stats to reflect the change in kernel options needed for armv8 (but used for all FS regressions).
2014-02-19 13:59:46 +01:00
system.cpu.toL2Bus.trans_dist::WriteReq 763385 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 763385 # Transaction distribution
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.toL2Bus.trans_dist::Writeback 595396 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 2928 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 2928 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 247229 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 247229 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1725354 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5749970 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12465 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27449 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 7515238 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54761180 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83637066 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14156 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 34872 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total 138447274 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 138447274 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 166176 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 3009006000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.toL2Bus.respLayer0.occupancy 1295477750 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.toL2Bus.respLayer1.occupancy 2533767938 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.toL2Bus.respLayer2.occupancy 8926000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.toL2Bus.respLayer3.occupancy 18731500 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iocache.tags.replacements 0 # number of replacements
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.iocache.tags.tag_accesses 0 # Number of tag accesses
system.iocache.tags.data_accesses 0 # Number of data accesses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1759698189250 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1759698189250 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1759698189250 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1759698189250 # number of overall MSHR uncacheable cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
Stats: Back out broken update.
2011-02-08 04:23:11 +01:00
---------- End Simulation Statistics ----------
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