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gem5/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt

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X86: Add o3 regressions in SE mode. Exclude bzip2 for now. It works, it just takes too long to run.
2011-02-05 09:16:09 +01:00
---------- Begin Simulation Statistics ----------
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
sim_seconds 0.062113 # Number of seconds simulated
sim_ticks 62113055500 # Number of ticks simulated
final_tick 62113055500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
X86: Add o3 regressions in SE mode. Exclude bzip2 for now. It works, it just takes too long to run.
2011-02-05 09:16:09 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
host_inst_rate 113198 # Simulator instruction rate (inst/s)
host_op_rate 199324 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 44503726 # Simulator tick rate (ticks/s)
host_mem_usage 454072 # Number of bytes of host memory used
host_seconds 1395.68 # Real time elapsed on the host
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
sim_insts 157988547 # Number of instructions simulated
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
sim_ops 278192464 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.bytes_read::cpu.inst 64896 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1883008 # Number of bytes read from this memory
system.physmem.bytes_read::total 1947904 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 64896 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 64896 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 10624 # Number of bytes written to this memory
system.physmem.bytes_written::total 10624 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1014 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 29422 # Number of read requests responded to by this memory
system.physmem.num_reads::total 30436 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 166 # Number of write requests responded to by this memory
system.physmem.num_writes::total 166 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 1044805 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 30315817 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 31360621 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1044805 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1044805 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 171043 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 171043 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 171043 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1044805 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 30315817 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 31531664 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 30436 # Number of read requests accepted
system.physmem.writeReqs 166 # Number of write requests accepted
system.physmem.readBursts 30436 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 166 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 1943680 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 4224 # Total number of bytes read from write queue
system.physmem.bytesWritten 9216 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 1947904 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 10624 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 66 # Number of DRAM read bursts serviced by the write queue
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.perBankRdBursts::0 1923 # Per bank write bursts
system.physmem.perBankRdBursts::1 2063 # Per bank write bursts
system.physmem.perBankRdBursts::2 2030 # Per bank write bursts
system.physmem.perBankRdBursts::3 1928 # Per bank write bursts
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.perBankRdBursts::4 2026 # Per bank write bursts
system.physmem.perBankRdBursts::5 1903 # Per bank write bursts
system.physmem.perBankRdBursts::6 1964 # Per bank write bursts
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.perBankRdBursts::7 1866 # Per bank write bursts
system.physmem.perBankRdBursts::8 1938 # Per bank write bursts
system.physmem.perBankRdBursts::9 1940 # Per bank write bursts
system.physmem.perBankRdBursts::10 1805 # Per bank write bursts
system.physmem.perBankRdBursts::11 1795 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.perBankRdBursts::12 1792 # Per bank write bursts
system.physmem.perBankRdBursts::13 1800 # Per bank write bursts
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.perBankRdBursts::14 1818 # Per bank write bursts
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.perBankRdBursts::15 1779 # Per bank write bursts
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.perBankWrBursts::0 15 # Per bank write bursts
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.perBankWrBursts::1 80 # Per bank write bursts
system.physmem.perBankWrBursts::2 11 # Per bank write bursts
system.physmem.perBankWrBursts::3 10 # Per bank write bursts
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.perBankWrBursts::4 7 # Per bank write bursts
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 13 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.perBankWrBursts::9 5 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.perBankWrBursts::10 3 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.totGap 62113012500 # Total gap between requests
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.readPktSize::6 30436 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.writePktSize::6 166 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 29887 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 372 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 84 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.wrQLenPdf::15 9 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 9 # What write queue length does an incoming req see
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.wrQLenPdf::17 9 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 9 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 9 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 9 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 9 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 8 # What write queue length does an incoming req see
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.bytesPerActivate::samples 2732 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 714.471449 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 512.855124 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 389.294613 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 368 13.47% 13.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 227 8.31% 21.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 131 4.80% 26.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 130 4.76% 31.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 109 3.99% 35.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 99 3.62% 38.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 107 3.92% 42.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 79 2.89% 45.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 1482 54.25% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 2732 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 8 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 3788.500000 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean 34.757307 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 10676.303052 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 7 87.50% 87.50% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::29696-30719 1 12.50% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 8 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 8 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 18 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.000000 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 8 100.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 8 # Writes before turning the bus around for reads
system.physmem.totQLat 135350500 # Total ticks spent queuing
system.physmem.totMemAccLat 704788000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 151850000 # Total ticks spent in databus transfers
system.physmem.avgQLat 4456.72 # Average queueing delay per DRAM burst
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.avgMemAccLat 23206.72 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 31.29 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.15 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 31.36 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.17 # Average system write bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.busUtil 0.25 # Data bus utilization in percentage
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.busUtilRead 0.24 # Data bus utilization in percentage for reads
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
system.physmem.avgWrQLen 11.89 # Average write queue length when enqueuing
system.physmem.readRowHits 27681 # Number of row buffer hits during reads
system.physmem.writeRowHits 96 # Number of row buffer hits during writes
system.physmem.readRowHitRate 91.15 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 57.83 # Row buffer hit rate for writes
system.physmem.avgGap 2029704.35 # Average gap between requests
system.physmem.pageHitRate 90.96 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 10931760 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 5964750 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 122311800 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 881280 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 4056783120 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 2875200840 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 34744599750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 41816673300 # Total energy per rank (pJ)
system.physmem_0.averagePower 673.255215 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 57785258250 # Time in different power states
system.physmem_0.memoryStateTime::REF 2074020000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem_0.memoryStateTime::ACT 2252296250 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem_1.actEnergy 9714600 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 5300625 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 114332400 # Energy for read commands per rank (pJ)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.writeEnergy 51840 # Energy for write commands per rank (pJ)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem_1.refreshEnergy 4056783120 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 3044489985 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 34596104250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 41826776820 # Total energy per rank (pJ)
system.physmem_1.averagePower 673.417815 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 57536988500 # Time in different power states
system.physmem_1.memoryStateTime::REF 2074020000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem_1.memoryStateTime::ACT 2500187750 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.branchPred.lookups 37409115 # Number of BP lookups
system.cpu.branchPred.condPredicted 37409115 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 796961 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 21404292 # Number of BTB lookups
system.cpu.branchPred.BTBHits 21297612 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.branchPred.BTBHitPct 99.501595 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 5520840 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 5370 # Number of incorrect RAS predictions.
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.workload.num_syscalls 444 # Number of system calls
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.numCycles 124226112 # number of cpu cycles simulated
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.fetch.icacheStallCycles 28235935 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 201516528 # Number of instructions fetch has processed
system.cpu.fetch.Branches 37409115 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 26818452 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 95078093 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1665601 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 765 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 13635 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles 38 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 27845177 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 203940 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 124161279 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.860308 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.369086 # Number of instructions fetched each cycle (Total)
X86: Add o3 regressions in SE mode. Exclude bzip2 for now. It works, it just takes too long to run.
2011-02-05 09:16:09 +01:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.fetch.rateDist::0 63245394 50.94% 50.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 3661074 2.95% 53.89% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 3505984 2.82% 56.71% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 5966145 4.81% 61.52% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 7636259 6.15% 67.67% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 5451035 4.39% 72.06% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 3359633 2.71% 74.76% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 2076013 1.67% 76.43% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 29259742 23.57% 100.00% # Number of instructions fetched each cycle (Total)
X86: Add o3 regressions in SE mode. Exclude bzip2 for now. It works, it just takes too long to run.
2011-02-05 09:16:09 +01:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.fetch.rateDist::total 124161279 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.301137 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.622175 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 13292806 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 63720296 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 36521548 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 9793829 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 832800 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 335002829 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 832800 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 18597256 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 8862328 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 16249 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 40799373 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 55053273 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 328652486 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 2589 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 765140 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 48300530 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 4998296 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 330629230 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 873051813 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 537695602 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 524 # Number of floating rename lookups
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.rename.UndoneMaps 51416483 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 478 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 478 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 66182076 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 106321382 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 36530805 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 49812358 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 8510426 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 325477303 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 2126 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 307989355 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 51384 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 46683880 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 68913858 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 1681 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 124161279 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.480559 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 2.127626 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iq.issued_per_cycle::0 30601082 24.65% 24.65% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 19574247 15.77% 40.41% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 16779908 13.51% 53.93% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 17045625 13.73% 67.65% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 15969415 12.86% 80.52% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 12663210 10.20% 90.72% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 5764205 4.64% 95.36% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 4169219 3.36% 98.72% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 1594368 1.28% 100.00% # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iq.issued_per_cycle::total 124161279 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iq.fu_full::IntAlu 316891 7.52% 7.52% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 7.52% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 7.52% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.52% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.52% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.52% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 7.52% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.52% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 7.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 7.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.52% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 3711549 88.13% 95.66% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 182770 4.34% 100.00% # attempts to use FU when none available
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.iq.FU_type_0::No_OpClass 33338 0.01% 0.01% # Type of FU issued
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iq.FU_type_0::IntAlu 175395413 56.95% 56.96% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 11214 0.00% 56.96% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 334 0.00% 56.96% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 40 0.00% 56.96% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.96% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.96% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.96% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.96% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.96% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 98514236 31.99% 88.95% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 34034780 11.05% 100.00% # Type of FU issued
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iq.FU_type_0::total 307989355 # Type of FU issued
system.cpu.iq.rate 2.479264 # Inst issue rate
system.cpu.iq.fu_busy_cnt 4211210 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.013673 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 744402178 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 372203676 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 305987015 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 405 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 719 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 146 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 312167028 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 199 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 58260510 # Number of loads that had data forwarded from stores
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iew.lsq.thread0.squashedLoads 15541997 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 57887 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 42363 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 5091053 # Number of stores squashed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iew.lsq.thread0.rescheduledLoads 3649 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 124471 # Number of times an access to memory failed due to the cache being blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iew.iewSquashCycles 832800 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 5705086 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 3056605 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 325479429 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 124396 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 106321382 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 36530805 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 465 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 2770 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 3059848 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 42363 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 401945 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 444615 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 846560 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 306916313 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 98157297 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1073042 # Number of squashed instructions skipped in execute
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iew.exec_refs 131977680 # number of memory reference insts executed
system.cpu.iew.exec_branches 31536553 # Number of branches executed
system.cpu.iew.exec_stores 33820383 # Number of stores executed
system.cpu.iew.exec_rate 2.470626 # Inst execution rate
system.cpu.iew.wb_sent 306317735 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 305987161 # cumulative count of insts written-back
system.cpu.iew.wb_producers 231581512 # num instructions producing a value
system.cpu.iew.wb_consumers 336076811 # num instructions consuming a value
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iew.wb_rate 2.463147 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.689073 # average fanout of values written-back
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.commit.commitSquashedInsts 47389031 # The number of squashed insts skipped by commit
x86 regressions: stats update due to new x87 instructions
2012-12-30 19:45:52 +01:00
system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.commit.branchMispredicts 797726 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 117712955 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 2.363312 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 3.086758 # Number of insts commited each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.commit.committed_per_cycle::0 53359699 45.33% 45.33% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 15949045 13.55% 58.88% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 10998829 9.34% 68.22% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 8750765 7.43% 75.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 1918688 1.63% 77.29% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1725778 1.47% 78.75% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 854994 0.73% 79.48% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 681396 0.58% 80.06% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 23473761 19.94% 100.00% # Number of insts commited each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.commit.committed_per_cycle::total 117712955 # Number of insts commited each cycle
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.commit.committedInsts 157988547 # Number of instructions committed
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.commit.refs 122219137 # Number of memory references committed
system.cpu.commit.loads 90779385 # Number of loads committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.membars 0 # Number of memory barriers committed
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.commit.branches 29309705 # Number of branches committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.fp_insts 40 # Number of committed floating point instructions.
test: update stats Update stats for recent changes. Mostly minor changes in register access stats due to addition of new cc register type and slightly different (and more accurate) classification of int vs. fp register accesses.
2013-10-16 16:44:12 +02:00
system.cpu.commit.int_insts 278169481 # Number of committed integer instructions.
x86, regressions: updates stats This is due to op class, function call, walker patches.
2013-05-21 18:41:27 +02:00
system.cpu.commit.function_calls 4237596 # Number of function calls committed.
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::No_OpClass 16695 0.01% 0.01% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 155945353 56.06% 56.06% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 10938 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 329 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 12 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 90779385 32.63% 88.70% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 31439752 11.30% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.commit.bw_lim_events 23473761 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 419820689 # The number of ROB reads
system.cpu.rob.rob_writes 657620446 # The number of ROB writes
system.cpu.timesIdled 598 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 64833 # Total number of cycles that the CPU has spent unscheduled due to idling
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.committedInsts 157988547 # Number of Instructions Simulated
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.cpi 0.786298 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.786298 # CPI: Total CPI of All Threads
system.cpu.ipc 1.271782 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.271782 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 493661924 # number of integer regfile reads
system.cpu.int_regfile_writes 240899982 # number of integer regfile writes
system.cpu.fp_regfile_reads 121 # number of floating regfile reads
system.cpu.fp_regfile_writes 99 # number of floating regfile writes
system.cpu.cc_regfile_reads 107697498 # number of cc regfile reads
system.cpu.cc_regfile_writes 64570083 # number of cc regfile writes
system.cpu.misc_regfile_reads 196298941 # number of misc regfile reads
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.tags.replacements 2072451 # number of replacements
system.cpu.dcache.tags.tagsinuse 4067.920590 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 68431233 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 2076547 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 32.954339 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 19749732250 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4067.920590 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.993145 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.993145 # Average percentage of cache occupancy
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 585 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 3383 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 128 # Occupied blocks per task id
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.tags.tag_accesses 144497109 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 144497109 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 37085404 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 37085404 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 31345829 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 31345829 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 68431233 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 68431233 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 68431233 # number of overall hits
system.cpu.dcache.overall_hits::total 68431233 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 2685125 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 2685125 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 93923 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 93923 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 2779048 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2779048 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2779048 # number of overall misses
system.cpu.dcache.overall_misses::total 2779048 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 32124036248 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 32124036248 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2977938994 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 2977938994 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 35101975242 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 35101975242 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 35101975242 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 35101975242 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 39770529 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 39770529 # number of ReadReq accesses(hits+misses)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.demand_accesses::cpu.data 71210281 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 71210281 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 71210281 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 71210281 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.067515 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.067515 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002987 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.002987 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.039026 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.039026 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.039026 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.039026 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11963.702341 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 11963.702341 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31706.174143 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 31706.174143 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 12630.935213 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 12630.935213 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 12630.935213 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 12630.935213 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 199096 # number of cycles access was blocked
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.blocked::no_mshrs 39942 # number of cycles access was blocked
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 4.984628 # average number of cycles each access was blocked
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.writebacks::writebacks 2066749 # number of writebacks
system.cpu.dcache.writebacks::total 2066749 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 690617 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 690617 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11883 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 11883 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 702500 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 702500 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 702500 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 702500 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994508 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1994508 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82040 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 82040 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2076548 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2076548 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2076548 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2076548 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23032838251 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 23032838251 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2765865745 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2765865745 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25798703996 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 25798703996 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25798703996 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 25798703996 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050150 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050150 # mshr miss rate for ReadReq accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002609 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002609 # mshr miss rate for WriteReq accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029161 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.029161 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029161 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.029161 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11548.130291 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11548.130291 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33713.624391 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33713.624391 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12423.841874 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12423.841874 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12423.841874 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12423.841874 # average overall mshr miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.tags.replacements 58 # number of replacements
system.cpu.icache.tags.tagsinuse 832.593358 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 27843840 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 1028 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 27085.447471 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.tags.occ_blocks::cpu.inst 832.593358 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.406540 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.406540 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 970 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 880 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.473633 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 55691382 # Number of tag accesses
system.cpu.icache.tags.data_accesses 55691382 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 27843840 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 27843840 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 27843840 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 27843840 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 27843840 # number of overall hits
system.cpu.icache.overall_hits::total 27843840 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1337 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1337 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1337 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1337 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1337 # number of overall misses
system.cpu.icache.overall_misses::total 1337 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 100311747 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 100311747 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 100311747 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 100311747 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 100311747 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 100311747 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 27845177 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 27845177 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 27845177 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 27845177 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 27845177 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 27845177 # number of overall (read+write) accesses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000048 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000048 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000048 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000048 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000048 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000048 # miss rate for overall accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75027.484667 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 75027.484667 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 75027.484667 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 75027.484667 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 75027.484667 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 75027.484667 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 601 # number of cycles access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 100.166667 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 309 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 309 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 309 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 309 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 309 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 309 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1028 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 1028 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 1028 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 1028 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1028 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1028 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 79616501 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 79616501 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 79616501 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 79616501 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 79616501 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 79616501 # number of overall MSHR miss cycles
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000037 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000037 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000037 # mshr miss rate for overall accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77447.958171 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77447.958171 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77447.958171 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 77447.958171 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77447.958171 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 77447.958171 # average overall mshr miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.tags.replacements 480 # number of replacements
system.cpu.l2cache.tags.tagsinuse 20677.307711 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 4029650 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 30419 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 132.471482 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.tags.occ_blocks::writebacks 19740.626067 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 685.734645 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 250.946999 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.602436 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020927 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.007658 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.631021 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29939 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 761 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1395 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27655 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.913666 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 33267098 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 33267098 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 1994043 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1994057 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 2066749 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 2066749 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 53083 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 53083 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 14 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 2047126 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2047140 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 14 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 2047126 # number of overall hits
system.cpu.l2cache.overall_hits::total 2047140 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 1014 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 426 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 1440 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 28996 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 28996 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 1014 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 29422 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 30436 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 1014 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 29422 # number of overall misses
system.cpu.l2cache.overall_misses::total 30436 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 78434000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32404750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 110838750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2126346500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 2126346500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 78434000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 2158751250 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 2237185250 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 78434000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 2158751250 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 2237185250 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1028 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1994469 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1995497 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 2066749 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 2066749 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 82079 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 82079 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 1028 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 2076548 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2077576 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 1028 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 2076548 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2077576 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.986381 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000214 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.000722 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.353269 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.353269 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.986381 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.014169 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.014650 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.986381 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.014169 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.014650 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77351.084813 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76067.488263 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 76971.354167 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73332.407918 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73332.407918 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77351.084813 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73372.009041 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 73504.575174 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77351.084813 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73372.009041 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 73504.575174 # average overall miss latency
X86 Regressions: Update stats due to introduction of TSO
2012-01-29 02:09:17 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
X86: Add o3 regressions in SE mode. Exclude bzip2 for now. It works, it just takes too long to run.
2011-02-05 09:16:09 +01:00
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
X86 Regressions: Update stats due to introduction of TSO
2012-01-29 02:09:17 +01:00
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
X86: Add o3 regressions in SE mode. Exclude bzip2 for now. It works, it just takes too long to run.
2011-02-05 09:16:09 +01:00
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.writebacks::writebacks 166 # number of writebacks
system.cpu.l2cache.writebacks::total 166 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1014 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 426 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 1440 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28996 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 28996 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1014 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 29422 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 30436 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1014 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 29422 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 30436 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 65771000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27116250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 92887250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1763882000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1763882000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65771000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1790998250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 1856769250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65771000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1790998250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 1856769250 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.986381 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000214 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000722 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353269 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353269 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.986381 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014169 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.014650 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.986381 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014169 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.014650 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64862.919132 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63653.169014 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64505.034722 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60831.907849 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60831.907849 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64862.919132 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60872.756781 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61005.692272 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64862.919132 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60872.756781 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61005.692272 # average overall mshr miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.toL2Bus.trans_dist::ReadReq 1995497 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 1995496 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 2066749 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 82079 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 82079 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2056 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219844 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 6221900 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 65792 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265170944 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 265236736 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.toL2Bus.snoop_fanout::samples 4144325 # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.toL2Bus.snoop_fanout::3 4144325 100.00% 100.00% # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.toL2Bus.snoop_fanout::total 4144325 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 4138911500 # Layer occupancy (ticks)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.toL2Bus.respLayer0.occupancy 1734248 # Layer occupancy (ticks)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.toL2Bus.respLayer1.occupancy 3121601499 # Layer occupancy (ticks)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.respLayer1.utilization 5.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.trans_dist::ReadReq 1440 # Transaction distribution
system.membus.trans_dist::ReadResp 1439 # Transaction distribution
system.membus.trans_dist::Writeback 166 # Transaction distribution
system.membus.trans_dist::ReadExReq 28996 # Transaction distribution
system.membus.trans_dist::ReadExResp 28996 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61037 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61037 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 61037 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1958464 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1958464 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 1958464 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.snoops 0 # Total snoops (count)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.snoop_fanout::samples 30602 # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.snoop_fanout::0 30602 100.00% 100.00% # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.snoop_fanout::total 30602 # Request fanout histogram
system.membus.reqLayer0.occupancy 42540000 # Layer occupancy (ticks)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.respLayer1.occupancy 160392250 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.3 # Layer utilization (%)
X86: Add o3 regressions in SE mode. Exclude bzip2 for now. It works, it just takes too long to run.
2011-02-05 09:16:09 +01:00
---------- End Simulation Statistics ----------
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