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gem5/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt

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X86: Add o3 regressions in SE mode. Exclude bzip2 for now. It works, it just takes too long to run.
2011-02-05 09:16:09 +01:00
---------- Begin Simulation Statistics ----------
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
sim_seconds 0.144471 # Number of seconds simulated
sim_ticks 144470654000 # Number of ticks simulated
final_tick 144470654000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
X86: Add o3 regressions in SE mode. Exclude bzip2 for now. It works, it just takes too long to run.
2011-02-05 09:16:09 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
host_inst_rate 75912 # Simulator instruction rate (inst/s)
host_op_rate 127236 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 83039301 # Simulator tick rate (ticks/s)
host_mem_usage 277792 # Number of bytes of host memory used
host_seconds 1739.79 # Real time elapsed on the host
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
sim_insts 132071192 # Number of instructions simulated
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
sim_ops 221362962 # Number of ops (including micro ops) simulated
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.bytes_read::cpu.inst 216768 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 124992 # Number of bytes read from this memory
system.physmem.bytes_read::total 341760 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 216768 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 216768 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 3387 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1953 # Number of read requests responded to by this memory
system.physmem.num_reads::total 5340 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1500429 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 865172 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2365602 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1500429 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1500429 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1500429 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 865172 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2365602 # Total bandwidth to/from this memory (bytes/s)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.physmem.readReqs 5340 # Total number of read requests accepted by DRAM controller
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
system.physmem.readBursts 5340 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.bytesRead 341760 # Total number of bytes read from memory
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.bytesWritten 0 # Total number of bytes written to memory
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.bytesConsumedRd 341760 # bytesRead derated as per pkt->getSize()
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.neitherReadNorWrite 152 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 286 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 358 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 449 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 359 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 325 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 326 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 398 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 381 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 337 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 280 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 229 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 276 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 207 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 464 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 383 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 282 # Track reads on a per bank basis
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.totGap 144470612000 # Total gap between requests
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.readPktSize::6 5340 # Categorize read packet sizes
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 0 # Categorize write packet sizes
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.rdQLenPdf::0 4308 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 868 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 144 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
x86, regressions: updates stats This is due to op class, function call, walker patches.
2013-05-21 18:41:27 +02:00
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.bytesPerActivate::samples 508 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 662.047244 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 229.931754 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 1294.319008 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-65 181 35.63% 35.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-129 78 15.35% 50.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-193 41 8.07% 59.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-257 18 3.54% 62.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-321 27 5.31% 67.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-385 9 1.77% 69.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-449 15 2.95% 72.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-513 11 2.17% 74.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-577 9 1.77% 76.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-641 6 1.18% 77.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-705 4 0.79% 78.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-769 6 1.18% 79.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-833 5 0.98% 80.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-897 4 0.79% 81.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-961 6 1.18% 82.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1025 5 0.98% 83.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1089 3 0.59% 84.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1153 3 0.59% 84.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1217 4 0.79% 85.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1281 1 0.20% 85.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1345 4 0.79% 86.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1409 4 0.79% 87.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1473 3 0.59% 87.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1537 1 0.20% 88.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1601 3 0.59% 88.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1729 1 0.20% 88.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1857 2 0.39% 89.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1921 6 1.18% 90.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1985 1 0.20% 90.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2049 1 0.20% 90.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2113 1 0.20% 91.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2177 1 0.20% 91.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2241 3 0.59% 91.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2305 2 0.39% 92.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2433 3 0.59% 92.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2497 1 0.20% 93.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2625 2 0.39% 93.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2689 1 0.20% 93.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2817 4 0.79% 94.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2881 3 0.59% 95.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3201 1 0.20% 95.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3393 2 0.39% 95.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3457 1 0.20% 95.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3521 2 0.39% 96.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3585 1 0.20% 96.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3649 1 0.20% 96.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4097 1 0.20% 96.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4161 1 0.20% 97.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4289 2 0.39% 97.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4481 1 0.20% 97.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4673 1 0.20% 97.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5313 1 0.20% 98.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5889 1 0.20% 98.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6401 1 0.20% 98.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6593 1 0.20% 98.62% # Bytes accessed per row activation
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.bytesPerActivate::6912-6913 1 0.20% 98.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8129 1 0.20% 99.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8193 5 0.98% 100.00% # Bytes accessed per row activation
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.bytesPerActivate::total 508 # Bytes accessed per row activation
system.physmem.totQLat 12730250 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 118864000 # Sum of mem lat for all requests
system.physmem.totBusLat 26700000 # Total cycles spent in databus access
system.physmem.totBankLat 79433750 # Total cycles spent in bank access
system.physmem.avgQLat 2383.94 # Average queueing delay per request
system.physmem.avgBankLat 14875.23 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
system.physmem.avgMemAccLat 22259.18 # Average memory access latency
x86, regressions: updates stats This is due to op class, function call, walker patches.
2013-05-21 18:41:27 +02:00
system.physmem.avgRdBW 2.37 # Average achieved read bandwidth in MB/s
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
x86, regressions: updates stats This is due to op class, function call, walker patches.
2013-05-21 18:41:27 +02:00
system.physmem.avgConsumedRdBW 2.37 # Average consumed read bandwidth in MB/s
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
x86, regressions: updates stats This is due to op class, function call, walker patches.
2013-05-21 18:41:27 +02:00
system.physmem.busUtil 0.02 # Data bus utilization in percentage
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.readRowHits 4832 # Number of row buffer hits during reads
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.readRowHitRate 90.49 # Row buffer hit rate for reads
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.avgGap 27054421.72 # Average gap between requests
system.membus.throughput 2365159 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 3810 # Transaction distribution
system.membus.trans_dist::ReadResp 3809 # Transaction distribution
system.membus.trans_dist::UpgradeReq 152 # Transaction distribution
system.membus.trans_dist::UpgradeResp 152 # Transaction distribution
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.trans_dist::ReadExReq 1530 # Transaction distribution
system.membus.trans_dist::ReadExResp 1530 # Transaction distribution
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10983 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 10983 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 10983 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 341696 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 341696 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 341696 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 341696 # Total data (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.membus.reqLayer0.occupancy 6922500 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.membus.respLayer1.occupancy 50657098 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.branchPred.lookups 18662810 # Number of BP lookups
system.cpu.branchPred.condPredicted 18662810 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1489054 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 11419999 # Number of BTB lookups
system.cpu.branchPred.BTBHits 10818987 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.branchPred.BTBHitPct 94.737197 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1313526 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 22992 # Number of incorrect RAS predictions.
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.workload.num_syscalls 400 # Number of system calls
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.numCycles 289223613 # number of cpu cycles simulated
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.fetch.icacheStallCycles 23462367 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 206597935 # Number of instructions fetch has processed
system.cpu.fetch.Branches 18662810 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 12132513 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 54232022 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 15527864 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 178098132 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 1461 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 8383 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 64 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 22359928 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 225896 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 269583947 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.268673 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.756592 # Number of instructions fetched each cycle (Total)
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.fetch.rateDist::0 216790408 80.42% 80.42% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 2847266 1.06% 81.47% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 2313368 0.86% 82.33% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 2651625 0.98% 83.31% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 3218833 1.19% 84.51% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 3390708 1.26% 85.77% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 3829918 1.42% 87.19% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 2557961 0.95% 88.14% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 31983860 11.86% 100.00% # Number of instructions fetched each cycle (Total)
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.fetch.rateDist::total 269583947 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.064527 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.714319 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 36913432 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 167057645 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 41544375 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 10286977 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 13781518 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 336085554 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 13781518 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 44957189 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 116645963 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 32240 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 42740267 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 51426770 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 329706442 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 10945 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 26120234 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 22717452 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 239 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 382540638 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 917473743 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 909278159 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 8195584 # Number of floating rename lookups
stats: Bump x86 stats This patch bumps the x86 stats to reflect the recent fixes.
2013-06-24 20:17:22 +02:00
system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.rename.UndoneMaps 123111188 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 2136 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 2172 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 105032755 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 84354587 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 30100906 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 58264869 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 19038031 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 322777816 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 4259 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 260629412 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 116539 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 101038886 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 209946848 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 3014 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 269583947 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.966784 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.343888 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.iq.issued_per_cycle::0 143351146 53.17% 53.17% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 55555603 20.61% 73.78% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 34178684 12.68% 86.46% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 19029881 7.06% 93.52% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 10872516 4.03% 97.55% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 4173623 1.55% 99.10% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 1820350 0.68% 99.78% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 470633 0.17% 99.95% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 131511 0.05% 100.00% # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.iq.issued_per_cycle::total 269583947 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.iq.fu_full::IntAlu 130095 4.79% 4.79% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 4.79% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 4.79% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.79% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.79% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.79% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 4.79% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.79% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 4.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 4.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.79% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 2285309 84.07% 88.85% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 303076 11.15% 100.00% # attempts to use FU when none available
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.iq.FU_type_0::No_OpClass 1210969 0.46% 0.46% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 162174415 62.22% 62.69% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 791156 0.30% 62.99% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 7035823 2.70% 65.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 1446634 0.56% 66.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.25% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 65423127 25.10% 91.35% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 22547288 8.65% 100.00% # Type of FU issued
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.iq.FU_type_0::total 260629412 # Type of FU issued
system.cpu.iq.rate 0.901135 # Inst issue rate
system.cpu.iq.fu_busy_cnt 2718480 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.010430 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 788786495 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 420497128 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 255267923 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 4891295 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 3603930 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 2350852 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 259675050 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 2461873 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 18886019 # Number of loads that had data forwarded from stores
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 27705000 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 26101 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 285579 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 9585192 # Number of stores squashed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.iew.lsq.thread0.rescheduledLoads 50399 # Number of loads that were rescheduled
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.iew.iewSquashCycles 13781518 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 85016114 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 5459108 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 322782075 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 133200 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 84354587 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 30100909 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 2090 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 2675714 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 13368 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 285579 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 639541 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 899945 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1539486 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 258853338 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 64649488 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1776074 # Number of squashed instructions skipped in execute
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.iew.exec_refs 86992429 # number of memory reference insts executed
system.cpu.iew.exec_branches 14274182 # Number of branches executed
system.cpu.iew.exec_stores 22342941 # Number of stores executed
system.cpu.iew.exec_rate 0.894994 # Inst execution rate
system.cpu.iew.wb_sent 258213659 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 257618775 # cumulative count of insts written-back
system.cpu.iew.wb_producers 206032066 # num instructions producing a value
system.cpu.iew.wb_consumers 369264105 # num instructions consuming a value
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.iew.wb_rate 0.890725 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.557953 # average fanout of values written-back
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.commit.commitSquashedInsts 101495618 # The number of squashed insts skipped by commit
x86 regressions: stats update due to new x87 instructions
2012-12-30 19:45:52 +01:00
system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.commit.branchMispredicts 1490324 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 255802429 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.865367 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.654211 # Number of insts commited each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.commit.committed_per_cycle::0 156431243 61.15% 61.15% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 57241672 22.38% 83.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 14031050 5.49% 89.02% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 12055371 4.71% 93.73% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 4173166 1.63% 95.36% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 2967121 1.16% 96.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 906774 0.35% 96.87% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 1044092 0.41% 97.28% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 6951940 2.72% 100.00% # Number of insts commited each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.commit.committed_per_cycle::total 255802429 # Number of insts commited each cycle
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.commit.committedInsts 132071192 # Number of instructions committed
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.commit.committedOps 221362962 # Number of ops (including micro ops) committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.commit.refs 77165304 # Number of memory references committed
system.cpu.commit.loads 56649587 # Number of loads committed
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.commit.membars 0 # Number of memory barriers committed
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.commit.branches 12326938 # Number of branches committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions.
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.commit.int_insts 220339553 # Number of committed integer instructions.
x86, regressions: updates stats This is due to op class, function call, walker patches.
2013-05-21 18:41:27 +02:00
system.cpu.commit.function_calls 797818 # Number of function calls committed.
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.commit.bw_lim_events 6951940 # number cycles where commit BW limit reached
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.rob.rob_reads 571709069 # The number of ROB reads
system.cpu.rob.rob_writes 659523764 # The number of ROB writes
system.cpu.timesIdled 5926858 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 19639666 # Total number of cycles that the CPU has spent unscheduled due to idling
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.committedInsts 132071192 # Number of Instructions Simulated
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.committedOps 221362962 # Number of Ops (including micro ops) Simulated
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.cpi 2.189907 # CPI: Cycles Per Instruction
system.cpu.cpi_total 2.189907 # CPI: Total CPI of All Threads
system.cpu.ipc 0.456640 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.456640 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 554085462 # number of integer regfile reads
system.cpu.int_regfile_writes 293886504 # number of integer regfile writes
system.cpu.fp_regfile_reads 3218743 # number of floating regfile reads
system.cpu.fp_regfile_writes 2010653 # number of floating regfile writes
system.cpu.misc_regfile_reads 133373003 # number of misc regfile reads
stats: Bump x86 stats This patch bumps the x86 stats to reflect the recent fixes.
2013-06-24 20:17:22 +02:00
system.cpu.misc_regfile_writes 1689 # number of misc regfile writes
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.toL2Bus.throughput 3891282 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 7235 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 7233 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 14 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 153 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 153 # Transaction distribution
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.trans_dist::ReadExReq 1537 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1537 # Transaction distribution
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13393 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4315 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 17708 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 423616 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128704 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total 552320 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.toL2Bus.data_through_bus 552320 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 9856 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 4483500 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.toL2Bus.respLayer0.occupancy 10832250 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.toL2Bus.respLayer1.occupancy 3515652 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.replacements 4654 # number of replacements
system.cpu.icache.tags.tagsinuse 1616.215170 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 22351029 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 6622 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 3375.268650 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1616.215170 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.789168 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.789168 # Average percentage of cache occupancy
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.icache.ReadReq_hits::cpu.inst 22351029 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 22351029 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 22351029 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 22351029 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 22351029 # number of overall hits
system.cpu.icache.overall_hits::total 22351029 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 8899 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 8899 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 8899 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 8899 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 8899 # number of overall misses
system.cpu.icache.overall_misses::total 8899 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 351537500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 351537500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 351537500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 351537500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 351537500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 351537500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 22359928 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 22359928 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 22359928 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 22359928 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 22359928 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 22359928 # number of overall (read+write) accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000398 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000398 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000398 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000398 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000398 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000398 # miss rate for overall accesses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39503.034049 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 39503.034049 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 39503.034049 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 39503.034049 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 39503.034049 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 39503.034049 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 913 # number of cycles access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 53.705882 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2125 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 2125 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 2125 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 2125 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 2125 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 2125 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6774 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 6774 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 6774 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 6774 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 6774 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 6774 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 261819250 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 261819250 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 261819250 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 261819250 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 261819250 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 261819250 # number of overall MSHR miss cycles
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000303 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000303 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000303 # mshr miss rate for overall accesses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 38650.612637 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 38650.612637 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 38650.612637 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 38650.612637 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 38650.612637 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 38650.612637 # average overall mshr miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 2537.222896 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 3276 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 3813 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.859166 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.tags.occ_blocks::writebacks 1.748933 # Average occupied blocks per requestor
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2223.089774 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 312.384188 # Average occupied blocks per requestor
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.tags.occ_percent::writebacks 0.000053 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.067843 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.009533 # Average percentage of cache occupancy
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.occ_percent::total 0.077430 # Average percentage of cache occupancy
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.ReadReq_hits::cpu.inst 3232 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 38 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 3270 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 14 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 14 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits
x86 regressions: stats update due to new x87 instructions
2012-12-30 19:45:52 +01:00
system.cpu.l2cache.ReadExReq_hits::cpu.data 7 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 7 # number of ReadExReq hits
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.demand_hits::cpu.inst 3232 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 45 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 3277 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 3232 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 45 # number of overall hits
system.cpu.l2cache.overall_hits::total 3277 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 3388 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 423 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 3811 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 152 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 152 # number of UpgradeReq misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 1530 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 1530 # number of ReadExReq misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.demand_misses::cpu.inst 3388 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 1953 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 5341 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 3388 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 1953 # number of overall misses
system.cpu.l2cache.overall_misses::total 5341 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 222562750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 30845000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 253407750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 96941500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 96941500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 222562750 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 127786500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 350349250 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 222562750 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 127786500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 350349250 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 6620 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 461 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 7081 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 14 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 14 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 153 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 153 # number of UpgradeReq accesses(hits+misses)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1537 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1537 # number of ReadExReq accesses(hits+misses)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.demand_accesses::cpu.inst 6620 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1998 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 8618 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 6620 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1998 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 8618 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.511782 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.917570 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.538201 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.993464 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.993464 # miss rate for UpgradeReq accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.995446 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.995446 # miss rate for ReadExReq accesses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.511782 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.977477 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.619749 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.511782 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.977477 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.619749 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65691.484652 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72919.621749 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 66493.768040 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 63360.457516 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 63360.457516 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65691.484652 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65430.875576 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 65596.189852 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65691.484652 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65430.875576 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 65596.189852 # average overall miss latency
x86 regressions: stats update due to new x87 instructions
2012-12-30 19:45:52 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3388 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 423 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 3811 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 152 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 152 # number of UpgradeReq MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1530 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 1530 # number of ReadExReq MSHR misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3388 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 1953 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 5341 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3388 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 1953 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 5341 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 179944250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25531000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 205475250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1520152 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1520152 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 77356000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 77356000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 179944250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 102887000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 282831250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 179944250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 102887000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 282831250 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.511782 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.917570 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.538201 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.993464 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.993464 # mshr miss rate for UpgradeReq accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995446 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995446 # mshr miss rate for ReadExReq accesses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.511782 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.977477 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.619749 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.511782 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.977477 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.619749 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53112.234357 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60356.973995 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53916.360535 # average ReadReq mshr miss latency
x86 regressions: stats update due to new x87 instructions
2012-12-30 19:45:52 +01:00
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50559.477124 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50559.477124 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53112.234357 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52681.515617 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52954.736941 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53112.234357 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52681.515617 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52954.736941 # average overall mshr miss latency
x86 regressions: stats update due to new x87 instructions
2012-12-30 19:45:52 +01:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.dcache.tags.replacements 56 # number of replacements
system.cpu.dcache.tags.tagsinuse 1433.333580 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 66124025 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1997 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 33111.680020 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 1433.333580 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.349935 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.349935 # Average percentage of cache occupancy
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.dcache.ReadReq_hits::cpu.data 45609763 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 45609763 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 20514039 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 20514039 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 66123802 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 66123802 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 66123802 # number of overall hits
system.cpu.dcache.overall_hits::total 66123802 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 934 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 934 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1692 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1692 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 2626 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2626 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2626 # number of overall misses
system.cpu.dcache.overall_misses::total 2626 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 55899820 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 55899820 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 106273652 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 106273652 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 162173472 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 162173472 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 162173472 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 162173472 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 45610697 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 45610697 # number of ReadReq accesses(hits+misses)
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.dcache.demand_accesses::cpu.data 66126428 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 66126428 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 66126428 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 66126428 # number of overall (read+write) accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000082 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000082 # miss rate for WriteReq accesses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.000040 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000040 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000040 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000040 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59849.914347 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 59849.914347 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62809.486998 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 62809.486998 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 61756.843869 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 61756.843869 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 61756.843869 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 61756.843869 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 228 # number of cycles access was blocked
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
x86, regressions: updates stats This is due to op class, function call, walker patches.
2013-05-21 18:41:27 +02:00
system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 76 # average number of cycles each access was blocked
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.dcache.writebacks::writebacks 14 # number of writebacks
system.cpu.dcache.writebacks::total 14 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 472 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 472 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 3 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 475 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 475 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 475 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 475 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 462 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 462 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1689 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1689 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2151 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2151 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2151 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2151 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31756250 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 31756250 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 102039098 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 102039098 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 133795348 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 133795348 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 133795348 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 133795348 # number of overall MSHR miss cycles
x86, regressions: updates stats This is due to op class, function call, walker patches.
2013-05-21 18:41:27 +02:00
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000082 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000082 # mshr miss rate for WriteReq accesses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000033 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000033 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000033 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000033 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68736.471861 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68736.471861 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60413.912374 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60413.912374 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62201.463505 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 62201.463505 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62201.463505 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 62201.463505 # average overall mshr miss latency
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
X86: Add o3 regressions in SE mode. Exclude bzip2 for now. It works, it just takes too long to run.
2011-02-05 09:16:09 +01:00
---------- End Simulation Statistics ----------
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