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gem5/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt

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ARM: Add regression tests
2010-07-27 07:03:44 +02:00
---------- Begin Simulation Statistics ----------
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
sim_seconds 0.517235 # Number of seconds simulated
sim_ticks 517235411000 # Number of ticks simulated
final_tick 517235411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
host_inst_rate 795879 # Simulator instruction rate (inst/s)
host_op_rate 955482 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1509341441 # Simulator tick rate (ticks/s)
host_mem_usage 314596 # Number of bytes of host memory used
host_seconds 342.69 # Real time elapsed on the host
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
sim_insts 272739285 # Number of instructions simulated
sim_ops 327433743 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.physmem.bytes_read::cpu.data 270272 # Number of bytes read from this memory
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.physmem.bytes_read::total 437248 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 166976 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 166976 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 2609 # Number of read requests responded to by this memory
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.physmem.num_reads::cpu.data 4223 # Number of read requests responded to by this memory
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.bw_read::cpu.inst 322824 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 522532 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 845356 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 322824 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 322824 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 322824 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 522532 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 845356 # Total bandwidth to/from this memory (bytes/s)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.trans_dist::ReadReq 3976 # Transaction distribution
system.membus.trans_dist::ReadResp 3976 # Transaction distribution
system.membus.trans_dist::ReadExReq 2856 # Transaction distribution
system.membus.trans_dist::ReadExResp 2856 # Transaction distribution
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13664 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 13664 # Packet count per connected master and slave (bytes)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 6833 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 6833 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 6833 # Request fanout histogram
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.membus.reqLayer0.occupancy 7260000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.membus.respLayer1.occupancy 61915000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
ARM: Update SE stats for TLB stats additions
2010-11-08 20:59:35 +01:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 191 # Number of system calls
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.numCycles 1034470822 # number of cpu cycles simulated
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.committedInsts 272739285 # Number of instructions committed
system.cpu.committedOps 327433743 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 258331537 # Number of integer alu accesses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.num_func_calls 12448615 # number of times a function call or return occured
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.num_conditional_control_insts 15799349 # number of instructions that are conditional controls
system.cpu.num_int_insts 258331537 # number of integer instructions
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.num_fp_insts 114216705 # number of float instructions
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.num_int_register_reads 1215888421 # number of times the integer registers were read
system.cpu.num_int_register_writes 162499693 # number of times the integer registers were written
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read
system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.num_cc_register_reads 1242915500 # number of times the CC registers were read
system.cpu.num_cc_register_writes 76361814 # number of times the CC registers were written
system.cpu.num_mem_refs 168107847 # number of memory refs
system.cpu.num_load_insts 85732248 # Number of load instructions
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.num_store_insts 82375599 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.num_busy_cycles 1034470822 # Number of busy cycles
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.Branches 30563502 # Number of branches fetched
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.op_class::IntAlu 104312543 31.82% 31.82% # Class of executed instruction
system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 6594343 2.01% 34.49% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 34.49% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction
system.cpu.op_class::MemRead 85732248 26.15% 74.87% # Class of executed instruction
system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Class of executed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.op_class::total 327812213 # Class of executed instruction
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.replacements 13796 # number of replacements
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.tags.tagsinuse 1766.007645 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 348644749 # Total number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks.
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.tags.avg_refs 22344.725309 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007645 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.862308 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.862308 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1524 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.882324 # Percentage of cache occupancy per task id
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.tags.tag_accesses 697336307 # Number of tag accesses
system.cpu.icache.tags.data_accesses 697336307 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 348644749 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 348644749 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 348644749 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 348644749 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 348644749 # number of overall hits
system.cpu.icache.overall_hits::total 348644749 # number of overall hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 15603 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses
system.cpu.icache.overall_misses::total 15603 # number of overall misses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.ReadReq_miss_latency::cpu.inst 312527500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 312527500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 312527500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 312527500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 312527500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 312527500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 348660352 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 348660352 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 348660352 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 348660352 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 348660352 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 348660352 # number of overall (read+write) accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20029.962187 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 20029.962187 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 20029.962187 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 20029.962187 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 20029.962187 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 20029.962187 # average overall miss latency
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15603 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 15603 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 15603 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281321500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 281321500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281321500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 281321500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281321500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 281321500 # number of overall MSHR miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18029.962187 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18029.962187 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18029.962187 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 18029.962187 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18029.962187 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 18029.962187 # average overall mshr miss latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.replacements 0 # number of replacements
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.tags.tagsinuse 3487.764987 # Cycle average of tags in use
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.total_refs 13310 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 2.726342 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.tags.occ_blocks::writebacks 341.623056 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2408.427143 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 737.714788 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.010426 # Average percentage of cache occupancy
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073499 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.022513 # Average percentage of cache occupancy
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.tags.occ_percent::total 0.106438 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.l2cache.tags.occ_task_id_blocks::1024 4882 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1232 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3543 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148987 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 176386 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 176386 # Number of data accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.ReadReq_hits::cpu.inst 12994 # number of ReadReq hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_hits::cpu.data 239 # number of ReadReq hits
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.ReadReq_hits::total 13233 # number of ReadReq hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.Writeback_hits::writebacks 998 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 998 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.demand_hits::cpu.inst 12994 # number of demand (read+write) hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_hits::cpu.data 255 # number of demand (read+write) hits
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.demand_hits::total 13249 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 12994 # number of overall hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_hits::cpu.data 255 # number of overall hits
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.overall_hits::total 13249 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 2609 # number of ReadReq misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_misses::cpu.data 1367 # number of ReadReq misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.ReadReq_misses::total 3976 # number of ReadReq misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 2856 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 2856 # number of ReadExReq misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.demand_misses::cpu.inst 2609 # number of demand (read+write) misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_misses::cpu.data 4223 # number of demand (read+write) misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.demand_misses::total 6832 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 2609 # number of overall misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_misses::cpu.data 4223 # number of overall misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.overall_misses::total 6832 # number of overall misses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 135778500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71271000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 207049500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 148649500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 148649500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 135778500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 219920500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 355699000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 135778500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 219920500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 355699000 # number of overall miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_accesses::cpu.inst 15603 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1606 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 17209 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 998 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 998 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 2872 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 2872 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 15603 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 4478 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 20081 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 15603 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 4478 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 20081 # number of overall (read+write) accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.167211 # miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.851183 # miss rate for ReadReq accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.ReadReq_miss_rate::total 0.231042 # miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994429 # miss rate for ReadExReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_miss_rate::total 0.994429 # miss rate for ReadExReq accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167211 # miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_miss_rate::cpu.data 0.943055 # miss rate for demand accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.demand_miss_rate::total 0.340222 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167211 # miss rate for overall accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_miss_rate::cpu.data 0.943055 # miss rate for overall accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.overall_miss_rate::total 0.340222 # miss rate for overall accesses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52042.353392 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52136.795903 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52074.823944 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52048.144258 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52048.144258 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52042.353392 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52076.841108 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52063.670960 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52042.353392 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52076.841108 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52063.670960 # average overall miss latency
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2609 # number of ReadReq MSHR misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1367 # number of ReadReq MSHR misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.ReadReq_mshr_misses::total 3976 # number of ReadReq MSHR misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2856 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 2856 # number of ReadExReq MSHR misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2609 # number of demand (read+write) MSHR misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_mshr_misses::cpu.data 4223 # number of demand (read+write) MSHR misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.demand_mshr_misses::total 6832 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2609 # number of overall MSHR misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_mshr_misses::cpu.data 4223 # number of overall MSHR misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104365000 # number of ReadReq MSHR miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54680000 # number of ReadReq MSHR miss cycles
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159045000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114243000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114243000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104365000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 168923000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 273288000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104365000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 168923000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 273288000 # number of overall MSHR miss cycles
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.851183 # mshr miss rate for ReadReq accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.231042 # mshr miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429 # mshr miss rate for ReadExReq accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for demand accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for overall accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for overall accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40001.916443 # average ReadReq mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40001.257545 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40001.050420 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40001.050420 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40001.916443 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.710395 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40001.170960 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40001.916443 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.710395 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40001.170960 # average overall mshr miss latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.dcache.tags.replacements 1332 # number of replacements
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.tags.tagsinuse 3078.445016 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks.
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445016 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.751573 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.751573 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.SoftPFReq_hits::cpu.data 54059 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 54059 # number of SoftPFReq hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.demand_hits::cpu.data 168283768 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 168283768 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 168337827 # number of overall hits
system.cpu.dcache.overall_hits::total 168337827 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1604 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1604 # number of ReadReq misses
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 4476 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses
system.cpu.dcache.overall_misses::total 4479 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 78354000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 78354000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 157425500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 157425500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 235779500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 235779500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 235779500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 235779500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses)
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.SoftPFReq_accesses::cpu.data 54062 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 54062 # number of SoftPFReq accesses(hits+misses)
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.demand_accesses::cpu.data 168288244 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 168288244 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 168342306 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 168342306 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000035 # miss rate for WriteReq accesses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000055 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.000055 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000027 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48849.127182 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 48849.127182 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54813.892758 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 54813.892758 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 52676.385165 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 52676.385165 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 52641.102925 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 52641.102925 # average overall miss latency
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 998 # number of writebacks
system.cpu.dcache.writebacks::total 998 # number of writebacks
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1603 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1603 # number of ReadReq MSHR misses
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 4475 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75108000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 75108000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151681500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 151681500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 159000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 159000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226789500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 226789500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226948500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 226948500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000055 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000055 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46854.647536 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46854.647536 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52813.892758 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52813.892758 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50679.217877 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 50679.217877 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50680.772666 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 50680.772666 # average overall mshr miss latency
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.trans_dist::ReadReq 17209 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 998 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31206 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9954 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 41160 # Packet count per connected master and slave (bytes)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 998592 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 1349056 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 21079 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::5 21079 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 21079 # Request fanout histogram
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.reqLayer0.occupancy 11537500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 23404500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
---------- End Simulation Statistics ----------
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