2012-08-28 20:30:25 +02:00
---------- Begin Simulation Statistics ----------
2016-04-09 18:13:40 +02:00
sim_seconds 2.832863 # Number of seconds simulated
2016-04-21 10:48:24 +02:00
sim_ticks 2832862976500 # Number of ticks simulated
final_tick 2832862976500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2012-08-28 20:30:25 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
2016-06-02 15:14:36 +02:00
host_inst_rate 104475 # Simulator instruction rate (inst/s)
host_op_rate 126719 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2616817312 # Simulator tick rate (ticks/s)
host_mem_usage 625044 # Number of bytes of host memory used
host_seconds 1082.56 # Real time elapsed on the host
2016-04-21 10:48:24 +02:00
sim_insts 113100501 # Number of instructions simulated
sim_ops 137180951 # Number of ops (including micro ops) simulated
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2016-04-09 18:13:40 +02:00
system.physmem.bytes_read::cpu.dtb.walker 1216 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory
2016-04-21 10:48:24 +02:00
system.physmem.bytes_read::cpu.inst 1320384 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9384040 # Number of bytes read from this memory
2014-11-12 15:05:25 +01:00
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
2016-04-21 10:48:24 +02:00
system.physmem.bytes_read::total 10706984 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1320384 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1320384 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 8026368 # Number of bytes written to this memory
2014-10-30 05:18:29 +01:00
system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
2016-04-21 10:48:24 +02:00
system.physmem.bytes_written::total 8043892 # Number of bytes written to this memory
2016-04-09 18:13:40 +02:00
system.physmem.num_reads::cpu.dtb.walker 19 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory
2016-04-21 10:48:24 +02:00
system.physmem.num_reads::cpu.inst 22878 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 147146 # Number of read requests responded to by this memory
2014-11-12 15:05:25 +01:00
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
2016-04-21 10:48:24 +02:00
system.physmem.num_reads::total 170064 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 125412 # Number of write requests responded to by this memory
2014-10-30 05:18:29 +01:00
system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
2016-04-21 10:48:24 +02:00
system.physmem.num_writes::total 129793 # Number of write requests responded to by this memory
2016-04-09 18:13:40 +02:00
system.physmem.bw_read::cpu.dtb.walker 429 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 136 # Total read bandwidth from this memory (bytes/s)
2016-04-21 10:48:24 +02:00
system.physmem.bw_read::cpu.inst 466095 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3312564 # Total read bandwidth from this memory (bytes/s)
2015-09-25 13:27:03 +02:00
system.physmem.bw_read::realview.ide 339 # Total read bandwidth from this memory (bytes/s)
2016-04-21 10:48:24 +02:00
system.physmem.bw_read::total 3779563 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 466095 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 466095 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2833306 # Write bandwidth from this memory (bytes/s)
2015-11-06 09:26:50 +01:00
system.physmem.bw_write::cpu.data 6186 # Write bandwidth from this memory (bytes/s)
2016-04-21 10:48:24 +02:00
system.physmem.bw_write::total 2839492 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 2833306 # Total bandwidth to/from this memory (bytes/s)
2016-04-09 18:13:40 +02:00
system.physmem.bw_total::cpu.dtb.walker 429 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 136 # Total bandwidth to/from this memory (bytes/s)
2016-04-21 10:48:24 +02:00
system.physmem.bw_total::cpu.inst 466095 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3318750 # Total bandwidth to/from this memory (bytes/s)
2015-09-25 13:27:03 +02:00
system.physmem.bw_total::realview.ide 339 # Total bandwidth to/from this memory (bytes/s)
2016-04-21 10:48:24 +02:00
system.physmem.bw_total::total 6619055 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 170065 # Number of read requests accepted
system.physmem.writeReqs 129793 # Number of write requests accepted
system.physmem.readBursts 170065 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 129793 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 10875840 # Total number of bytes read from DRAM
2016-04-09 18:13:40 +02:00
system.physmem.bytesReadWrQ 8320 # Total number of bytes read from write queue
2016-04-21 10:48:24 +02:00
system.physmem.bytesWritten 8056896 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 10707048 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 8043892 # Total written bytes from the system interface side
2016-04-09 18:13:40 +02:00
system.physmem.servicedByWrQ 130 # Number of DRAM read bursts serviced by the write queue
2015-09-25 13:27:03 +02:00
system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one
2016-02-10 10:08:27 +01:00
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
2016-04-21 10:48:24 +02:00
system.physmem.perBankRdBursts::0 11272 # Per bank write bursts
system.physmem.perBankRdBursts::1 10588 # Per bank write bursts
system.physmem.perBankRdBursts::2 10986 # Per bank write bursts
system.physmem.perBankRdBursts::3 11169 # Per bank write bursts
system.physmem.perBankRdBursts::4 12952 # Per bank write bursts
2016-04-09 18:13:40 +02:00
system.physmem.perBankRdBursts::5 9956 # Per bank write bursts
2016-04-21 10:48:24 +02:00
system.physmem.perBankRdBursts::6 10481 # Per bank write bursts
system.physmem.perBankRdBursts::7 10743 # Per bank write bursts
system.physmem.perBankRdBursts::8 10600 # Per bank write bursts
system.physmem.perBankRdBursts::9 10174 # Per bank write bursts
2016-04-09 18:13:40 +02:00
system.physmem.perBankRdBursts::10 10343 # Per bank write bursts
system.physmem.perBankRdBursts::11 9301 # Per bank write bursts
2016-04-21 10:48:24 +02:00
system.physmem.perBankRdBursts::12 10025 # Per bank write bursts
system.physmem.perBankRdBursts::13 11028 # Per bank write bursts
system.physmem.perBankRdBursts::14 10189 # Per bank write bursts
system.physmem.perBankRdBursts::15 10128 # Per bank write bursts
system.physmem.perBankWrBursts::0 8502 # Per bank write bursts
system.physmem.perBankWrBursts::1 7941 # Per bank write bursts
system.physmem.perBankWrBursts::2 8563 # Per bank write bursts
2016-04-09 18:13:40 +02:00
system.physmem.perBankWrBursts::3 8669 # Per bank write bursts
2016-04-21 10:48:24 +02:00
system.physmem.perBankWrBursts::4 7608 # Per bank write bursts
2016-04-09 18:13:40 +02:00
system.physmem.perBankWrBursts::5 7365 # Per bank write bursts
2016-04-21 10:48:24 +02:00
system.physmem.perBankWrBursts::6 7699 # Per bank write bursts
system.physmem.perBankWrBursts::7 7999 # Per bank write bursts
system.physmem.perBankWrBursts::8 7959 # Per bank write bursts
2016-04-09 18:13:40 +02:00
system.physmem.perBankWrBursts::9 7673 # Per bank write bursts
system.physmem.perBankWrBursts::10 7751 # Per bank write bursts
system.physmem.perBankWrBursts::11 6981 # Per bank write bursts
2016-04-21 10:48:24 +02:00
system.physmem.perBankWrBursts::12 7672 # Per bank write bursts
system.physmem.perBankWrBursts::13 8384 # Per bank write bursts
2016-04-09 18:13:40 +02:00
system.physmem.perBankWrBursts::14 7646 # Per bank write bursts
2016-04-21 10:48:24 +02:00
system.physmem.perBankWrBursts::15 7477 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
2016-04-21 10:48:24 +02:00
system.physmem.numWrRetry 20 # Number of times write queue was full causing retry
system.physmem.totGap 2832862744500 # Total gap between requests
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
2015-05-05 09:22:39 +02:00
system.physmem.readPktSize::2 542 # Read request sizes (log2)
2014-10-30 05:18:29 +01:00
system.physmem.readPktSize::3 14 # Read request sizes (log2)
2015-09-25 13:27:03 +02:00
system.physmem.readPktSize::4 2996 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2016-04-21 10:48:24 +02:00
system.physmem.readPktSize::6 166513 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
2014-10-30 05:18:29 +01:00
system.physmem.writePktSize::2 4381 # Write request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
2016-04-21 10:48:24 +02:00
system.physmem.writePktSize::6 125412 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 150612 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 16390 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 2189 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 728 # What read queue length does an incoming req see
2016-04-09 18:13:40 +02:00
system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see
2014-10-30 05:18:29 +01:00
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
2013-05-30 18:54:18 +02:00
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
2016-04-21 10:48:24 +02:00
system.physmem.wrQLenPdf::15 1890 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 2879 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 6620 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 6141 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 7081 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 6533 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 6367 # What write queue length does an incoming req see
2016-04-09 18:13:40 +02:00
system.physmem.wrQLenPdf::22 6633 # What write queue length does an incoming req see
2016-04-21 10:48:24 +02:00
system.physmem.wrQLenPdf::23 7195 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 6951 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 7619 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 8448 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 7506 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 7828 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 8947 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 7499 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 7258 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 7266 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 1259 # What write queue length does an incoming req see
2016-04-09 18:13:40 +02:00
system.physmem.wrQLenPdf::34 366 # What write queue length does an incoming req see
2016-04-21 10:48:24 +02:00
system.physmem.wrQLenPdf::35 262 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 216 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 208 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 208 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 170 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 174 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 175 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 114 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 189 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 191 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 107 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 106 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 106 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 125 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 131 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 120 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 102 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 95 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 150 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 88 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 79 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 78 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 70 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 57 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 38 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 50 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 28 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 58 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 61915 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 305.784899 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 180.937223 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 324.895489 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 23052 37.23% 37.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 14889 24.05% 61.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 6490 10.48% 71.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3653 5.90% 77.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2551 4.12% 81.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1649 2.66% 84.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1497 2.42% 86.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1106 1.79% 88.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 7028 11.35% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 61915 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 6142 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 27.666884 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 569.620654 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 6141 99.98% 99.98% # Reads before turning the bus around for writes
2015-09-25 13:27:03 +02:00
system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes
2016-04-21 10:48:24 +02:00
system.physmem.rdPerTurnAround::total 6142 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 6142 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 20.496418 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.503929 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 14.596363 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 5449 88.72% 88.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 115 1.87% 90.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 28 0.46% 91.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 44 0.72% 91.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 34 0.55% 92.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 18 0.29% 92.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 53 0.86% 93.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 7 0.11% 93.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 141 2.30% 95.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 11 0.18% 96.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 8 0.13% 96.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 8 0.13% 96.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 63 1.03% 97.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 7 0.11% 97.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 8 0.13% 97.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 25 0.41% 98.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 94 1.53% 99.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 1 0.02% 99.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91 1 0.02% 99.56% # Writes before turning the bus around for reads
2016-03-16 21:03:49 +01:00
system.physmem.wrPerTurnAround::96-99 1 0.02% 99.58% # Writes before turning the bus around for reads
2016-04-09 18:13:40 +02:00
system.physmem.wrPerTurnAround::100-103 1 0.02% 99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 1 0.02% 99.61% # Writes before turning the bus around for reads
2016-04-21 10:48:24 +02:00
system.physmem.wrPerTurnAround::120-123 1 0.02% 99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 7 0.11% 99.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 1 0.02% 99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147 6 0.10% 99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 1 0.02% 99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179 5 0.08% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183 1 0.02% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191 1 0.02% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::204-207 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 6142 # Writes before turning the bus around for reads
system.physmem.totQLat 2126742000 # Total ticks spent queuing
system.physmem.totMemAccLat 5313023250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 849675000 # Total ticks spent in databus transfers
system.physmem.avgQLat 12515.03 # Average queueing delay per DRAM burst
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2016-04-21 10:48:24 +02:00
system.physmem.avgMemAccLat 31265.03 # Average memory access latency per DRAM burst
2015-09-25 13:27:03 +02:00
system.physmem.avgRdBW 3.84 # Average DRAM read bandwidth in MiByte/s
2016-04-09 18:13:40 +02:00
system.physmem.avgWrBW 2.84 # Average achieved write bandwidth in MiByte/s
2015-09-25 13:27:03 +02:00
system.physmem.avgRdBWSys 3.78 # Average system read bandwidth in MiByte/s
2016-04-09 18:13:40 +02:00
system.physmem.avgWrBWSys 2.84 # Average system write bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2015-07-03 16:15:03 +02:00
system.physmem.busUtil 0.05 # Data bus utilization in percentage
2014-10-30 05:18:29 +01:00
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
2015-07-03 16:15:03 +02:00
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
2016-04-09 18:13:40 +02:00
system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
2016-04-21 10:48:24 +02:00
system.physmem.avgWrQLen 23.43 # Average write queue length when enqueuing
system.physmem.readRowHits 139707 # Number of row buffer hits during reads
system.physmem.writeRowHits 94201 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.21 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 74.82 # Row buffer hit rate for writes
system.physmem.avgGap 9447347.56 # Average gap between requests
system.physmem.pageHitRate 79.07 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 242207280 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 132156750 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 687546600 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 416962080 # Energy for write commands per rank (pJ)
2016-04-09 18:13:40 +02:00
system.physmem_0.refreshEnergy 185028367680 # Energy for refresh commands per rank (pJ)
2016-04-21 10:48:24 +02:00
system.physmem_0.actBackEnergy 83427429555 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1626531651000 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 1896466320945 # Total energy per rank (pJ)
system.physmem_0.averagePower 669.453835 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 2705741524500 # Time in different power states
2016-04-09 18:13:40 +02:00
system.physmem_0.memoryStateTime::REF 94595280000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
2016-04-21 10:48:24 +02:00
system.physmem_0.memoryStateTime::ACT 32519220500 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
2016-04-21 10:48:24 +02:00
system.physmem_1.actEnergy 225870120 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 123242625 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 637938600 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 398798640 # Energy for write commands per rank (pJ)
2016-04-09 18:13:40 +02:00
system.physmem_1.refreshEnergy 185028367680 # Energy for refresh commands per rank (pJ)
2016-04-21 10:48:24 +02:00
system.physmem_1.actBackEnergy 82153488960 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 1627649142750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 1896216849375 # Total energy per rank (pJ)
system.physmem_1.averagePower 669.365771 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 2707616089750 # Time in different power states
2016-04-09 18:13:40 +02:00
system.physmem_1.memoryStateTime::REF 94595280000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
2016-04-21 10:48:24 +02:00
system.physmem_1.memoryStateTime::ACT 30651593250 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
2016-04-09 18:13:40 +02:00
system.realview.nvmem.bytes_read::cpu.inst 112 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 112 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 112 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 112 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 7 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 40 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 40 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 40 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 40 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 40 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 40 # Total bandwidth to/from this memory (bytes/s)
2012-08-28 20:30:25 +02:00
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
2014-10-30 05:18:29 +01:00
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
2016-04-21 10:48:24 +02:00
system.cpu.branchPred.lookups 46806016 # Number of BP lookups
system.cpu.branchPred.condPredicted 23977735 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1175497 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 29454915 # Number of BTB lookups
system.cpu.branchPred.BTBHits 13525299 # Number of BTB hits
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2016-04-21 10:48:24 +02:00
system.cpu.branchPred.BTBHitPct 45.918649 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 11724113 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 34916 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 7913969 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 7767748 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 146221 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 60350 # Number of mispredicted indirect branches.
2014-11-12 15:05:25 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2014-12-23 15:31:20 +01:00
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-04-21 10:48:24 +02:00
system.cpu.checker.dtb.walker.walks 9708 # Table walker walks requested
system.cpu.checker.dtb.walker.walksShort 9708 # Table walker walks initiated with short descriptors
system.cpu.checker.dtb.walker.walkWaitTime::samples 9708 # Table walker wait (enqueue to first request) latency
system.cpu.checker.dtb.walker.walkWaitTime::0 9708 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.checker.dtb.walker.walkWaitTime::total 9708 # Table walker wait (enqueue to first request) latency
2015-09-25 13:27:03 +02:00
system.cpu.checker.dtb.walker.walksPending::samples 375751000 # Table walker pending requests distribution
system.cpu.checker.dtb.walker.walksPending::0 375751000 100.00% 100.00% # Table walker pending requests distribution
system.cpu.checker.dtb.walker.walksPending::total 375751000 # Table walker pending requests distribution
2016-04-21 10:48:24 +02:00
system.cpu.checker.dtb.walker.walkPageSizes::4K 6238 82.69% 82.69% # Table walker page sizes translated
2016-04-09 18:13:40 +02:00
system.cpu.checker.dtb.walker.walkPageSizes::1M 1306 17.31% 100.00% # Table walker page sizes translated
2016-04-21 10:48:24 +02:00
system.cpu.checker.dtb.walker.walkPageSizes::total 7544 # Table walker page sizes translated
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 9708 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2016-04-21 10:48:24 +02:00
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 9708 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 7544 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2016-04-21 10:48:24 +02:00
system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 7544 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin::total 17252 # Table walker requests started/completed, data/inst
2012-08-28 20:30:25 +02:00
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
2016-05-31 17:55:47 +02:00
system.cpu.checker.dtb.read_hits 24576304 # DTB read hits
2016-04-21 10:48:24 +02:00
system.cpu.checker.dtb.read_misses 8296 # DTB read misses
2016-05-31 17:55:47 +02:00
system.cpu.checker.dtb.write_hits 19632670 # DTB write hits
2016-04-09 18:13:40 +02:00
system.cpu.checker.dtb.write_misses 1412 # DTB write misses
2014-10-30 05:18:29 +01:00
system.cpu.checker.dtb.flush_tlb 128 # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA
system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2015-09-25 13:27:03 +02:00
system.cpu.checker.dtb.flush_entries 4283 # Number of entries that have been flushed from TLB
2012-08-28 20:30:25 +02:00
system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
2016-04-09 18:13:40 +02:00
system.cpu.checker.dtb.prefetch_faults 1622 # Number of TLB faults due to prefetch
2012-08-28 20:30:25 +02:00
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2014-10-30 05:18:29 +01:00
system.cpu.checker.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
2016-05-31 17:55:47 +02:00
system.cpu.checker.dtb.read_accesses 24584600 # DTB read accesses
system.cpu.checker.dtb.write_accesses 19634082 # DTB write accesses
2012-08-28 20:30:25 +02:00
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
2016-05-31 17:55:47 +02:00
system.cpu.checker.dtb.hits 44208974 # DTB hits
2016-04-21 10:48:24 +02:00
system.cpu.checker.dtb.misses 9708 # DTB misses
2016-05-31 17:55:47 +02:00
system.cpu.checker.dtb.accesses 44218682 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2015-09-25 13:27:03 +02:00
system.cpu.checker.itb.walker.walks 4825 # Table walker walks requested
system.cpu.checker.itb.walker.walksShort 4825 # Table walker walks initiated with short descriptors
system.cpu.checker.itb.walker.walkWaitTime::samples 4825 # Table walker wait (enqueue to first request) latency
system.cpu.checker.itb.walker.walkWaitTime::0 4825 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.checker.itb.walker.walkWaitTime::total 4825 # Table walker wait (enqueue to first request) latency
system.cpu.checker.itb.walker.walksPending::samples 375090000 # Table walker pending requests distribution
system.cpu.checker.itb.walker.walksPending::0 375090000 100.00% 100.00% # Table walker pending requests distribution
system.cpu.checker.itb.walker.walksPending::total 375090000 # Table walker pending requests distribution
system.cpu.checker.itb.walker.walkPageSizes::4K 2798 88.26% 88.26% # Table walker page sizes translated
system.cpu.checker.itb.walker.walkPageSizes::1M 372 11.74% 100.00% # Table walker page sizes translated
system.cpu.checker.itb.walker.walkPageSizes::total 3170 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2015-09-25 13:27:03 +02:00
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 4825 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 4825 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2015-09-25 13:27:03 +02:00
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 3170 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 3170 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin::total 7995 # Table walker requests started/completed, data/inst
2016-04-21 10:48:24 +02:00
system.cpu.checker.itb.inst_hits 115798779 # ITB inst hits
2015-09-25 13:27:03 +02:00
system.cpu.checker.itb.inst_misses 4825 # ITB inst misses
2012-08-28 20:30:25 +02:00
system.cpu.checker.itb.read_hits 0 # DTB read hits
system.cpu.checker.itb.read_misses 0 # DTB read misses
system.cpu.checker.itb.write_hits 0 # DTB write hits
system.cpu.checker.itb.write_misses 0 # DTB write misses
2014-10-30 05:18:29 +01:00
system.cpu.checker.itb.flush_tlb 128 # Number of times complete TLB was flushed
system.cpu.checker.itb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA
system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2015-09-25 13:27:03 +02:00
system.cpu.checker.itb.flush_entries 2976 # Number of entries that have been flushed from TLB
2012-08-28 20:30:25 +02:00
system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
2016-04-21 10:48:24 +02:00
system.cpu.checker.itb.inst_accesses 115803604 # ITB inst accesses
system.cpu.checker.itb.hits 115798779 # DTB hits
2015-09-25 13:27:03 +02:00
system.cpu.checker.itb.misses 4825 # DTB misses
2016-04-21 10:48:24 +02:00
system.cpu.checker.itb.accesses 115803604 # DTB accesses
system.cpu.checker.numCycles 139031272 # number of cpu cycles simulated
2012-08-28 20:30:25 +02:00
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
2014-12-23 15:31:20 +01:00
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-04-21 10:48:24 +02:00
system.cpu.dtb.walker.walks 72368 # Table walker walks requested
system.cpu.dtb.walker.walksShort 72368 # Table walker walks initiated with short descriptors
system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29394 # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23209 # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walksSquashedBefore 19765 # Table walks squashed before starting
system.cpu.dtb.walker.walkWaitTime::samples 52603 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::mean 464.308119 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::stdev 2802.300904 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0-8191 51295 97.51% 97.51% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::8192-16383 909 1.73% 99.24% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::16384-24575 317 0.60% 99.84% # Table walker wait (enqueue to first request) latency
2016-04-09 18:13:40 +02:00
system.cpu.dtb.walker.walkWaitTime::24576-32767 38 0.07% 99.92% # Table walker wait (enqueue to first request) latency
2016-04-21 10:48:24 +02:00
system.cpu.dtb.walker.walkWaitTime::32768-40959 17 0.03% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::40960-49151 21 0.04% 99.99% # Table walker wait (enqueue to first request) latency
2016-04-09 18:13:40 +02:00
system.cpu.dtb.walker.walkWaitTime::49152-57343 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::57344-65535 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::81920-90111 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::90112-98303 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
2016-04-21 10:48:24 +02:00
system.cpu.dtb.walker.walkWaitTime::total 52603 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples 17713 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 12609.213572 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean 10088.702316 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev 8411.296807 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-32767 17487 98.72% 98.72% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::32768-65535 220 1.24% 99.97% # Table walker service (enqueue to completion) latency
2015-09-25 13:27:03 +02:00
system.cpu.dtb.walker.walkCompletionTime::131072-163839 5 0.03% 99.99% # Table walker service (enqueue to completion) latency
2016-04-09 18:13:40 +02:00
system.cpu.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
2016-04-21 10:48:24 +02:00
system.cpu.dtb.walker.walkCompletionTime::total 17713 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples 131327462316 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::mean 0.619046 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::stdev 0.492812 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0-1 131267362816 99.95% 99.95% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::2-3 40987500 0.03% 99.99% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::4-5 8789000 0.01% 99.99% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::6-7 6827500 0.01% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::8-9 1022500 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::10-11 578500 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::12-13 1418000 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::14-15 467000 0.00% 100.00% # Table walker pending requests distribution
2016-04-09 18:13:40 +02:00
system.cpu.dtb.walker.walksPending::16-17 9500 0.00% 100.00% # Table walker pending requests distribution
2016-04-21 10:48:24 +02:00
system.cpu.dtb.walker.walksPending::total 131327462316 # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K 6375 82.60% 82.60% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::1M 1343 17.40% 100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total 7718 # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 72368 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2016-04-21 10:48:24 +02:00
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 72368 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7718 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2016-04-21 10:48:24 +02:00
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7718 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 80086 # Table walker requests started/completed, data/inst
2012-08-28 20:30:25 +02:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
2016-05-31 17:55:47 +02:00
system.cpu.dtb.read_hits 25410890 # DTB read hits
2016-04-21 10:48:24 +02:00
system.cpu.dtb.read_misses 62740 # DTB read misses
2016-05-31 17:55:47 +02:00
system.cpu.dtb.write_hits 19865163 # DTB write hits
2016-04-21 10:48:24 +02:00
system.cpu.dtb.write_misses 9628 # DTB write misses
2014-10-30 05:18:29 +01:00
system.cpu.dtb.flush_tlb 128 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2015-11-06 09:26:50 +01:00
system.cpu.dtb.flush_entries 4317 # Number of entries that have been flushed from TLB
2016-04-21 10:48:24 +02:00
system.cpu.dtb.align_faults 362 # Number of TLB faults due to alignment restrictions
2016-04-09 18:13:40 +02:00
system.cpu.dtb.prefetch_faults 2060 # Number of TLB faults due to prefetch
2012-08-28 20:30:25 +02:00
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-04-21 10:48:24 +02:00
system.cpu.dtb.perms_faults 1318 # Number of TLB faults due to permissions restrictions
2016-05-31 17:55:47 +02:00
system.cpu.dtb.read_accesses 25473630 # DTB read accesses
system.cpu.dtb.write_accesses 19874791 # DTB write accesses
2012-08-28 20:30:25 +02:00
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
2016-05-31 17:55:47 +02:00
system.cpu.dtb.hits 45276053 # DTB hits
2016-04-21 10:48:24 +02:00
system.cpu.dtb.misses 72368 # DTB misses
2016-05-31 17:55:47 +02:00
system.cpu.dtb.accesses 45348421 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-04-21 10:48:24 +02:00
system.cpu.itb.walker.walks 12817 # Table walker walks requested
system.cpu.itb.walker.walksShort 12817 # Table walker walks initiated with short descriptors
system.cpu.itb.walker.walksShortTerminationLevel::Level1 3368 # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walksShortTerminationLevel::Level2 7731 # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walksSquashedBefore 1718 # Table walks squashed before starting
system.cpu.itb.walker.walkWaitTime::samples 11099 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::mean 753.896747 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::stdev 3151.109885 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0-4095 10511 94.70% 94.70% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::4096-8191 118 1.06% 95.77% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::8192-12287 237 2.14% 97.90% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::12288-16383 123 1.11% 99.01% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::16384-20479 46 0.41% 99.42% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::20480-24575 47 0.42% 99.85% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::24576-28671 4 0.04% 99.88% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::28672-32767 7 0.06% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::32768-36863 1 0.01% 99.95% # Table walker wait (enqueue to first request) latency
2016-04-09 18:13:40 +02:00
system.cpu.itb.walker.walkWaitTime::36864-40959 2 0.02% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::40960-45055 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::53248-57343 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
2015-11-06 09:26:50 +01:00
system.cpu.itb.walker.walkWaitTime::57344-61439 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
2016-04-21 10:48:24 +02:00
system.cpu.itb.walker.walkWaitTime::total 11099 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples 5044 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 12037.073751 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 9689.647863 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev 7634.465398 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-16383 4079 80.87% 80.87% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::16384-32767 946 18.75% 99.62% # Table walker service (enqueue to completion) latency
2016-04-09 18:13:40 +02:00
system.cpu.itb.walker.walkCompletionTime::32768-49151 16 0.32% 99.94% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::49152-65535 1 0.02% 99.96% # Table walker service (enqueue to completion) latency
2016-03-16 21:03:49 +01:00
system.cpu.itb.walker.walkCompletionTime::131072-147455 2 0.04% 100.00% # Table walker service (enqueue to completion) latency
2016-04-21 10:48:24 +02:00
system.cpu.itb.walker.walkCompletionTime::total 5044 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples 23953217916 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::mean 0.646337 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::stdev 0.478297 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0 8473460000 35.38% 35.38% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::1 15477752916 64.62% 99.99% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::2 1917000 0.01% 100.00% # Table walker pending requests distribution
2016-04-09 18:13:40 +02:00
system.cpu.itb.walker.walksPending::3 88000 0.00% 100.00% # Table walker pending requests distribution
2016-04-21 10:48:24 +02:00
system.cpu.itb.walker.walksPending::total 23953217916 # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K 2992 89.96% 89.96% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::1M 334 10.04% 100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total 3326 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2016-04-21 10:48:24 +02:00
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 12817 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 12817 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2016-04-21 10:48:24 +02:00
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3326 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 3326 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 16143 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 65995629 # ITB inst hits
system.cpu.itb.inst_misses 12817 # ITB inst misses
2012-08-28 20:30:25 +02:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
2014-10-30 05:18:29 +01:00
system.cpu.itb.flush_tlb 128 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2016-04-21 10:48:24 +02:00
system.cpu.itb.flush_entries 3089 # Number of entries that have been flushed from TLB
2012-08-28 20:30:25 +02:00
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-04-21 10:48:24 +02:00
system.cpu.itb.perms_faults 2166 # Number of TLB faults due to permissions restrictions
2012-08-28 20:30:25 +02:00
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
2016-04-21 10:48:24 +02:00
system.cpu.itb.inst_accesses 66008446 # ITB inst accesses
system.cpu.itb.hits 65995629 # DTB hits
system.cpu.itb.misses 12817 # DTB misses
system.cpu.itb.accesses 66008446 # DTB accesses
system.cpu.numCycles 278423951 # number of cpu cycles simulated
2012-08-28 20:30:25 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
2016-05-31 17:55:47 +02:00
system.cpu.fetch.icacheStallCycles 104963927 # Number of cycles fetch is stalled on an Icache miss
2016-04-21 10:48:24 +02:00
system.cpu.fetch.Insts 184057531 # Number of instructions fetch has processed
system.cpu.fetch.Branches 46806016 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 33017160 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 161476606 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 6057796 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 189442 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles 8697 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 337421 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 555442 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles 188 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 65994399 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 1047621 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes 6260 # Number of outstanding ITLB misses that were squashed
2016-05-31 17:55:47 +02:00
system.cpu.fetch.rateDist::samples 270560621 # Number of instructions fetched each cycle (Total)
2016-04-21 10:48:24 +02:00
system.cpu.fetch.rateDist::mean 0.829508 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.217052 # Number of instructions fetched each cycle (Total)
2012-08-28 20:30:25 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2016-05-31 17:55:47 +02:00
system.cpu.fetch.rateDist::0 171637464 63.44% 63.44% # Number of instructions fetched each cycle (Total)
2016-04-21 10:48:24 +02:00
system.cpu.fetch.rateDist::1 29152121 10.77% 74.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 14032929 5.19% 79.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 55738107 20.60% 100.00% # Number of instructions fetched each cycle (Total)
2012-08-28 20:30:25 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
2014-09-03 13:42:59 +02:00
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
2016-05-31 17:55:47 +02:00
system.cpu.fetch.rateDist::total 270560621 # Number of instructions fetched each cycle (Total)
2016-04-21 10:48:24 +02:00
system.cpu.fetch.branchRate 0.168111 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.661069 # Number of inst fetches per cycle
2016-05-31 17:55:47 +02:00
system.cpu.decode.IdleCycles 77946488 # Number of cycles decode is idle
2016-04-21 10:48:24 +02:00
system.cpu.decode.BlockedCycles 121877263 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 64301274 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 3866559 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 2569037 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 3407655 # Number of times decode resolved a branch
2016-04-09 18:13:40 +02:00
system.cpu.decode.BranchMispred 467954 # Number of times decode detected a branch misprediction
2016-04-21 10:48:24 +02:00
system.cpu.decode.DecodedInsts 156976144 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 3511593 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 2569037 # Number of cycles rename is squashing
2016-05-31 17:55:47 +02:00
system.cpu.rename.IdleCycles 83703989 # Number of cycles rename is idle
2016-04-21 10:48:24 +02:00
system.cpu.rename.BlockCycles 11810773 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 76556801 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 62410429 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 33509592 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 146427061 # Number of instructions processed by rename
system.cpu.rename.SquashedInsts 918712 # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents 467058 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 65507 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 18530 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 30752508 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 150221263 # Number of destination operands rename has renamed
2016-06-02 15:14:36 +02:00
system.cpu.rename.RenameLookups 676943612 # Number of register rename lookups that rename has made
2016-04-21 10:48:24 +02:00
system.cpu.rename.int_rename_lookups 163957736 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 10899 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 141737618 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 8483639 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 2839333 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 2643784 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 13883095 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 26339486 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 21214202 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1704469 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 2149070 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 143218821 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 2117732 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 143038678 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 260968 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 8155598 # Number of squashed instructions iterated over during squash; mainly for profiling
2016-06-02 15:14:36 +02:00
system.cpu.iq.iqSquashedOperandsExamined 14294324 # Number of squashed operands that are examined and possibly removed from graph
2016-04-21 10:48:24 +02:00
system.cpu.iq.iqSquashedNonSpecRemoved 121861 # Number of squashed non-spec instructions that were removed
2016-05-31 17:55:47 +02:00
system.cpu.iq.issued_per_cycle::samples 270560621 # Number of insts issued each cycle
2016-04-21 10:48:24 +02:00
system.cpu.iq.issued_per_cycle::mean 0.528675 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 0.865256 # Number of insts issued each cycle
2012-08-28 20:30:25 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2016-05-31 17:55:47 +02:00
system.cpu.iq.issued_per_cycle::0 182379693 67.41% 67.41% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 45219625 16.71% 84.12% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 31881925 11.78% 95.91% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 10262342 3.79% 99.70% # Number of insts issued each cycle
2016-04-21 10:48:24 +02:00
system.cpu.iq.issued_per_cycle::4 817003 0.30% 100.00% # Number of insts issued each cycle
2015-11-06 09:26:50 +01:00
system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle
2014-09-03 13:42:59 +02:00
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
2012-08-28 20:30:25 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
2014-09-03 13:42:59 +02:00
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
2016-05-31 17:55:47 +02:00
system.cpu.iq.issued_per_cycle::total 270560621 # Number of insts issued each cycle
2012-08-28 20:30:25 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2016-04-21 10:48:24 +02:00
system.cpu.iq.fu_full::IntAlu 7341670 32.77% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 32 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.77% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 5623214 25.10% 57.86% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 9441955 42.14% 100.00% # attempts to use FU when none available
2012-08-28 20:30:25 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2014-10-30 05:18:29 +01:00
system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued
2016-04-21 10:48:24 +02:00
system.cpu.iq.FU_type_0::IntAlu 95844496 67.01% 67.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 114325 0.08% 67.09% # Type of FU issued
2016-04-09 18:13:40 +02:00
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.09% # Type of FU issued
2016-04-21 10:48:24 +02:00
system.cpu.iq.FU_type_0::SimdFloatMisc 8580 0.01% 67.09% # Type of FU issued
2016-04-09 18:13:40 +02:00
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.09% # Type of FU issued
2016-04-21 10:48:24 +02:00
system.cpu.iq.FU_type_0::MemRead 26129578 18.27% 85.36% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 20939362 14.64% 100.00% # Type of FU issued
2012-08-28 20:30:25 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2016-04-21 10:48:24 +02:00
system.cpu.iq.FU_type_0::total 143038678 # Type of FU issued
system.cpu.iq.rate 0.513744 # Inst issue rate
system.cpu.iq.fu_busy_cnt 22406871 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.156649 # FU busy rate (busy events/executed inst)
2016-05-31 17:55:47 +02:00
system.cpu.iq.int_inst_queue_reads 579270175 # Number of integer instruction queue reads
2016-04-21 10:48:24 +02:00
system.cpu.iq.int_inst_queue_writes 153497654 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 139987851 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 35641 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 13126 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 11370 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 165419813 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 23399 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 323906 # Number of loads that had data forwarded from stores
2012-08-28 20:30:25 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2016-04-21 10:48:24 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 1435915 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 710 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 18680 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 623667 # Number of stores squashed
2012-08-28 20:30:25 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2016-04-21 10:48:24 +02:00
system.cpu.iew.lsq.thread0.rescheduledLoads 88637 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 6231 # Number of times an access to memory failed due to the cache being blocked
2012-08-28 20:30:25 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2016-04-21 10:48:24 +02:00
system.cpu.iew.iewSquashCycles 2569037 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 1239960 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 546279 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 145517187 # Number of instructions dispatched to IQ
2014-09-03 13:42:59 +02:00
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
2016-04-21 10:48:24 +02:00
system.cpu.iew.iewDispLoadInsts 26339486 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 21214202 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 1094236 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 17880 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 509843 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 18680 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 277456 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 471588 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 749044 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 142138491 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 25734027 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 827925 # Number of squashed instructions skipped in execute
2012-08-28 20:30:25 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
2016-04-21 10:48:24 +02:00
system.cpu.iew.exec_nop 180634 # number of nop insts executed
system.cpu.iew.exec_refs 46561433 # number of memory reference insts executed
system.cpu.iew.exec_branches 26490215 # Number of branches executed
system.cpu.iew.exec_stores 20827406 # Number of stores executed
system.cpu.iew.exec_rate 0.510511 # Inst execution rate
system.cpu.iew.wb_sent 141769563 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 139999221 # cumulative count of insts written-back
2016-05-31 17:55:47 +02:00
system.cpu.iew.wb_producers 63237137 # num instructions producing a value
system.cpu.iew.wb_consumers 95708450 # num instructions consuming a value
2016-04-21 10:48:24 +02:00
system.cpu.iew.wb_rate 0.502828 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.660727 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 7372199 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1995871 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 715636 # The number of times a branch was mispredicted
2016-05-31 17:55:47 +02:00
system.cpu.commit.committed_per_cycle::samples 267668722 # Number of insts commited each cycle
2016-04-21 10:48:24 +02:00
system.cpu.commit.committed_per_cycle::mean 0.513081 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.118378 # Number of insts commited each cycle
2012-08-28 20:30:25 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2016-05-31 17:55:47 +02:00
system.cpu.commit.committed_per_cycle::0 194241019 72.57% 72.57% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 43280697 16.17% 88.74% # Number of insts commited each cycle
2016-04-21 10:48:24 +02:00
system.cpu.commit.committed_per_cycle::2 15455980 5.77% 94.51% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 4372366 1.63% 96.14% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 6407128 2.39% 98.54% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1628567 0.61% 99.15% # Number of insts commited each cycle
2016-05-31 17:55:47 +02:00
system.cpu.commit.committed_per_cycle::6 798346 0.30% 99.45% # Number of insts commited each cycle
2016-04-21 10:48:24 +02:00
system.cpu.commit.committed_per_cycle::7 412274 0.15% 99.60% # Number of insts commited each cycle
2016-05-31 17:55:47 +02:00
system.cpu.commit.committed_per_cycle::8 1072345 0.40% 100.00% # Number of insts commited each cycle
2012-08-28 20:30:25 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2016-05-31 17:55:47 +02:00
system.cpu.commit.committed_per_cycle::total 267668722 # Number of insts commited each cycle
2016-04-21 10:48:24 +02:00
system.cpu.commit.committedInsts 113255406 # Number of instructions committed
system.cpu.commit.committedOps 137335856 # Number of ops (including micro ops) committed
2012-08-28 20:30:25 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
2016-04-21 10:48:24 +02:00
system.cpu.commit.refs 45494106 # Number of memory references committed
system.cpu.commit.loads 24903571 # Number of loads committed
2016-04-09 18:13:40 +02:00
system.cpu.commit.membars 814876 # Number of memory barriers committed
2016-04-21 10:48:24 +02:00
system.cpu.commit.branches 26023568 # Number of branches committed
2015-09-25 13:27:03 +02:00
system.cpu.commit.fp_insts 11364 # Number of committed floating point instructions.
2016-04-21 10:48:24 +02:00
system.cpu.commit.int_insts 120163713 # Number of committed integer instructions.
system.cpu.commit.function_calls 4884102 # Number of function calls committed.
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2016-04-21 10:48:24 +02:00
system.cpu.commit.op_class_0::IntAlu 91720354 66.79% 66.79% # Class of committed instruction
2016-04-09 18:13:40 +02:00
system.cpu.commit.op_class_0::IntMult 112817 0.08% 66.87% # Class of committed instruction
2014-10-30 05:18:29 +01:00
system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction
2016-04-09 18:13:40 +02:00
system.cpu.commit.op_class_0::SimdFloatMisc 8579 0.01% 66.87% # Class of committed instruction
2015-09-25 13:27:03 +02:00
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.87% # Class of committed instruction
2016-04-21 10:48:24 +02:00
system.cpu.commit.op_class_0::MemRead 24903571 18.13% 85.01% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 20590535 14.99% 100.00% # Class of committed instruction
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2016-04-21 10:48:24 +02:00
system.cpu.commit.op_class_0::total 137335856 # Class of committed instruction
2016-05-31 17:55:47 +02:00
system.cpu.commit.bw_lim_events 1072345 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 389119868 # The number of ROB reads
2016-04-21 10:48:24 +02:00
system.cpu.rob.rob_writes 292294903 # The number of ROB writes
system.cpu.timesIdled 890799 # Number of times that the entire CPU went into an idle state and unscheduled itself
2016-05-31 17:55:47 +02:00
system.cpu.idleCycles 7863330 # Total number of cycles that the CPU has spent unscheduled due to idling
2016-04-21 10:48:24 +02:00
system.cpu.quiesceCycles 5387302003 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 113100501 # Number of Instructions Simulated
system.cpu.committedOps 137180951 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 2.461739 # CPI: Cycles Per Instruction
system.cpu.cpi_total 2.461739 # CPI: Total CPI of All Threads
system.cpu.ipc 0.406217 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.406217 # IPC: Total IPC of All Threads
2016-05-31 17:55:47 +02:00
system.cpu.int_regfile_reads 155524954 # number of integer regfile reads
2016-04-21 10:48:24 +02:00
system.cpu.int_regfile_writes 88488763 # number of integer regfile writes
system.cpu.fp_regfile_reads 9529 # number of floating regfile reads
2014-10-30 05:18:29 +01:00
system.cpu.fp_regfile_writes 2716 # number of floating regfile writes
2016-05-31 17:55:47 +02:00
system.cpu.cc_regfile_reads 502156067 # number of cc regfile reads
2016-04-21 10:48:24 +02:00
system.cpu.cc_regfile_writes 53129749 # number of cc regfile writes
2016-06-02 15:14:36 +02:00
system.cpu.misc_regfile_reads 347855567 # number of misc regfile reads
2016-04-21 10:48:24 +02:00
system.cpu.misc_regfile_writes 1521708 # number of misc regfile writes
system.cpu.dcache.tags.replacements 838747 # number of replacements
2016-04-09 18:13:40 +02:00
system.cpu.dcache.tags.tagsinuse 511.925928 # Cycle average of tags in use
2016-05-31 17:55:47 +02:00
system.cpu.dcache.tags.total_refs 40056711 # Total number of references to valid blocks.
2016-04-21 10:48:24 +02:00
system.cpu.dcache.tags.sampled_refs 839259 # Sample count of references to valid blocks.
2016-05-31 17:55:47 +02:00
system.cpu.dcache.tags.avg_refs 47.728664 # Average number of references to valid blocks.
2015-09-25 13:27:03 +02:00
system.cpu.dcache.tags.warmup_cycle 441954500 # Cycle when the warmup percentage was hit.
2016-04-09 18:13:40 +02:00
system.cpu.dcache.tags.occ_blocks::cpu.data 511.925928 # Average occupied blocks per requestor
2015-09-25 13:27:03 +02:00
system.cpu.dcache.tags.occ_percent::cpu.data 0.999855 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999855 # Average percentage of cache occupancy
2014-11-12 15:05:25 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-04-09 18:13:40 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 356 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id
2014-11-12 15:05:25 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-05-31 17:55:47 +02:00
system.cpu.dcache.tags.tag_accesses 179125109 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 179125109 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 23264148 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 23264148 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 15542286 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 15542286 # number of WriteReq hits
2016-04-21 10:48:24 +02:00
system.cpu.dcache.SoftPFReq_hits::cpu.data 345698 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 345698 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 441334 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 441334 # number of LoadLockedReq hits
2016-04-09 18:13:40 +02:00
system.cpu.dcache.StoreCondReq_hits::cpu.data 460350 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 460350 # number of StoreCondReq hits
2016-05-31 17:55:47 +02:00
system.cpu.dcache.demand_hits::cpu.data 38806434 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 38806434 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 39152132 # number of overall hits
system.cpu.dcache.overall_hits::total 39152132 # number of overall hits
2016-04-21 10:48:24 +02:00
system.cpu.dcache.ReadReq_misses::cpu.data 705134 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 705134 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 3607427 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 3607427 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 177712 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 177712 # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 27363 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 27363 # number of LoadLockedReq misses
2016-04-09 18:13:40 +02:00
system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses
2016-04-21 10:48:24 +02:00
system.cpu.dcache.demand_misses::cpu.data 4312561 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 4312561 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 4490273 # number of overall misses
system.cpu.dcache.overall_misses::total 4490273 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11711380000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 11711380000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 232487777697 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 232487777697 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 376699000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 376699000 # number of LoadLockedReq miss cycles
2016-04-09 18:13:40 +02:00
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 276000 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 276000 # number of StoreCondReq miss cycles
2016-04-21 10:48:24 +02:00
system.cpu.dcache.demand_miss_latency::cpu.data 244199157697 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 244199157697 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 244199157697 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 244199157697 # number of overall miss cycles
2016-05-31 17:55:47 +02:00
system.cpu.dcache.ReadReq_accesses::cpu.data 23969282 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 23969282 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 19149713 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 19149713 # number of WriteReq accesses(hits+misses)
2016-04-21 10:48:24 +02:00
system.cpu.dcache.SoftPFReq_accesses::cpu.data 523410 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 523410 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468697 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 468697 # number of LoadLockedReq accesses(hits+misses)
2016-04-09 18:13:40 +02:00
system.cpu.dcache.StoreCondReq_accesses::cpu.data 460355 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 460355 # number of StoreCondReq accesses(hits+misses)
2016-05-31 17:55:47 +02:00
system.cpu.dcache.demand_accesses::cpu.data 43118995 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 43118995 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 43642405 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 43642405 # number of overall (read+write) accesses
2016-04-21 10:48:24 +02:00
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029418 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.029418 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188380 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.188380 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.339527 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.339527 # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.058381 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.058381 # miss rate for LoadLockedReq accesses
2016-04-09 18:13:40 +02:00
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses
2016-04-21 10:48:24 +02:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.100015 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.100015 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.102888 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.102888 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16608.729688 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16608.729688 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64446.980548 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 64446.980548 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13766.728794 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13766.728794 # average LoadLockedReq miss latency
2016-04-09 18:13:40 +02:00
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 55200 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 55200 # average StoreCondReq miss latency
2016-04-21 10:48:24 +02:00
system.cpu.dcache.demand_avg_miss_latency::cpu.data 56625.090682 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 56625.090682 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54384.033598 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 54384.033598 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 871366 # number of cycles access was blocked
2014-11-12 15:05:25 +01:00
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-04-21 10:48:24 +02:00
system.cpu.dcache.blocked::no_mshrs 6856 # number of cycles access was blocked
2014-11-12 15:05:25 +01:00
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
2016-04-21 10:48:24 +02:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 127.095391 # average number of cycles each access was blocked
2014-11-12 15:05:25 +01:00
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-04-21 10:48:24 +02:00
system.cpu.dcache.writebacks::writebacks 696773 # number of writebacks
system.cpu.dcache.writebacks::total 696773 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 291027 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 291027 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3307518 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 3307518 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18885 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 18885 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 3598545 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 3598545 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 3598545 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 3598545 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414107 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 414107 # number of ReadReq MSHR misses
2016-04-09 18:13:40 +02:00
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299909 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 299909 # number of WriteReq MSHR misses
2016-04-21 10:48:24 +02:00
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119568 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 119568 # number of SoftPFReq MSHR misses
2016-04-09 18:13:40 +02:00
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8478 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 8478 # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses
2016-04-21 10:48:24 +02:00
system.cpu.dcache.demand_mshr_misses::cpu.data 714016 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 714016 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 833584 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 833584 # number of overall MSHR misses
2015-09-25 13:27:03 +02:00
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31129 # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total 31129 # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27585 # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total 27585 # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total 58714 # number of overall MSHR uncacheable misses
2016-04-21 10:48:24 +02:00
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6386388500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6386388500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19974009472 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 19974009472 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1699913000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1699913000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 127031000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 127031000 # number of LoadLockedReq MSHR miss cycles
2016-04-09 18:13:40 +02:00
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 271000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 271000 # number of StoreCondReq MSHR miss cycles
2016-04-21 10:48:24 +02:00
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26360397972 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 26360397972 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28060310972 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 28060310972 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6276272000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6276272000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6276272000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 6276272000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017277 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017277 # mshr miss rate for ReadReq accesses
2016-04-09 18:13:40 +02:00
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015661 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015661 # mshr miss rate for WriteReq accesses
2016-04-21 10:48:24 +02:00
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228440 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228440 # mshr miss rate for SoftPFReq accesses
2016-04-09 18:13:40 +02:00
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018088 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018088 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses
2016-04-21 10:48:24 +02:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016559 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.016559 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019100 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.019100 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15422.073281 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15422.073281 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66600.233644 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66600.233644 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14217.123311 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14217.123311 # average SoftPFReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14983.604624 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14983.604624 # average LoadLockedReq mshr miss latency
2016-04-09 18:13:40 +02:00
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 54200 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 54200 # average StoreCondReq mshr miss latency
2016-04-21 10:48:24 +02:00
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36918.497585 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 36918.497585 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33662.247562 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 33662.247562 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201621.381991 # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201621.381991 # average ReadReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106895.663726 # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106895.663726 # average overall mshr uncacheable latency
system.cpu.icache.tags.replacements 1886245 # number of replacements
system.cpu.icache.tags.tagsinuse 511.154077 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 64013417 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 1886757 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 33.927749 # Average number of references to valid blocks.
2016-04-09 18:13:40 +02:00
system.cpu.icache.tags.warmup_cycle 16319051500 # Cycle when the warmup percentage was hit.
2016-04-21 10:48:24 +02:00
system.cpu.icache.tags.occ_blocks::cpu.inst 511.154077 # Average occupied blocks per requestor
2015-11-06 09:26:50 +01:00
system.cpu.icache.tags.occ_percent::cpu.inst 0.998348 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.998348 # Average percentage of cache occupancy
2014-11-12 15:05:25 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-04-21 10:48:24 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id
2016-04-09 18:13:40 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::1 173 # Occupied blocks per task id
2016-04-21 10:48:24 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::2 209 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
2014-11-12 15:05:25 +01:00
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-04-21 10:48:24 +02:00
system.cpu.icache.tags.tag_accesses 67878198 # Number of tag accesses
system.cpu.icache.tags.data_accesses 67878198 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 64013417 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 64013417 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 64013417 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 64013417 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 64013417 # number of overall hits
system.cpu.icache.overall_hits::total 64013417 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1977977 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1977977 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1977977 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1977977 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1977977 # number of overall misses
system.cpu.icache.overall_misses::total 1977977 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 28160163493 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 28160163493 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 28160163493 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 28160163493 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 28160163493 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 28160163493 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 65991394 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 65991394 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 65991394 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 65991394 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 65991394 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 65991394 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029973 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.029973 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.029973 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.029973 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.029973 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.029973 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14236.850829 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14236.850829 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14236.850829 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14236.850829 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14236.850829 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14236.850829 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 6440 # number of cycles access was blocked
2014-11-12 15:05:25 +01:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-04-21 10:48:24 +02:00
system.cpu.icache.blocked::no_mshrs 190 # number of cycles access was blocked
2014-11-12 15:05:25 +01:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
2016-04-21 10:48:24 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 33.894737 # average number of cycles each access was blocked
2014-11-12 15:05:25 +01:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-04-21 10:48:24 +02:00
system.cpu.icache.writebacks::writebacks 1886245 # number of writebacks
system.cpu.icache.writebacks::total 1886245 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91172 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 91172 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 91172 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 91172 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 91172 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 91172 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1886805 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 1886805 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 1886805 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 1886805 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1886805 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1886805 # number of overall MSHR misses
2016-04-09 18:13:40 +02:00
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3003 # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total 3003 # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3003 # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total 3003 # number of overall MSHR uncacheable misses
2016-04-21 10:48:24 +02:00
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25187429497 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 25187429497 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25187429497 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 25187429497 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25187429497 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 25187429497 # number of overall MSHR miss cycles
2016-04-09 18:13:40 +02:00
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 377605500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 377605500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 377605500 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total 377605500 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028592 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028592 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028592 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.028592 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028592 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.028592 # mshr miss rate for overall accesses
2016-04-21 10:48:24 +02:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13349.248861 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13349.248861 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13349.248861 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 13349.248861 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13349.248861 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13349.248861 # average overall mshr miss latency
2016-04-09 18:13:40 +02:00
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 125742.757243 # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 125742.757243 # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 125742.757243 # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 125742.757243 # average overall mshr uncacheable latency
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.tags.replacements 96776 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65028.780058 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 5006507 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 162101 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 30.885109 # Average number of references to valid blocks.
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.tags.occ_blocks::writebacks 49620.305059 # Average occupied blocks per requestor
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 10.737497 # Average occupied blocks per requestor
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 2.672900 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 10369.952431 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 5025.112172 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.757146 # Average percentage of cache occupancy
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000164 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000041 # Average percentage of cache occupancy
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.158233 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.076677 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.992260 # Average percentage of cache occupancy
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65312 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2860 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6691 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55601 # Occupied blocks per task id
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000198 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996582 # Percentage of cache occupancy per task id
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.tags.tag_accesses 44296182 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 44296182 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 58073 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12060 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 70133 # number of ReadReq hits
system.cpu.l2cache.WritebackDirty_hits::writebacks 696773 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 696773 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 1848340 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 1848340 # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 62 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 62 # number of UpgradeReq hits
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.ReadExReq_hits::cpu.data 161752 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 161752 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1866806 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 1866806 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 528684 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 528684 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 58073 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 12060 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 1866806 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 690436 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2627375 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 58073 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 12060 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 1866806 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 690436 # number of overall hits
system.cpu.l2cache.overall_hits::total 2627375 # number of overall hits
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 19 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 25 # number of ReadReq misses
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2719 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 2719 # number of UpgradeReq misses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 135508 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 135508 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 19911 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 19911 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 13337 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 13337 # number of ReadSharedReq misses
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.demand_misses::cpu.dtb.walker 19 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.demand_misses::cpu.inst 19911 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 148845 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 168781 # number of demand (read+write) misses
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.overall_misses::cpu.dtb.walker 19 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.overall_misses::cpu.inst 19911 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 148845 # number of overall misses
system.cpu.l2cache.overall_misses::total 168781 # number of overall misses
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2632000 # number of ReadReq miss cycles
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 795500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 3427500 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 2731500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 2731500 # number of UpgradeReq miss cycles
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 162000 # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 162000 # number of SCUpgradeReq miss cycles
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 17610608500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 17610608500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2638749000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 2638749000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1798280000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 1798280000 # number of ReadSharedReq miss cycles
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2632000 # number of demand (read+write) miss cycles
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 795500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 2638749000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 19408888500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 22051065000 # number of demand (read+write) miss cycles
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2632000 # number of overall miss cycles
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 795500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 2638749000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 19408888500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 22051065000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 58092 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12066 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 70158 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::writebacks 696773 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 696773 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 1848340 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 1848340 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2781 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 2781 # number of UpgradeReq accesses(hits+misses)
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 5 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses)
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 297260 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 297260 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1886717 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 1886717 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 542021 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 542021 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 58092 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 12066 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 1886717 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 839281 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2796156 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 58092 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 12066 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 1886717 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 839281 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2796156 # number of overall (read+write) accesses
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000327 # miss rate for ReadReq accesses
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000497 # miss rate for ReadReq accesses
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.ReadReq_miss_rate::total 0.000356 # miss rate for ReadReq accesses
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.977706 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.977706 # miss rate for UpgradeReq accesses
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.600000 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.600000 # miss rate for SCUpgradeReq accesses
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.455857 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.455857 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010553 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010553 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.024606 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024606 # miss rate for ReadSharedReq accesses
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000327 # miss rate for demand accesses
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000497 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010553 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.177348 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.060362 # miss rate for demand accesses
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000327 # miss rate for overall accesses
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000497 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010553 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.177348 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.060362 # miss rate for overall accesses
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 138526.315789 # average ReadReq miss latency
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 132583.333333 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 137100 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 1004.597278 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 1004.597278 # average UpgradeReq miss latency
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 54000 # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 54000 # average SCUpgradeReq miss latency
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 129959.917496 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 129959.917496 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132527.196022 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132527.196022 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 134833.920672 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 134833.920672 # average ReadSharedReq miss latency
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 138526.315789 # average overall miss latency
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 132583.333333 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132527.196022 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 130396.644160 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 130648.977077 # average overall miss latency
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 138526.315789 # average overall miss latency
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 132583.333333 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132527.196022 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 130396.644160 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 130648.977077 # average overall miss latency
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.writebacks::writebacks 89222 # number of writebacks
system.cpu.l2cache.writebacks::total 89222 # number of writebacks
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 26 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 26 # number of ReadCleanReq MSHR hits
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 111 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 111 # number of ReadSharedReq MSHR hits
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.demand_mshr_hits::cpu.inst 26 # number of demand (read+write) MSHR hits
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.demand_mshr_hits::cpu.data 111 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 137 # number of demand (read+write) MSHR hits
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.overall_mshr_hits::cpu.inst 26 # number of overall MSHR hits
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.overall_mshr_hits::cpu.data 111 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 137 # number of overall MSHR hits
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 19 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 25 # number of ReadReq MSHR misses
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2719 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 2719 # number of UpgradeReq MSHR misses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 135508 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 135508 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 19885 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 19885 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 13226 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 13226 # number of ReadSharedReq MSHR misses
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 19 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.demand_mshr_misses::cpu.inst 19885 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 148734 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 168644 # number of demand (read+write) MSHR misses
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 19 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.overall_mshr_misses::cpu.inst 19885 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 148734 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 168644 # number of overall MSHR misses
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3003 # number of ReadReq MSHR uncacheable
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31129 # number of ReadReq MSHR uncacheable
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34132 # number of ReadReq MSHR uncacheable
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27585 # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27585 # number of WriteReq MSHR uncacheable
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3003 # number of overall MSHR uncacheable misses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61717 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2442000 # number of ReadReq MSHR miss cycles
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 735500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3177500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 184950500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 184950500 # number of UpgradeReq MSHR miss cycles
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 211500 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 211500 # number of SCUpgradeReq MSHR miss cycles
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16255528500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16255528500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2436802003 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2436802003 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1652257000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1652257000 # number of ReadSharedReq MSHR miss cycles
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2442000 # number of demand (read+write) MSHR miss cycles
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 735500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2436802003 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17907785500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 20347765003 # number of demand (read+write) MSHR miss cycles
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2442000 # number of overall MSHR miss cycles
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 735500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2436802003 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17907785500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 20347765003 # number of overall MSHR miss cycles
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 340067500 # number of ReadReq MSHR uncacheable cycles
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5887147000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6227214500 # number of ReadReq MSHR uncacheable cycles
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 340067500 # number of overall MSHR uncacheable cycles
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5887147000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6227214500 # number of overall MSHR uncacheable cycles
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000327 # mshr miss rate for ReadReq accesses
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000497 # mshr miss rate for ReadReq accesses
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000356 # mshr miss rate for ReadReq accesses
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.977706 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.977706 # mshr miss rate for UpgradeReq accesses
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.600000 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.600000 # mshr miss rate for SCUpgradeReq accesses
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.455857 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.455857 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010539 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010539 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.024401 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024401 # mshr miss rate for ReadSharedReq accesses
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000327 # mshr miss rate for demand accesses
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000497 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010539 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.177216 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.060313 # mshr miss rate for demand accesses
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000327 # mshr miss rate for overall accesses
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000497 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010539 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.177216 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.060313 # mshr miss rate for overall accesses
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 128526.315789 # average ReadReq mshr miss latency
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122583.333333 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127100 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68021.515263 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68021.515263 # average UpgradeReq mshr miss latency
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70500 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 119959.917496 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 119959.917496 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122544.732361 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122544.732361 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124924.920611 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124924.920611 # average ReadSharedReq mshr miss latency
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 128526.315789 # average overall mshr miss latency
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122583.333333 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122544.732361 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120401.424691 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120655.137467 # average overall mshr miss latency
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 128526.315789 # average overall mshr miss latency
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122583.333333 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122544.732361 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120401.424691 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120655.137467 # average overall mshr miss latency
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113242.590743 # average ReadReq mshr uncacheable latency
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189120.980436 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 182445.051565 # average ReadReq mshr uncacheable latency
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113242.590743 # average overall mshr uncacheable latency
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100268.198385 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 100899.500948 # average overall mshr uncacheable latency
system.cpu.toL2Bus.snoop_filter.tot_requests 5483921 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2757867 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 44951 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-04-09 18:13:40 +02:00
system.cpu.toL2Bus.snoop_filter.tot_snoops 378 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 378 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-04-09 18:13:40 +02:00
system.cpu.toL2Bus.trans_dist::ReadReq 128774 # Transaction distribution
2016-04-21 10:48:24 +02:00
system.cpu.toL2Bus.trans_dist::ReadResp 2557731 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.trans_dist::WriteReq 27585 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 27585 # Transaction distribution
2016-04-21 10:48:24 +02:00
system.cpu.toL2Bus.trans_dist::WritebackDirty 822205 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 1886245 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 149751 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 2781 # Transaction distribution
2016-04-09 18:13:40 +02:00
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution
2016-04-21 10:48:24 +02:00
system.cpu.toL2Bus.trans_dist::UpgradeResp 2786 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 297260 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 297260 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 1886805 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 542244 # Transaction distribution
2016-04-09 18:13:40 +02:00
system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
2016-04-21 10:48:24 +02:00
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5665772 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2640441 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30896 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 133904 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 8471013 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 241517552 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98498985 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 48264 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 232368 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 340297169 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 194360 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 3054889 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.024700 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.155211 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-04-21 10:48:24 +02:00
system.cpu.toL2Bus.snoop_fanout::0 2979432 97.53% 97.53% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 75457 2.47% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
2016-04-21 10:48:24 +02:00
system.cpu.toL2Bus.snoop_fanout::total 3054889 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 5401923998 # Layer occupancy (ticks)
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
2016-04-09 18:13:40 +02:00
system.cpu.toL2Bus.snoopLayer0.occupancy 258877 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2016-04-21 10:48:24 +02:00
system.cpu.toL2Bus.respLayer0.occupancy 2834168078 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
2016-04-21 10:48:24 +02:00
system.cpu.toL2Bus.respLayer1.occupancy 1305452066 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2016-04-21 10:48:24 +02:00
system.cpu.toL2Bus.respLayer2.occupancy 18839481 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-04-21 10:48:24 +02:00
system.cpu.toL2Bus.respLayer3.occupancy 75872379 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2016-04-09 18:13:40 +02:00
system.iobus.trans_dist::ReadReq 30172 # Transaction distribution
system.iobus.trans_dist::ReadResp 30172 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.iobus.trans_dist::WriteResp 59014 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes)
2016-04-09 18:13:40 +02:00
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72894 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72894 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 178372 # Packet count per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes)
2016-04-09 18:13:40 +02:00
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321016 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321016 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2480141 # Cumulative packet size per connected master and slave (bytes)
2016-04-21 10:48:24 +02:00
system.iobus.reqLayer0.occupancy 43093500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2016-04-09 18:13:40 +02:00
system.iobus.reqLayer1.occupancy 100500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2016-04-09 18:13:40 +02:00
system.iobus.reqLayer2.occupancy 326500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2016-04-09 18:13:40 +02:00
system.iobus.reqLayer3.occupancy 27500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2016-04-09 18:13:40 +02:00
system.iobus.reqLayer4.occupancy 14000 # Layer occupancy (ticks)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
2016-04-21 10:48:24 +02:00
system.iobus.reqLayer7.occupancy 93500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
2016-04-21 10:48:24 +02:00
system.iobus.reqLayer8.occupancy 652000 # Layer occupancy (ticks)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
2016-04-09 18:13:40 +02:00
system.iobus.reqLayer10.occupancy 20500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer13.occupancy 9000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2016-04-09 18:13:40 +02:00
system.iobus.reqLayer16.occupancy 47500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2016-04-09 18:13:40 +02:00
system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2016-04-09 18:13:40 +02:00
system.iobus.reqLayer18.occupancy 9500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer19.occupancy 3000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
2016-03-16 21:03:49 +01:00
system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
2016-04-09 18:13:40 +02:00
system.iobus.reqLayer21.occupancy 9000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
2016-04-21 10:48:24 +02:00
system.iobus.reqLayer23.occupancy 6160000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2016-04-21 10:48:24 +02:00
system.iobus.reqLayer24.occupancy 33076500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2016-04-21 10:48:24 +02:00
system.iobus.reqLayer25.occupancy 187162988 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2015-03-02 11:04:20 +01:00
system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2016-04-09 18:13:40 +02:00
system.iobus.respLayer3.occupancy 36718000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2016-04-09 18:13:40 +02:00
system.iocache.tags.replacements 36413 # number of replacements
system.iocache.tags.tagsinuse 1.005739 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 36429 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 256498269000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide 1.005739 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide 0.062859 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.062859 # Average percentage of cache occupancy
2014-10-30 05:18:29 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2016-04-09 18:13:40 +02:00
system.iocache.tags.tag_accesses 328023 # Number of tag accesses
system.iocache.tags.data_accesses 328023 # Number of data accesses
system.iocache.ReadReq_misses::realview.ide 223 # number of ReadReq misses
system.iocache.ReadReq_misses::total 223 # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
2016-04-21 10:48:24 +02:00
system.iocache.demand_misses::realview.ide 36447 # number of demand (read+write) misses
system.iocache.demand_misses::total 36447 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 36447 # number of overall misses
system.iocache.overall_misses::total 36447 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide 28153877 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 28153877 # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide 4551268111 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 4551268111 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide 4579421988 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 4579421988 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide 4579421988 # number of overall miss cycles
system.iocache.overall_miss_latency::total 4579421988 # number of overall miss cycles
2016-04-09 18:13:40 +02:00
system.iocache.ReadReq_accesses::realview.ide 223 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 223 # number of ReadReq accesses(hits+misses)
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
2016-04-21 10:48:24 +02:00
system.iocache.demand_accesses::realview.ide 36447 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 36447 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide 36447 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 36447 # number of overall (read+write) accesses
2014-10-30 05:18:29 +01:00
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2016-04-09 18:13:40 +02:00
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2014-10-30 05:18:29 +01:00
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2016-04-21 10:48:24 +02:00
system.iocache.ReadReq_avg_miss_latency::realview.ide 126250.569507 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 126250.569507 # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125642.339637 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 125642.339637 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 125646.061075 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 125646.061075 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 125646.061075 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 125646.061075 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2012-08-28 20:30:25 +02:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-04-21 10:48:24 +02:00
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
2012-08-28 20:30:25 +02:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2016-04-21 10:48:24 +02:00
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2012-08-28 20:30:25 +02:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-04-09 18:13:40 +02:00
system.iocache.writebacks::writebacks 36190 # number of writebacks
system.iocache.writebacks::total 36190 # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide 223 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 223 # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
2016-04-21 10:48:24 +02:00
system.iocache.demand_mshr_misses::realview.ide 36447 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 36447 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 36447 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 36447 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide 17003877 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 17003877 # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2738656099 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 2738656099 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 2755659976 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 2755659976 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 2755659976 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 2755659976 # number of overall MSHR miss cycles
2014-10-30 05:18:29 +01:00
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2016-04-09 18:13:40 +02:00
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2014-10-30 05:18:29 +01:00
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2016-04-21 10:48:24 +02:00
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76250.569507 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 76250.569507 # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75603.359623 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75603.359623 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 75607.319560 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 75607.319560 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 75607.319560 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 75607.319560 # average overall mshr miss latency
2016-04-09 18:13:40 +02:00
system.membus.trans_dist::ReadReq 34132 # Transaction distribution
2016-04-21 10:48:24 +02:00
system.membus.trans_dist::ReadResp 67490 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.membus.trans_dist::WriteReq 27585 # Transaction distribution
system.membus.trans_dist::WriteResp 27585 # Transaction distribution
2016-04-21 10:48:24 +02:00
system.membus.trans_dist::WritebackDirty 125412 # Transaction distribution
system.membus.trans_dist::CleanEvict 7777 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4588 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
2016-02-10 10:08:27 +01:00
system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
2016-04-21 10:48:24 +02:00
system.membus.trans_dist::ReadExReq 133639 # Transaction distribution
system.membus.trans_dist::ReadExResp 133639 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 33359 # Transaction distribution
2016-04-09 18:13:40 +02:00
system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
2016-04-09 18:13:40 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2076 # Packet count per connected master and slave (bytes)
2016-04-21 10:48:24 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 450505 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 558073 # Packet count per connected master and slave (bytes)
2016-04-09 18:13:40 +02:00
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72875 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 72875 # Packet count per connected master and slave (bytes)
2016-04-21 10:48:24 +02:00
system.membus.pkt_count::total 630948 # Packet count per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
2016-04-09 18:13:40 +02:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 112 # Cumulative packet size per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4152 # Cumulative packet size per connected master and slave (bytes)
2016-04-21 10:48:24 +02:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16433756 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16597145 # Cumulative packet size per connected master and slave (bytes)
2016-04-09 18:13:40 +02:00
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes)
2016-04-21 10:48:24 +02:00
system.membus.pkt_size::total 18914265 # Cumulative packet size per connected master and slave (bytes)
2016-04-09 18:13:40 +02:00
system.membus.snoops 487 # Total snoops (count)
2016-04-21 10:48:24 +02:00
system.membus.snoop_fanout::samples 402739 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2016-04-21 10:48:24 +02:00
system.membus.snoop_fanout::1 402739 100.00% 100.00% # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2016-04-21 10:48:24 +02:00
system.membus.snoop_fanout::total 402739 # Request fanout histogram
system.membus.reqLayer0.occupancy 83678000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2016-04-09 18:13:40 +02:00
system.membus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
2016-04-21 10:48:24 +02:00
system.membus.reqLayer2.occupancy 1737499 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
2016-04-21 10:48:24 +02:00
system.membus.reqLayer5.occupancy 875953366 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
2016-04-21 10:48:24 +02:00
system.membus.respLayer2.occupancy 978576250 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-04-09 18:13:40 +02:00
system.membus.respLayer3.occupancy 1182123 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
2015-12-04 01:19:05 +01:00
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
2014-11-12 15:05:25 +01:00
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
2015-12-04 01:19:05 +01:00
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
2012-08-28 20:30:25 +02:00
system.cpu.kern.inst.arm 0 # number of arm instructions executed
2015-09-25 13:27:03 +02:00
system.cpu.kern.inst.quiesce 3037 # number of quiesce instructions executed
2012-08-28 20:30:25 +02:00
---------- End Simulation Statistics ----------
