2011-01-18 23:30:06 +01:00
---------- Begin Simulation Statistics ----------
2015-11-06 09:26:50 +01:00
sim_seconds 0.000019 # Number of seconds simulated
sim_ticks 18741000 # Number of ticks simulated
final_tick 18741000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2011-01-18 23:30:06 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
2016-02-10 10:08:27 +01:00
host_inst_rate 84742 # Simulator instruction rate (inst/s)
host_op_rate 99228 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 345728368 # Simulator tick rate (ticks/s)
host_mem_usage 266024 # Number of bytes of host memory used
host_seconds 0.05 # Real time elapsed on the host
2015-04-30 21:17:43 +02:00
sim_insts 4592 # Number of instructions simulated
sim_ops 5378 # Number of ops (including micro ops) simulated
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2015-11-06 09:26:50 +01:00
system.physmem.bytes_read::cpu.inst 18432 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8064 # Number of bytes read from this memory
2014-12-23 15:31:20 +01:00
system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 # Number of bytes read from this memory
2015-11-06 09:26:50 +01:00
system.physmem.bytes_read::total 28224 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 18432 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 18432 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 288 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 126 # Number of read requests responded to by this memory
2014-12-23 15:31:20 +01:00
system.physmem.num_reads::cpu.l2cache.prefetcher 27 # Number of read requests responded to by this memory
2015-11-06 09:26:50 +01:00
system.physmem.num_reads::total 441 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 983512086 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 430286538 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher 92204258 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1506002881 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 983512086 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 983512086 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 983512086 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 430286538 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher 92204258 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1506002881 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 442 # Number of read requests accepted
2013-11-01 16:56:34 +01:00
system.physmem.writeReqs 0 # Number of write requests accepted
2015-11-06 09:26:50 +01:00
system.physmem.readBursts 442 # Number of DRAM read bursts, including those serviced by the write queue
2013-11-01 16:56:34 +01:00
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
2015-11-06 09:26:50 +01:00
system.physmem.bytesReadDRAM 28288 # Total number of bytes read from DRAM
2013-11-01 16:56:34 +01:00
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
2015-11-06 09:26:50 +01:00
system.physmem.bytesReadSys 28288 # Total read bytes from the system interface side
2013-11-01 16:56:34 +01:00
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
2015-11-06 09:26:50 +01:00
system.physmem.perBankRdBursts::0 101 # Per bank write bursts
system.physmem.perBankRdBursts::1 48 # Per bank write bursts
2014-12-23 15:31:20 +01:00
system.physmem.perBankRdBursts::2 19 # Per bank write bursts
2015-03-02 11:04:20 +01:00
system.physmem.perBankRdBursts::3 44 # Per bank write bursts
2015-11-06 09:26:50 +01:00
system.physmem.perBankRdBursts::4 19 # Per bank write bursts
system.physmem.perBankRdBursts::5 37 # Per bank write bursts
system.physmem.perBankRdBursts::6 46 # Per bank write bursts
2014-12-23 15:31:20 +01:00
system.physmem.perBankRdBursts::7 10 # Per bank write bursts
system.physmem.perBankRdBursts::8 4 # Per bank write bursts
2015-11-06 09:26:50 +01:00
system.physmem.perBankRdBursts::9 8 # Per bank write bursts
system.physmem.perBankRdBursts::10 27 # Per bank write bursts
2014-09-20 23:18:53 +02:00
system.physmem.perBankRdBursts::11 47 # Per bank write bursts
system.physmem.perBankRdBursts::12 17 # Per bank write bursts
2015-11-06 09:26:50 +01:00
system.physmem.perBankRdBursts::13 8 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.perBankRdBursts::14 0 # Per bank write bursts
2015-11-06 09:26:50 +01:00
system.physmem.perBankRdBursts::15 7 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
2015-11-06 09:26:50 +01:00
system.physmem.totGap 18727500 # Total gap between requests
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2015-11-06 09:26:50 +01:00
system.physmem.readPktSize::6 442 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
2015-11-06 09:26:50 +01:00
system.physmem.rdQLenPdf::0 245 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 134 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 33 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
2015-03-02 11:04:20 +01:00
system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
2015-07-30 09:42:27 +02:00
system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see
2014-12-23 15:31:20 +01:00
system.physmem.rdQLenPdf::7 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 2 # What read queue length does an incoming req see
2015-07-30 09:42:27 +02:00
system.physmem.rdQLenPdf::9 2 # What read queue length does an incoming req see
2014-12-23 15:31:20 +01:00
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
2015-11-06 09:26:50 +01:00
system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 425.650794 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 288.378165 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 357.476918 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 7 11.11% 11.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 21 33.33% 44.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 8 12.70% 57.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 7 11.11% 68.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 5 7.94% 76.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1 1.59% 77.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 2 3.17% 80.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 12 19.05% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation
system.physmem.totQLat 3434000 # Total ticks spent queuing
system.physmem.totMemAccLat 11721500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2210000 # Total ticks spent in databus transfers
system.physmem.avgQLat 7769.23 # Average queueing delay per DRAM burst
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2015-11-06 09:26:50 +01:00
system.physmem.avgMemAccLat 26519.23 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1509.42 # Average DRAM read bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
2015-11-06 09:26:50 +01:00
system.physmem.avgRdBWSys 1509.42 # Average system read bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2015-11-06 09:26:50 +01:00
system.physmem.busUtil 11.79 # Data bus utilization in percentage
system.physmem.busUtilRead 11.79 # Data bus utilization in percentage for reads
2013-11-01 16:56:34 +01:00
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
2015-07-30 09:42:27 +02:00
system.physmem.avgRdQLen 1.81 # Average read queue length when enqueuing
2013-11-01 16:56:34 +01:00
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
2015-11-06 09:26:50 +01:00
system.physmem.readRowHits 370 # Number of row buffer hits during reads
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
2015-11-06 09:26:50 +01:00
system.physmem.readRowHitRate 83.71 # Row buffer hit rate for reads
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
2015-11-06 09:26:50 +01:00
system.physmem.avgGap 42369.91 # Average gap between requests
system.physmem.pageHitRate 83.71 # Row buffer hit rate, read and write combined
2015-04-30 21:17:43 +02:00
system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ)
2015-11-06 09:26:50 +01:00
system.physmem_0.readEnergy 2160600 # Energy for read commands per rank (pJ)
2014-12-23 15:31:20 +01:00
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
2015-11-06 09:26:50 +01:00
system.physmem_0.actBackEnergy 10786680 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 37500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 14457615 # Total energy per rank (pJ)
system.physmem_0.averagePower 913.160587 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 7000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::REF 520000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
2015-11-06 09:26:50 +01:00
system.physmem_0.memoryStateTime::ACT 15319250 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
2015-03-02 11:04:20 +01:00
system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ)
2015-11-06 09:26:50 +01:00
system.physmem_1.readEnergy 811200 # Energy for read commands per rank (pJ)
2014-12-23 15:31:20 +01:00
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
2015-11-06 09:26:50 +01:00
system.physmem_1.actBackEnergy 9859005 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 851250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 12737220 # Total energy per rank (pJ)
system.physmem_1.averagePower 804.498342 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 2184750 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::REF 520000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
2015-11-06 09:26:50 +01:00
system.physmem_1.memoryStateTime::ACT 13949750 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
2015-11-06 09:26:50 +01:00
system.cpu.branchPred.lookups 2341 # Number of BP lookups
system.cpu.branchPred.condPredicted 1389 # Number of conditional branches predicted
2015-07-03 16:15:03 +02:00
system.cpu.branchPred.condIncorrect 508 # Number of conditional branches incorrect
2015-11-06 09:26:50 +01:00
system.cpu.branchPred.BTBLookups 838 # Number of BTB lookups
system.cpu.branchPred.BTBHits 447 # Number of BTB hits
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2015-11-06 09:26:50 +01:00
system.cpu.branchPred.BTBHitPct 53.341289 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 290 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 57 # Number of incorrect RAS predictions.
2014-12-23 15:31:20 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2011-05-23 17:59:13 +02:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2011-05-23 17:59:13 +02:00
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 13 # Number of system calls
2015-11-06 09:26:50 +01:00
system.cpu.numCycles 37483 # number of cpu cycles simulated
2011-05-23 17:59:13 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
2015-11-06 09:26:50 +01:00
system.cpu.fetch.icacheStallCycles 6059 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 11274 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2341 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 737 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 8204 # Number of cycles fetch has run and was not squashing or blocked
2015-07-03 16:15:03 +02:00
system.cpu.fetch.SquashCycles 1059 # Number of cycles fetch has spent squashing
2015-11-06 09:26:50 +01:00
system.cpu.fetch.MiscStallCycles 143 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
2015-03-02 11:04:20 +01:00
system.cpu.fetch.PendingTrapStallCycles 303 # Number of stall cycles due to pending traps
2015-11-06 09:26:50 +01:00
system.cpu.fetch.IcacheWaitRetryStallCycles 363 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 3834 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 177 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 15601 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.845843 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.199579 # Number of instructions fetched each cycle (Total)
2011-05-23 17:59:13 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2015-11-06 09:26:50 +01:00
system.cpu.fetch.rateDist::0 9385 60.16% 60.16% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 2463 15.79% 75.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 526 3.37% 79.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 3227 20.68% 100.00% # Number of instructions fetched each cycle (Total)
2011-05-23 17:59:13 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
2014-09-20 23:18:53 +02:00
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
2015-11-06 09:26:50 +01:00
system.cpu.fetch.rateDist::total 15601 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.062455 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.300776 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 5749 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 4322 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 5029 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 132 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 369 # Number of cycles decode is squashing
2015-09-25 13:27:03 +02:00
system.cpu.decode.BranchResolved 331 # Number of times decode resolved a branch
2015-11-06 09:26:50 +01:00
system.cpu.decode.BranchMispred 162 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 9880 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 1586 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 369 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 6811 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 1118 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 2339 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 4089 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 875 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 8892 # Number of instructions processed by rename
system.cpu.rename.SquashedInsts 417 # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents 21 # Number of times rename has blocked due to ROB full
2015-04-30 21:17:43 +02:00
system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full
2015-11-06 09:26:50 +01:00
system.cpu.rename.LQFullEvents 28 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 772 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 9259 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 40331 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 9781 # Number of integer rename lookups
2015-03-02 11:04:20 +01:00
system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups
2014-09-03 13:42:59 +02:00
system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed
2015-11-06 09:26:50 +01:00
system.cpu.rename.UndoneMaps 3765 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 29 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 323 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 1800 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1272 # Number of stores inserted to the mem dependence unit.
2014-09-20 23:18:53 +02:00
system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
2015-11-06 09:26:50 +01:00
system.cpu.iq.iqInstsAdded 8358 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 38 # Number of non-speculative instructions added to the IQ
2015-09-25 13:27:03 +02:00
system.cpu.iq.iqInstsIssued 7148 # Number of instructions issued
2015-11-06 09:26:50 +01:00
system.cpu.iq.iqSquashedInstsIssued 184 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 3018 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 7856 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 15601 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.458176 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 0.848338 # Number of insts issued each cycle
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2015-11-06 09:26:50 +01:00
system.cpu.iq.issued_per_cycle::0 11391 73.01% 73.01% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 1965 12.60% 85.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 1598 10.24% 95.85% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 601 3.85% 99.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 46 0.29% 100.00% # Number of insts issued each cycle
2014-09-20 23:18:53 +02:00
system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
2014-09-20 23:18:53 +02:00
system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle
2015-11-06 09:26:50 +01:00
system.cpu.iq.issued_per_cycle::total 15601 # Number of insts issued each cycle
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2015-11-06 09:26:50 +01:00
system.cpu.iq.fu_full::IntAlu 413 28.70% 28.70% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 28.70% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 28.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 28.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 28.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 28.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.70% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 475 33.01% 61.71% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 551 38.29% 100.00% # attempts to use FU when none available
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
2015-11-06 09:26:50 +01:00
system.cpu.iq.FU_type_0::IntAlu 4480 62.67% 62.67% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.74% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.74% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.74% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.74% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.74% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.74% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.74% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.74% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.74% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.74% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.74% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.74% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.74% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.74% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.74% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.74% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.74% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.74% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.74% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.74% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.74% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.74% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.74% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.74% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.79% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.79% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.79% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.79% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 1582 22.13% 84.92% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 1078 15.08% 100.00% # Type of FU issued
2011-05-23 17:59:13 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2015-09-25 13:27:03 +02:00
system.cpu.iq.FU_type_0::total 7148 # Type of FU issued
2015-11-06 09:26:50 +01:00
system.cpu.iq.rate 0.190700 # Inst issue rate
system.cpu.iq.fu_busy_cnt 1439 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.201315 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 31476 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 11405 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 6562 # Number of integer instruction queue wakeup accesses
2014-12-23 15:31:20 +01:00
system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads
2015-03-02 11:04:20 +01:00
system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
2014-09-20 23:18:53 +02:00
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
2015-11-06 09:26:50 +01:00
system.cpu.iq.int_alu_accesses 8559 # Number of integer alu accesses
2014-12-23 15:31:20 +01:00
system.cpu.iq.fp_alu_accesses 28 # Number of floating point alu accesses
2015-11-06 09:26:50 +01:00
system.cpu.iew.lsq.thread0.forwLoads 11 # Number of loads that had data forwarded from stores
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2015-11-06 09:26:50 +01:00
system.cpu.iew.lsq.thread0.squashedLoads 773 # Number of loads squashed
2014-12-23 15:31:20 +01:00
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
2014-09-20 23:18:53 +02:00
system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations
2015-11-06 09:26:50 +01:00
system.cpu.iew.lsq.thread0.squashedStores 334 # Number of stores squashed
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2015-11-06 09:26:50 +01:00
system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled
2015-03-02 11:04:20 +01:00
system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked
2011-05-23 17:59:13 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2015-11-06 09:26:50 +01:00
system.cpu.iew.iewSquashCycles 369 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 385 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 8410 # Number of instructions dispatched to IQ
2014-09-20 23:18:53 +02:00
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
2015-11-06 09:26:50 +01:00
system.cpu.iew.iewDispLoadInsts 1800 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 1272 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
2015-07-03 16:15:03 +02:00
system.cpu.iew.iewLSQFullEvents 6 # Number of times the LSQ has become full, causing a stall
2014-09-20 23:18:53 +02:00
system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations
2015-07-03 16:15:03 +02:00
system.cpu.iew.predictedTakenIncorrect 67 # Number of branches that were predicted taken incorrectly
2015-04-30 21:17:43 +02:00
system.cpu.iew.predictedNotTakenIncorrect 294 # Number of branches that were predicted not taken incorrectly
2015-07-03 16:15:03 +02:00
system.cpu.iew.branchMispredicts 361 # Number of branch mispredicts detected at execute
2015-11-06 09:26:50 +01:00
system.cpu.iew.iewExecutedInsts 6751 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 1398 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 397 # Number of squashed instructions skipped in execute
2011-05-23 17:59:13 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
2014-09-20 23:18:53 +02:00
system.cpu.iew.exec_nop 14 # number of nop insts executed
2015-11-06 09:26:50 +01:00
system.cpu.iew.exec_refs 2419 # number of memory reference insts executed
system.cpu.iew.exec_branches 1275 # Number of branches executed
system.cpu.iew.exec_stores 1021 # Number of stores executed
system.cpu.iew.exec_rate 0.180108 # Inst execution rate
system.cpu.iew.wb_sent 6621 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 6578 # cumulative count of insts written-back
system.cpu.iew.wb_producers 2993 # num instructions producing a value
system.cpu.iew.wb_consumers 5408 # num instructions consuming a value
system.cpu.iew.wb_rate 0.175493 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.553439 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 2586 # The number of squashed insts skipped by commit
2013-01-08 14:54:16 +01:00
system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards
2015-11-06 09:26:50 +01:00
system.cpu.commit.branchMispredicts 348 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 15057 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.357176 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.003286 # Number of insts commited each cycle
2011-04-20 03:45:23 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2015-11-06 09:26:50 +01:00
system.cpu.commit.committed_per_cycle::0 12412 82.43% 82.43% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 1386 9.21% 91.64% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 592 3.93% 95.57% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 296 1.97% 97.54% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 173 1.15% 98.68% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 78 0.52% 99.20% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 45 0.30% 99.50% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 32 0.21% 99.71% # Number of insts commited each cycle
2015-09-25 13:27:03 +02:00
system.cpu.commit.committed_per_cycle::8 43 0.29% 100.00% # Number of insts commited each cycle
2011-04-20 03:45:23 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2015-11-06 09:26:50 +01:00
system.cpu.commit.committed_per_cycle::total 15057 # Number of insts commited each cycle
2015-04-30 21:17:43 +02:00
system.cpu.commit.committedInsts 4592 # Number of instructions committed
system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed
2011-05-23 17:59:13 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
2014-09-03 13:42:59 +02:00
system.cpu.commit.refs 1965 # Number of memory references committed
system.cpu.commit.loads 1027 # Number of loads committed
2011-04-20 03:45:23 +02:00
system.cpu.commit.membars 12 # Number of memory barriers committed
2015-04-30 21:17:43 +02:00
system.cpu.commit.branches 1008 # Number of branches committed
2011-05-23 17:59:13 +02:00
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
2014-09-03 13:42:59 +02:00
system.cpu.commit.int_insts 4624 # Number of committed integer instructions.
2011-05-23 17:59:13 +02:00
system.cpu.commit.function_calls 82 # Number of function calls committed.
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2015-04-30 21:17:43 +02:00
system.cpu.commit.op_class_0::IntAlu 3406 63.33% 63.33% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 4 0.07% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.41% # Class of committed instruction
2014-09-03 13:42:59 +02:00
system.cpu.commit.op_class_0::SimdFloatMisc 3 0.06% 63.46% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2015-04-30 21:17:43 +02:00
system.cpu.commit.op_class_0::total 5378 # Class of committed instruction
2015-07-03 16:15:03 +02:00
system.cpu.commit.bw_lim_events 43 # number cycles where commit BW limit reached
2015-11-06 09:26:50 +01:00
system.cpu.rob.rob_reads 22821 # The number of ROB reads
system.cpu.rob.rob_writes 16478 # The number of ROB writes
system.cpu.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 21882 # Total number of cycles that the CPU has spent unscheduled due to idling
2015-04-30 21:17:43 +02:00
system.cpu.committedInsts 4592 # Number of Instructions Simulated
system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated
2015-11-06 09:26:50 +01:00
system.cpu.cpi 8.162674 # CPI: Cycles Per Instruction
system.cpu.cpi_total 8.162674 # CPI: Total CPI of All Threads
system.cpu.ipc 0.122509 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.122509 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 6722 # number of integer regfile reads
system.cpu.int_regfile_writes 3755 # number of integer regfile writes
2014-09-20 23:18:53 +02:00
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
2015-11-06 09:26:50 +01:00
system.cpu.cc_regfile_reads 23977 # number of cc regfile reads
system.cpu.cc_regfile_writes 2903 # number of cc regfile writes
system.cpu.misc_regfile_reads 2611 # number of misc regfile reads
2013-01-08 14:54:16 +01:00
system.cpu.misc_regfile_writes 24 # number of misc regfile writes
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.replacements 1 # number of replacements
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.tagsinuse 84.551975 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1908 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 13.342657 # Average number of references to valid blocks.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.occ_blocks::cpu.data 84.551975 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.165141 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.165141 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
2015-03-02 11:04:20 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 0.277344 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 4677 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 4677 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 1166 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1166 # number of ReadReq hits
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
2015-11-06 09:26:50 +01:00
system.cpu.dcache.demand_hits::cpu.data 1888 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 1888 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 1888 # number of overall hits
system.cpu.dcache.overall_hits::total 1888 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 166 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 166 # number of ReadReq misses
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_misses::cpu.data 191 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 191 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
2015-11-06 09:26:50 +01:00
system.cpu.dcache.demand_misses::cpu.data 357 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 357 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 357 # number of overall misses
system.cpu.dcache.overall_misses::total 357 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 10689500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 10689500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 7727500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 7727500 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 125000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 125000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 18417000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 18417000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 18417000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 18417000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1332 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1332 # number of ReadReq accesses(hits+misses)
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
2015-11-06 09:26:50 +01:00
system.cpu.dcache.demand_accesses::cpu.data 2245 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2245 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2245 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2245 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.124625 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.124625 # miss rate for ReadReq accesses
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.209200 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.209200 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses
2015-11-06 09:26:50 +01:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.159020 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.159020 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.159020 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.159020 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64394.578313 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 64394.578313 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40458.115183 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 40458.115183 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62500 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62500 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 51588.235294 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 51588.235294 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 51588.235294 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 51588.235294 # average overall miss latency
2014-12-23 15:31:20 +01:00
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.cpu.dcache.blocked_cycles::no_targets 846 # number of cycles access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2015-11-06 09:26:50 +01:00
system.cpu.dcache.avg_blocked_cycles::no_targets 47 # average number of cycles each access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
2015-11-06 09:26:50 +01:00
system.cpu.dcache.writebacks::writebacks 1 # number of writebacks
system.cpu.dcache.writebacks::total 1 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 63 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 150 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 150 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
2015-11-06 09:26:50 +01:00
system.cpu.dcache.demand_mshr_hits::cpu.data 213 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 213 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 213 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 213 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 103 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.dcache.demand_mshr_misses::cpu.data 144 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6989000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6989000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2447000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2447000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9436000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 9436000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9436000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 9436000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.077327 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.077327 # mshr miss rate for ReadReq accesses
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses
2015-11-06 09:26:50 +01:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064143 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.064143 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064143 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.064143 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67854.368932 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67854.368932 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59682.926829 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59682.926829 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65527.777778 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 65527.777778 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65527.777778 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 65527.777778 # average overall mshr miss latency
2014-12-23 15:31:20 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-11-06 09:26:50 +01:00
system.cpu.icache.tags.replacements 43 # number of replacements
system.cpu.icache.tags.tagsinuse 137.647063 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 3470 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 296 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 11.722973 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-11-06 09:26:50 +01:00
system.cpu.icache.tags.occ_blocks::cpu.inst 137.647063 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.268842 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.268842 # Average percentage of cache occupancy
2015-03-02 11:04:20 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 253 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id
2015-03-02 11:04:20 +01:00
system.cpu.icache.tags.occ_task_id_percent::1024 0.494141 # Percentage of cache occupancy per task id
2015-11-06 09:26:50 +01:00
system.cpu.icache.tags.tag_accesses 7960 # Number of tag accesses
system.cpu.icache.tags.data_accesses 7960 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 3470 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 3470 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 3470 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 3470 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 3470 # number of overall hits
system.cpu.icache.overall_hits::total 3470 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 362 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 362 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 362 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 362 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 362 # number of overall misses
system.cpu.icache.overall_misses::total 362 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 22661491 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 22661491 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 22661491 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 22661491 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 22661491 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 22661491 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 3832 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 3832 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 3832 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 3832 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 3832 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 3832 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094468 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.094468 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.094468 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.094468 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.094468 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.094468 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62600.803867 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 62600.803867 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 62600.803867 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 62600.803867 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 62600.803867 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 62600.803867 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 8953 # number of cycles access was blocked
2015-03-02 11:04:20 +01:00
system.cpu.icache.blocked_cycles::no_targets 33 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.cpu.icache.blocked::no_mshrs 96 # number of cycles access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 93.260417 # average number of cycles each access was blocked
2015-03-02 11:04:20 +01:00
system.cpu.icache.avg_blocked_cycles::no_targets 33 # average number of cycles each access was blocked
2011-05-23 17:59:13 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
2015-11-06 09:26:50 +01:00
system.cpu.icache.writebacks::writebacks 43 # number of writebacks
system.cpu.icache.writebacks::total 43 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 65 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 65 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 65 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 65 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 65 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 65 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 297 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 297 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 297 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 297 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 297 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 297 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19893491 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 19893491 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19893491 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 19893491 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19893491 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 19893491 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.077505 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.077505 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.077505 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.077505 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.077505 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.077505 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66981.451178 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66981.451178 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66981.451178 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 66981.451178 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66981.451178 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 66981.451178 # average overall mshr miss latency
2011-05-23 17:59:13 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.replacements 0 # number of replacements
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.tagsinuse 19.860815 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 10 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 48 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.208333 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.occ_blocks::writebacks 10.581774 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.279041 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.000646 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000566 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.001212 # Average percentage of cache occupancy
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.tags.occ_task_id_blocks::1022 16 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32 # Occupied blocks per task id
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.tags.occ_task_id_percent::1022 0.000977 # Percentage of cache occupancy per task id
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.001953 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 7643 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 7643 # Number of data accesses
system.cpu.l2cache.WritebackClean_hits::writebacks 33 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 33 # number of WritebackClean hits
2014-09-20 23:18:53 +02:00
system.cpu.l2cache.ReadExReq_hits::cpu.data 11 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 11 # number of ReadExReq hits
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 7 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 7 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 2 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 7 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 13 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 20 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 7 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 13 # number of overall hits
system.cpu.l2cache.overall_hits::total 20 # number of overall hits
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 30 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 30 # number of ReadExReq misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 290 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 290 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 101 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 101 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 290 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 131 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 421 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 290 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 131 # number of overall misses
system.cpu.l2cache.overall_misses::total 421 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2313000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 2313000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 19544000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 19544000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6815000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 6815000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 19544000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 9128000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 28672000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 19544000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 9128000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 28672000 # number of overall miss cycles
system.cpu.l2cache.WritebackClean_accesses::writebacks 33 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 33 # number of WritebackClean accesses(hits+misses)
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses)
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 297 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 297 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 103 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 103 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 297 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 144 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 441 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 297 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 144 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 441 # number of overall (read+write) accesses
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.731707 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.731707 # miss rate for ReadExReq accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.976431 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.976431 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.980583 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.980583 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.976431 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.909722 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.954649 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.976431 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.909722 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.954649 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77100 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77100 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 67393.103448 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 67393.103448 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 67475.247525 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 67475.247525 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67393.103448 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69679.389313 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 68104.513064 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67393.103448 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69679.389313 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 68104.513064 # average overall miss latency
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2013-01-07 19:05:54 +01:00
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
2013-01-07 19:05:54 +01:00
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2013-01-07 19:05:54 +01:00
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 5 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 5 # number of ReadSharedReq MSHR hits
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 53 # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total 53 # number of HardPFReq MSHR misses
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 30 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 30 # number of ReadExReq MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 289 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 289 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 96 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 96 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 289 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 126 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 415 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 126 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 53 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 468 # number of overall MSHR misses
2015-07-30 09:42:27 +02:00
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1625926 # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1625926 # number of HardPFReq MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2133000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2133000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 17760500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 17760500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5946500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5946500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17760500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8079500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 25840000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17760500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8079500 # number of overall MSHR miss cycles
2015-07-30 09:42:27 +02:00
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1625926 # number of overall MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_mshr_miss_latency::total 27465926 # number of overall MSHR miss cycles
2014-09-20 23:18:53 +02:00
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.731707 # mshr miss rate for ReadExReq accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.973064 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.973064 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.932039 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.932039 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.973064 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.875000 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.941043 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.973064 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.875000 # mshr miss rate for overall accesses
2014-09-20 23:18:53 +02:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::total 1.061224 # mshr miss rate for overall accesses
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 30677.849057 # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 30677.849057 # average HardPFReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71100 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71100 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 61455.017301 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 61455.017301 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61942.708333 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61942.708333 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61455.017301 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64123.015873 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62265.060241 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61455.017301 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64123.015873 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 30677.849057 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58687.876068 # average overall mshr miss latency
2013-01-07 19:05:54 +01:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoop_filter.tot_requests 485 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 74 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 11 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoop_filter.tot_snoops 409 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 368 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 41 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution
2016-02-10 10:08:27 +01:00
system.cpu.toL2Bus.trans_dist::WritebackClean 44 # Transaction distribution
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.trans_dist::CleanEvict 383 # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq 69 # Transaction distribution
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.trans_dist::ReadCleanReq 297 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution
2016-02-10 10:08:27 +01:00
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 636 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 288 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 924 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21696 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9216 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 30912 # Cumulative packet size per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoops 452 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 893 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.549832 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.582857 # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoop_fanout::0 443 49.61% 49.61% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 409 45.80% 95.41% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 41 4.59% 100.00% # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 893 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 286500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 444499 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 216995 # Layer occupancy (ticks)
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.membus.trans_dist::ReadResp 410 # Transaction distribution
2014-12-23 15:31:20 +01:00
system.membus.trans_dist::ReadExReq 30 # Transaction distribution
system.membus.trans_dist::ReadExResp 30 # Transaction distribution
2015-11-06 09:26:50 +01:00
system.membus.trans_dist::ReadSharedReq 412 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 882 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 882 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28160 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes)
2014-12-23 15:31:20 +01:00
system.membus.snoops 0 # Total snoops (count)
2015-11-06 09:26:50 +01:00
system.membus.snoop_fanout::samples 442 # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.membus.snoop_fanout::0 442 100.00% 100.00% # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.membus.snoop_fanout::total 442 # Request fanout histogram
system.membus.reqLayer0.occupancy 559944 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 3.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 2320000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 12.4 # Layer utilization (%)
2011-01-18 23:30:06 +01:00
---------- End Simulation Statistics ----------
