sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity
gem5/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt

1591 lines
187 KiB
Text
Raw Normal View History

X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
---------- Begin Simulation Statistics ----------
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
sim_seconds 5.125902 # Number of seconds simulated
sim_ticks 5125902116500 # Number of ticks simulated
final_tick 5125902116500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
host_inst_rate 196886 # Simulator instruction rate (inst/s)
host_op_rate 389187 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2473535129 # Simulator tick rate (ticks/s)
host_mem_usage 743248 # Number of bytes of host memory used
host_seconds 2072.30 # Real time elapsed on the host
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
sim_insts 408006726 # Number of instructions simulated
sim_ops 806511598 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.physmem.bytes_read::cpu.dtb.walker 4800 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 1043840 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10813760 # Number of bytes read from this memory
system.physmem.bytes_read::total 11891200 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1043840 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1043840 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 6604544 # Number of bytes written to this memory
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.physmem.bytes_written::total 9594624 # Number of bytes written to this memory
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.physmem.num_reads::cpu.dtb.walker 75 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 16310 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 168965 # Number of read requests responded to by this memory
system.physmem.num_reads::total 185800 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 103196 # Number of write requests responded to by this memory
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.physmem.num_writes::total 149916 # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide 5531 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 936 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 203640 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2109631 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2319826 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 203640 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 203640 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1288465 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::pc.south_bridge.ide 583328 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1871792 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1288465 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide 588859 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 936 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 203640 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2109631 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 4191618 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 185800 # Number of read requests accepted
system.physmem.writeReqs 149916 # Number of write requests accepted
system.physmem.readBursts 185800 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 149916 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 11876224 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 14976 # Total number of bytes read from write queue
system.physmem.bytesWritten 9592960 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 11891200 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 9594624 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 234 # Number of DRAM read bursts serviced by the write queue
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.physmem.neitherReadNorWriteReqs 1736 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 11489 # Per bank write bursts
system.physmem.perBankRdBursts::1 10946 # Per bank write bursts
system.physmem.perBankRdBursts::2 11982 # Per bank write bursts
system.physmem.perBankRdBursts::3 11463 # Per bank write bursts
system.physmem.perBankRdBursts::4 11671 # Per bank write bursts
system.physmem.perBankRdBursts::5 11298 # Per bank write bursts
system.physmem.perBankRdBursts::6 11252 # Per bank write bursts
system.physmem.perBankRdBursts::7 11687 # Per bank write bursts
system.physmem.perBankRdBursts::8 11071 # Per bank write bursts
system.physmem.perBankRdBursts::9 11217 # Per bank write bursts
system.physmem.perBankRdBursts::10 11355 # Per bank write bursts
system.physmem.perBankRdBursts::11 12125 # Per bank write bursts
system.physmem.perBankRdBursts::12 11861 # Per bank write bursts
system.physmem.perBankRdBursts::13 12651 # Per bank write bursts
system.physmem.perBankRdBursts::14 12184 # Per bank write bursts
system.physmem.perBankRdBursts::15 11314 # Per bank write bursts
system.physmem.perBankWrBursts::0 9710 # Per bank write bursts
system.physmem.perBankWrBursts::1 9082 # Per bank write bursts
system.physmem.perBankWrBursts::2 8978 # Per bank write bursts
system.physmem.perBankWrBursts::3 8996 # Per bank write bursts
system.physmem.perBankWrBursts::4 9462 # Per bank write bursts
system.physmem.perBankWrBursts::5 9601 # Per bank write bursts
system.physmem.perBankWrBursts::6 9097 # Per bank write bursts
system.physmem.perBankWrBursts::7 8837 # Per bank write bursts
system.physmem.perBankWrBursts::8 9327 # Per bank write bursts
system.physmem.perBankWrBursts::9 9159 # Per bank write bursts
system.physmem.perBankWrBursts::10 9532 # Per bank write bursts
system.physmem.perBankWrBursts::11 9463 # Per bank write bursts
system.physmem.perBankWrBursts::12 9618 # Per bank write bursts
system.physmem.perBankWrBursts::13 9862 # Per bank write bursts
system.physmem.perBankWrBursts::14 9881 # Per bank write bursts
system.physmem.perBankWrBursts::15 9285 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.physmem.numWrRetry 4 # Number of times write queue was full causing retry
system.physmem.totGap 5125902065000 # Total gap between requests
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.physmem.readPktSize::6 185800 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.physmem.writePktSize::6 149916 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 170703 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 12067 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 2038 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 421 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 56 # What read queue length does an incoming req see
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.physmem.rdQLenPdf::6 33 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.rdQLenPdf::11 28 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 26 # What read queue length does an incoming req see
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.rdQLenPdf::13 26 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
test: update stats Update stats for recent changes. Mostly minor changes in register access stats due to addition of new cc register type and slightly different (and more accurate) classification of int vs. fp register accesses.
2013-10-16 16:44:12 +02:00
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.physmem.wrQLenPdf::15 2237 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 2934 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 7172 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 7637 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 7787 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 8527 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 8842 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 9565 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 10246 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 11384 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 10610 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 9929 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 9208 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 9073 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 7958 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 7723 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 7760 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 7617 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 249 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 229 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 241 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 223 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 222 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 205 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 214 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 183 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 169 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 170 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 164 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 174 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 170 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 142 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 139 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 121 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 108 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 94 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 63 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 46 # What write queue length does an incoming req see
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.wrQLenPdf::53 46 # What write queue length does an incoming req see
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.physmem.wrQLenPdf::54 43 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 38 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 46 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 41 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 38 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 37 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 29 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 23 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 11 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 72846 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 294.719271 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 174.256286 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 318.919065 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 28471 39.08% 39.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 17446 23.95% 63.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 7310 10.03% 73.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 4243 5.82% 78.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2987 4.10% 82.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1984 2.72% 85.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1403 1.93% 87.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1126 1.55% 89.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 7876 10.81% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 72846 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 7377 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 25.152094 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 560.212559 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 7376 99.99% 99.99% # Reads before turning the bus around for writes
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.physmem.rdPerTurnAround::total 7377 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 7377 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 20.318558 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.615023 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 12.539295 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 6330 85.81% 85.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 64 0.87% 86.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 33 0.45% 87.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 268 3.63% 90.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 287 3.89% 94.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 24 0.33% 94.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 24 0.33% 95.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 16 0.22% 95.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 20 0.27% 95.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 2 0.03% 95.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 6 0.08% 95.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 2 0.03% 95.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 237 3.21% 99.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 3 0.04% 99.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 2 0.03% 99.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 3 0.04% 99.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 11 0.15% 99.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 1 0.01% 99.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 12 0.16% 99.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 1 0.01% 99.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 3 0.04% 99.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111 2 0.03% 99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 6 0.08% 99.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119 3 0.04% 99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 1 0.01% 99.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 13 0.18% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139 1 0.01% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 1 0.01% 99.99% # Writes before turning the bus around for reads
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.wrPerTurnAround::144-147 1 0.01% 100.00% # Writes before turning the bus around for reads
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.physmem.wrPerTurnAround::total 7377 # Writes before turning the bus around for reads
system.physmem.totQLat 2068154250 # Total ticks spent queuing
system.physmem.totMemAccLat 5547516750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 927830000 # Total ticks spent in databus transfers
system.physmem.avgQLat 11145.11 # Average queueing delay per DRAM burst
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.physmem.avgMemAccLat 29895.11 # Average memory access latency per DRAM burst
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.avgRdBW 2.32 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 2.32 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.87 # Average system write bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.busUtil 0.03 # Data bus utilization in percentage
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing
system.physmem.avgWrQLen 21.36 # Average write queue length when enqueuing
system.physmem.readRowHits 151753 # Number of row buffer hits during reads
system.physmem.writeRowHits 110856 # Number of row buffer hits during writes
system.physmem.readRowHitRate 81.78 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 73.95 # Row buffer hit rate for writes
system.physmem.avgGap 15268566.48 # Average gap between requests
system.physmem.pageHitRate 78.28 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 4919748958000 # Time in different power states
system.physmem.memoryStateTime::REF 171165020000 # Time in different power states
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.physmem.memoryStateTime::ACT 34988035500 # Time in different power states
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.physmem.actEnergy::0 267185520 # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1 283530240 # Energy for activate commands per rank (pJ)
system.physmem.preEnergy::0 145785750 # Energy for precharge commands per rank (pJ)
system.physmem.preEnergy::1 154704000 # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0 715946400 # Energy for read commands per rank (pJ)
system.physmem.readEnergy::1 731460600 # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0 477984240 # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1 493302960 # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0 334798779120 # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1 334798779120 # Energy for refresh commands per rank (pJ)
system.physmem.actBackEnergy::0 129305495790 # Energy for active background per rank (pJ)
system.physmem.actBackEnergy::1 129519356940 # Energy for active background per rank (pJ)
system.physmem.preBackEnergy::0 2962113436500 # Energy for precharge background per rank (pJ)
system.physmem.preBackEnergy::1 2961925839000 # Energy for precharge background per rank (pJ)
system.physmem.totalEnergy::0 3427824613320 # Total energy per rank (pJ)
system.physmem.totalEnergy::1 3427906972860 # Total energy per rank (pJ)
system.physmem.averagePower::0 668.726542 # Core power per rank (mW)
system.physmem.averagePower::1 668.742609 # Core power per rank (mW)
system.membus.trans_dist::ReadReq 662592 # Transaction distribution
system.membus.trans_dist::ReadResp 662582 # Transaction distribution
system.membus.trans_dist::WriteReq 13889 # Transaction distribution
system.membus.trans_dist::WriteResp 13889 # Transaction distribution
system.membus.trans_dist::Writeback 103196 # Transaction distribution
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.membus.trans_dist::UpgradeReq 2215 # Transaction distribution
system.membus.trans_dist::UpgradeResp 1736 # Transaction distribution
system.membus.trans_dist::ReadExReq 133104 # Transaction distribution
system.membus.trans_dist::ReadExResp 133101 # Transaction distribution
system.membus.trans_dist::MessageReq 1644 # Transaction distribution
system.membus.trans_dist::MessageResp 1644 # Transaction distribution
system.membus.trans_dist::BadAddressError 10 # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3288 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total 3288 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471544 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775066 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 477864 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 20 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1724494 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94793 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 94793 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1822575 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6576 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::total 6576 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 242058 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550129 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18467392 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20259579 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.membus.pkt_size::total 23284587 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 949 # Total snoops (count)
system.membus.snoop_fanout::samples 338415 # Request fanout histogram
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.membus.snoop_fanout::1 338415 100.00% 100.00% # Request fanout histogram
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.membus.snoop_fanout::total 338415 # Request fanout histogram
system.membus.reqLayer0.occupancy 251687000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.membus.reqLayer1.occupancy 583226500 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.membus.reqLayer2.occupancy 3288000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.membus.reqLayer3.occupancy 1575195000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.membus.reqLayer4.occupancy 13500 # Layer occupancy (ticks)
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.membus.respLayer0.occupancy 1644000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.membus.respLayer2.occupancy 3157657266 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.membus.respLayer4.occupancy 54931743 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.iocache.tags.replacements 47575 # number of replacements
system.iocache.tags.tagsinuse 0.091458 # Cycle average of tags in use
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.iocache.tags.sampled_refs 47591 # Sample count of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.iocache.tags.warmup_cycle 4992976867000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.091458 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005716 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.005716 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.iocache.tags.tag_accesses 428670 # Number of tag accesses
system.iocache.tags.data_accesses 428670 # Number of data accesses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits
system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses
system.iocache.ReadReq_misses::total 910 # number of ReadReq misses
system.iocache.demand_misses::pc.south_bridge.ide 910 # number of demand (read+write) misses
system.iocache.demand_misses::total 910 # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide 910 # number of overall misses
system.iocache.overall_misses::total 910 # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 152161446 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 152161446 # number of ReadReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide 152161446 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 152161446 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide 152161446 # number of overall miss cycles
system.iocache.overall_miss_latency::total 152161446 # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.iocache.demand_accesses::pc.south_bridge.ide 910 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 910 # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide 910 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 910 # number of overall (read+write) accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167210.380220 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 167210.380220 # average ReadReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167210.380220 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 167210.380220 # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167210.380220 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 167210.380220 # average overall miss latency
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.iocache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.iocache.blocked::no_mshrs 26 # number of cycles access was blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.iocache.avg_blocked_cycles::no_mshrs 11.846154 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.iocache.fast_writes 46720 # number of fast writes performed
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.iocache.cache_copies 0 # number of cache copies performed
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 910 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide 910 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 910 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide 910 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 910 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 104814946 # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2846577667 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2846577667 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 104814946 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 104814946 # number of overall MSHR miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 115181.259341 # average ReadReq mshr miss latency
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide inf # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 115181.259341 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 115181.259341 # average overall mshr miss latency
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
Regression: Update statistics for x86 long regression tests This patch updates reference statistics for the regression tests. This update was necessitated by a recent change in behavior of some instructions in the x86 architecture.
2011-11-18 05:53:56 +01:00
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
Regression: Update statistics for x86 long regression tests This patch updates reference statistics for the regression tests. This update was necessitated by a recent change in behavior of some instructions in the x86 architecture.
2011-11-18 05:53:56 +01:00
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.iobus.trans_dist::ReadReq 225681 # Transaction distribution
system.iobus.trans_dist::ReadResp 225681 # Transaction distribution
system.iobus.trans_dist::WriteReq 57721 # Transaction distribution
system.iobus.trans_dist::WriteResp 57721 # Transaction distribution
system.iobus.trans_dist::MessageReq 1644 # Transaction distribution
system.iobus.trans_dist::MessageResp 1644 # Transaction distribution
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27696 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.iobus.pkt_count_system.bridge.master::total 471544 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95260 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95260 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3288 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3288 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 570092 # Packet count per connected master and slave (bytes)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13848 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.iobus.pkt_size_system.bridge.master::total 242058 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027824 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027824 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6576 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6576 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 3276458 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 3917656 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.iobus.reqLayer9.occupancy 213679000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.iobus.reqLayer13.occupancy 20719000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.iobus.reqLayer18.occupancy 422009356 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.iobus.respLayer0.occupancy 460543000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.iobus.respLayer1.occupancy 52362257 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.iobus.respLayer2.occupancy 1644000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.branchPred.lookups 86911006 # Number of BP lookups
system.cpu.branchPred.condPredicted 86911006 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 901724 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 80066722 # Number of BTB lookups
system.cpu.branchPred.BTBHits 78189070 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.branchPred.BTBHitPct 97.654891 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1556278 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 178526 # Number of incorrect RAS predictions.
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.numCycles 449563158 # number of cpu cycles simulated
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.fetch.icacheStallCycles 27553144 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 429142218 # Number of instructions fetch has processed
system.cpu.fetch.Branches 86911006 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 79745348 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 417985667 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1891240 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 143316 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles 50930 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 210883 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 127962 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles 502 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 9183903 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 446388 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes 4881 # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples 447018024 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.894555 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.051977 # Number of instructions fetched each cycle (Total)
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.fetch.rateDist::0 281457902 62.96% 62.96% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 2285728 0.51% 63.47% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 72178245 16.15% 79.62% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 1597297 0.36% 79.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 2150673 0.48% 80.46% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 2329203 0.52% 80.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 1531441 0.34% 81.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1871505 0.42% 81.74% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 81616030 18.26% 100.00% # Number of instructions fetched each cycle (Total)
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.fetch.rateDist::total 447018024 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.193323 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.954576 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 22975502 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 264891753 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 150781344 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 7423805 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 945620 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 838588132 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 945620 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 25820685 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 223318475 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 13301995 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 154670533 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 28960716 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 835102889 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 477440 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 12397064 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 181319 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 13705397 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 997542850 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 1813799496 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 1115056771 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 257 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 964533940 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 33008908 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 469072 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 473209 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 39003947 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 17327061 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 10187947 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1305152 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 1075480 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 829577981 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 1211612 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 824337261 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 238496 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 23343623 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 36066463 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 155823 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 447018024 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.844081 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 2.418172 # Number of insts issued each cycle
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.iq.issued_per_cycle::0 262761301 58.78% 58.78% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 13855312 3.10% 61.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 10080748 2.26% 64.14% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 6920312 1.55% 65.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 74355494 16.63% 82.32% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 4460813 1.00% 83.32% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 72820654 16.29% 99.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 1197568 0.27% 99.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 565822 0.13% 100.00% # Number of insts issued each cycle
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.iq.issued_per_cycle::total 447018024 # Number of insts issued each cycle
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.iq.fu_full::IntAlu 1976611 71.80% 71.80% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 212 0.01% 71.80% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 1052 0.04% 71.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 71.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 71.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 71.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.84% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 614146 22.31% 94.15% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 161054 5.85% 100.00% # attempts to use FU when none available
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.iq.FU_type_0::No_OpClass 292817 0.04% 0.04% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 795957786 96.56% 96.59% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 150640 0.02% 96.61% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 125262 0.02% 96.63% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.63% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.63% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.63% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.63% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.63% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.63% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 18413325 2.23% 98.86% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 9397431 1.14% 100.00% # Type of FU issued
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.iq.FU_type_0::total 824337261 # Type of FU issued
system.cpu.iq.rate 1.833641 # Inst issue rate
system.cpu.iq.fu_busy_cnt 2753075 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.003340 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 2098683900 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 854145561 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 819784123 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 216 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 406 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 61 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 826797417 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 102 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 1878905 # Number of loads that had data forwarded from stores
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 3325389 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 14284 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 14518 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 1760345 # Number of stores squashed
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.iew.lsq.thread0.rescheduledLoads 2224613 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 71287 # Number of times an access to memory failed due to the cache being blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.iew.iewSquashCycles 945620 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 205593402 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 9425350 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 830789593 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 184731 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 17327061 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 10187947 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 714336 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 416093 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 8107674 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 14518 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 515540 # Number of branches that were predicted taken incorrectly
stats: Small bump of trailing stats Somehow these seem to have been missed.
2014-10-16 11:49:31 +02:00
system.cpu.iew.predictedNotTakenIncorrect 536896 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1052436 # Number of branch mispredicts detected at execute
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.iew.iewExecutedInsts 822725796 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 18017825 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1477345 # Number of squashed instructions skipped in execute
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.iew.exec_refs 27187593 # number of memory reference insts executed
system.cpu.iew.exec_branches 83308581 # Number of branches executed
system.cpu.iew.exec_stores 9169768 # Number of stores executed
system.cpu.iew.exec_rate 1.830056 # Inst execution rate
system.cpu.iew.wb_sent 822221777 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 819784184 # cumulative count of insts written-back
system.cpu.iew.wb_producers 641108962 # num instructions producing a value
system.cpu.iew.wb_consumers 1050701242 # num instructions consuming a value
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.iew.wb_rate 1.823513 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.610172 # average fanout of values written-back
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.commit.commitSquashedInsts 24183935 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1055789 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 913678 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 443381671 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.819001 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.675688 # Number of insts commited each cycle
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.commit.committed_per_cycle::0 272578077 61.48% 61.48% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 11201647 2.53% 64.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 3542666 0.80% 64.80% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 74562549 16.82% 81.62% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 2432578 0.55% 82.17% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1609465 0.36% 82.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 914477 0.21% 82.74% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 71049223 16.02% 98.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 5490989 1.24% 100.00% # Number of insts commited each cycle
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.commit.committed_per_cycle::total 443381671 # Number of insts commited each cycle
system.cpu.commit.committedInsts 408006726 # Number of instructions committed
system.cpu.commit.committedOps 806511598 # Number of ops (including micro ops) committed
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.commit.refs 22429273 # Number of memory references committed
system.cpu.commit.loads 14001671 # Number of loads committed
system.cpu.commit.membars 475333 # Number of memory barriers committed
system.cpu.commit.branches 82207365 # Number of branches committed
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.commit.int_insts 735317995 # Number of committed integer instructions.
system.cpu.commit.function_calls 1155841 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 174216 0.02% 0.02% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 783641693 97.16% 97.19% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 144853 0.02% 97.20% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 121563 0.02% 97.22% # Class of committed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.commit.op_class_0::MemRead 14001671 1.74% 98.96% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 8427602 1.04% 100.00% # Class of committed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.commit.op_class_0::total 806511598 # Class of committed instruction
system.cpu.commit.bw_lim_events 5490989 # number cycles where commit BW limit reached
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.rob.rob_reads 1268507964 # The number of ROB reads
system.cpu.rob.rob_writes 1665044622 # The number of ROB writes
system.cpu.timesIdled 294262 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 2545134 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 9802241311 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 408006726 # Number of Instructions Simulated
system.cpu.committedOps 806511598 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 1.101852 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.101852 # CPI: Total CPI of All Threads
system.cpu.ipc 0.907563 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.907563 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 1092659743 # number of integer regfile reads
system.cpu.int_regfile_writes 656162059 # number of integer regfile writes
system.cpu.fp_regfile_reads 61 # number of floating regfile reads
system.cpu.cc_regfile_reads 416306470 # number of cc regfile reads
system.cpu.cc_regfile_writes 322125902 # number of cc regfile writes
system.cpu.misc_regfile_reads 265627452 # number of misc regfile reads
system.cpu.misc_regfile_writes 402647 # number of misc regfile writes
system.cpu.toL2Bus.trans_dist::ReadReq 3066870 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 3066328 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 13889 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 13889 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 1584468 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46724 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 2232 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 2232 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 287069 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 287069 # Transaction distribution
system.cpu.toL2Bus.trans_dist::BadAddressError 10 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1989808 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6126047 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 30798 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 165937 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 8312590 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63671040 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207694139 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1011904 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5790912 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 278167995 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 58568 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 4377947 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 3.010880 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.103740 # Request fanout histogram
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.toL2Bus.snoop_fanout::3 4330313 98.91% 98.91% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4 47634 1.09% 100.00% # Request fanout histogram
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.toL2Bus.snoop_fanout::total 4377947 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 4068281890 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.toL2Bus.snoopLayer0.occupancy 567000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.toL2Bus.respLayer0.occupancy 1496480643 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.toL2Bus.respLayer1.occupancy 3139987945 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.toL2Bus.respLayer2.occupancy 22488486 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.toL2Bus.respLayer3.occupancy 113254360 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.icache.tags.replacements 994393 # number of replacements
system.cpu.icache.tags.tagsinuse 510.035216 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 8125717 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 994905 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 8.167330 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 147627648000 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 510.035216 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.996163 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.996163 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 129 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 141 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.icache.tags.tag_accesses 10178850 # Number of tag accesses
system.cpu.icache.tags.data_accesses 10178850 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 8125717 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 8125717 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 8125717 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 8125717 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 8125717 # number of overall hits
system.cpu.icache.overall_hits::total 8125717 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1058185 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1058185 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1058185 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1058185 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1058185 # number of overall misses
system.cpu.icache.overall_misses::total 1058185 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 14693875503 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 14693875503 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 14693875503 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 14693875503 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 14693875503 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 14693875503 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 9183902 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 9183902 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 9183902 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 9183902 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 9183902 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 9183902 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115222 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.115222 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.115222 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.115222 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.115222 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.115222 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13885.923069 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13885.923069 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13885.923069 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13885.923069 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13885.923069 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13885.923069 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 7023 # number of cycles access was blocked
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.icache.blocked::no_mshrs 297 # number of cycles access was blocked
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 23.646465 # average number of cycles each access was blocked
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63237 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 63237 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 63237 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 63237 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 63237 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 63237 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 994948 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 994948 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 994948 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 994948 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 994948 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 994948 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12059629101 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 12059629101 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12059629101 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 12059629101 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12059629101 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 12059629101 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108336 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108336 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108336 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.108336 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108336 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.108336 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12120.863704 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12120.863704 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12120.863704 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12120.863704 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12120.863704 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12120.863704 # average overall mshr miss latency
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.itb_walker_cache.tags.replacements 14092 # number of replacements
system.cpu.itb_walker_cache.tags.tagsinuse 6.014059 # Cycle average of tags in use
system.cpu.itb_walker_cache.tags.total_refs 26262 # Total number of references to valid blocks.
system.cpu.itb_walker_cache.tags.sampled_refs 14107 # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.tags.avg_refs 1.861629 # Average number of references to valid blocks.
system.cpu.itb_walker_cache.tags.warmup_cycle 5101924515000 # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.014059 # Average occupied blocks per requestor
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.375879 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_percent::total 0.375879 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id
system.cpu.itb_walker_cache.tags.tag_accesses 97491 # Number of tag accesses
system.cpu.itb_walker_cache.tags.data_accesses 97491 # Number of data accesses
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 26263 # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total 26263 # number of ReadReq hits
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 26265 # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total 26265 # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 26265 # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total 26265 # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 14987 # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total 14987 # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 14987 # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total 14987 # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 14987 # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total 14987 # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 174073497 # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total 174073497 # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 174073497 # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total 174073497 # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 174073497 # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total 174073497 # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 41250 # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total 41250 # number of ReadReq accesses(hits+misses)
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 41252 # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total 41252 # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 41252 # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total 41252 # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.363321 # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.363321 # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.363304 # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total 0.363304 # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.363304 # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total 0.363304 # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11614.966104 # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11614.966104 # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11614.966104 # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11614.966104 # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11614.966104 # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11614.966104 # average overall miss latency
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.itb_walker_cache.writebacks::writebacks 3303 # number of writebacks
system.cpu.itb_walker_cache.writebacks::total 3303 # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 14987 # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 14987 # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 14987 # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total 14987 # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 14987 # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total 14987 # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 144083525 # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 144083525 # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 144083525 # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 144083525 # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 144083525 # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 144083525 # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.363321 # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.363321 # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.363304 # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.363304 # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.363304 # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.363304 # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9613.900380 # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9613.900380 # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9613.900380 # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9613.900380 # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9613.900380 # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9613.900380 # average overall mshr miss latency
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.dtb_walker_cache.tags.replacements 74377 # number of replacements
system.cpu.dtb_walker_cache.tags.tagsinuse 15.812457 # Cycle average of tags in use
system.cpu.dtb_walker_cache.tags.total_refs 116780 # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.sampled_refs 74392 # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.tags.avg_refs 1.569792 # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.warmup_cycle 194043074000 # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.812457 # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.988279 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_percent::total 0.988279 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id
system.cpu.dtb_walker_cache.tags.tag_accesses 459926 # Number of tag accesses
system.cpu.dtb_walker_cache.tags.data_accesses 459926 # Number of data accesses
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 116782 # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total 116782 # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 116782 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total 116782 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 116782 # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total 116782 # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 75454 # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total 75454 # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 75454 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total 75454 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 75454 # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total 75454 # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 927232955 # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 927232955 # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 927232955 # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total 927232955 # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 927232955 # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total 927232955 # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 192236 # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total 192236 # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 192236 # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total 192236 # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 192236 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total 192236 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.392507 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.392507 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.392507 # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.392507 # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.392507 # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.392507 # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12288.718358 # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12288.718358 # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12288.718358 # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12288.718358 # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12288.718358 # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12288.718358 # average overall miss latency
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.dtb_walker_cache.writebacks::writebacks 21876 # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total 21876 # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 75454 # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 75454 # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 75454 # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total 75454 # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 75454 # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total 75454 # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 776178235 # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 776178235 # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 776178235 # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 776178235 # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 776178235 # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 776178235 # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.392507 # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.392507 # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.392507 # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.392507 # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.392507 # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.392507 # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10286.773862 # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10286.773862 # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10286.773862 # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10286.773862 # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10286.773862 # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10286.773862 # average overall mshr miss latency
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.dcache.tags.replacements 1657683 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.996297 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 19131015 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1658195 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 11.537253 # Average number of references to valid blocks.
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.tags.warmup_cycle 37454250 # Cycle when the warmup percentage was hit.
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.dcache.tags.occ_blocks::cpu.data 511.996297 # Average occupied blocks per requestor
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.dcache.tags.occ_percent::cpu.data 0.999993 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999993 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.dcache.tags.tag_accesses 88314142 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 88314142 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 10979297 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 10979297 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 8084679 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 8084679 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 64358 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 64358 # number of SoftPFReq hits
system.cpu.dcache.demand_hits::cpu.data 19063976 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 19063976 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 19128334 # number of overall hits
system.cpu.dcache.overall_hits::total 19128334 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1796007 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1796007 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 333248 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 333248 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 406393 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 406393 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 2129255 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2129255 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2535648 # number of overall misses
system.cpu.dcache.overall_misses::total 2535648 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 26565336178 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 26565336178 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 12842853467 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 12842853467 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 39408189645 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 39408189645 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 39408189645 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 39408189645 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 12775304 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 12775304 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 8417927 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 8417927 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 470751 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 470751 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 21193231 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 21193231 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 21663982 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 21663982 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.140584 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.140584 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039588 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.039588 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.863287 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.863287 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.100469 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.100469 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.117044 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.117044 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14791.332204 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14791.332204 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38538.426238 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 38538.426238 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 18507.970931 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 18507.970931 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15541.664160 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 15541.664160 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 378856 # number of cycles access was blocked
X86 Regressions: Update stats due to introduction of TSO
2012-01-29 02:09:17 +01:00
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.dcache.blocked::no_mshrs 39922 # number of cycles access was blocked
X86 Regressions: Update stats due to introduction of TSO
2012-01-29 02:09:17 +01:00
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.489905 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.dcache.writebacks::writebacks 1559289 # number of writebacks
system.cpu.dcache.writebacks::total 1559289 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 827651 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 827651 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44088 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 44088 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 871739 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 871739 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 871739 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 871739 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 968356 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 968356 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289160 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 289160 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402927 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 402927 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1257516 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1257516 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1660443 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1660443 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12252685521 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 12252685521 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11181268784 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 11181268784 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5616168251 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5616168251 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23433954305 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 23433954305 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29050122556 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 29050122556 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97390324000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97390324000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2564320000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2564320000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99954644000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 99954644000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075799 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075799 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034350 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034350 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.855924 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.855924 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059336 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.059336 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076645 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.076645 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12653.079571 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12653.079571 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38668.103417 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38668.103417 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13938.426194 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13938.426194 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18635.114229 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18635.114229 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17495.404874 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17495.404874 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.l2cache.tags.replacements 113085 # number of replacements
system.cpu.l2cache.tags.tagsinuse 64818.383323 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 3831425 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 176970 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 21.650138 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.l2cache.tags.occ_blocks::writebacks 50432.340696 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 22.760500 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.143343 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3264.453296 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 11098.685488 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.769536 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000347 # Average percentage of cache occupancy
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049812 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.169353 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.989050 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 63885 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 634 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3305 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5793 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54091 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.974808 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 35031209 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 35031209 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 68532 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12501 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst 978548 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 1334624 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2394205 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 1584468 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 1584468 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 309 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 309 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 153669 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 153669 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 68532 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 12501 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 978548 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 1488293 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2547874 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 68532 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 12501 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 978548 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 1488293 # number of overall hits
system.cpu.l2cache.overall_hits::total 2547874 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 75 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst 16312 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 35875 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 52269 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1444 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 1444 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 133393 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 133393 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 75 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst 16312 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 169268 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 185662 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 75 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst 16312 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 169268 # number of overall misses
system.cpu.l2cache.overall_misses::total 185662 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 6508500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 560500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1253827000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2884413497 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 4145309497 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16150808 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 16150808 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9313802457 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 9313802457 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 6508500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 560500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 1253827000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 12198215954 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 13459111954 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 6508500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 560500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 1253827000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 12198215954 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 13459111954 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 68607 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12508 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst 994860 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1370499 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 2446474 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 1584468 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 1584468 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1753 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 1753 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 287062 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 287062 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 68607 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 12508 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 994860 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1657561 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2733536 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 68607 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 12508 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 994860 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1657561 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2733536 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001093 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000560 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016396 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026177 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.021365 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.823731 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.823731 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.464684 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.464684 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001093 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000560 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016396 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.102119 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.067920 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001093 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000560 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016396 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.102119 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.067920 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 86780 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 80071.428571 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76865.313879 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80401.769951 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 79307.227936 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11184.770083 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11184.770083 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69822.272960 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69822.272960 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 86780 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 80071.428571 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76865.313879 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72064.512808 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 72492.550732 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 86780 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 80071.428571 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76865.313879 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72064.512808 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 72492.550732 # average overall miss latency
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.l2cache.writebacks::writebacks 103196 # number of writebacks
system.cpu.l2cache.writebacks::total 103196 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.l2cache.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.l2cache.overall_mshr_hits::total 3 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 75 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16310 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35874 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 52266 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1444 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 1444 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133393 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 133393 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 75 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 16310 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 169267 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 185659 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 75 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 16310 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 169267 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 185659 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5579000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 473000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1049198000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2439336749 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3494586749 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14472940 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14472940 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7638617543 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7638617543 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5579000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 473000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1049198000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10077954292 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 11133204292 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5579000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 473000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1049198000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10077954292 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 11133204292 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89275584000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89275584000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2397149000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2397149000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91672733000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91672733000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001093 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000560 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016394 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026176 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021364 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823731 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823731 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.464684 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.464684 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001093 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000560 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016394 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102118 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.067919 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001093 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000560 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016394 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102118 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.067919 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 74386.666667 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 67571.428571 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64328.510116 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67997.344846 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 66861.568687 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10022.811634 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10022.811634 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57264.005930 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57264.005930 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 74386.666667 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 67571.428571 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64328.510116 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59538.801373 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59965.874490 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 74386.666667 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 67571.428571 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64328.510116 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59538.801373 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59965.874490 # average overall mshr miss latency
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink