2012-03-09 15:59:28 +01:00
---------- Begin Simulation Statistics ----------
2015-03-02 11:04:20 +01:00
sim_seconds 0.000017 # Number of seconds simulated
2016-04-08 18:01:45 +02:00
sim_ticks 17232500 # Number of ticks simulated
final_tick 17232500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2012-03-09 15:59:28 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
2016-06-06 18:16:44 +02:00
host_inst_rate 78702 # Simulator instruction rate (inst/s)
host_op_rate 92158 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 295258113 # Simulator tick rate (ticks/s)
host_mem_usage 310332 # Number of bytes of host memory used
2016-06-02 15:14:36 +02:00
host_seconds 0.06 # Real time elapsed on the host
2015-04-30 21:17:43 +02:00
sim_insts 4592 # Number of instructions simulated
sim_ops 5378 # Number of ops (including micro ops) simulated
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2016-06-06 18:16:44 +02:00
system.physmem.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
2016-04-08 18:01:45 +02:00
system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory
2015-07-03 16:15:03 +02:00
system.physmem.bytes_read::cpu.data 7744 # Number of bytes read from this memory
2016-04-08 18:01:45 +02:00
system.physmem.bytes_read::total 25408 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory
2015-07-03 16:15:03 +02:00
system.physmem.num_reads::cpu.data 121 # Number of read requests responded to by this memory
2016-04-08 18:01:45 +02:00
system.physmem.num_reads::total 397 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1025039896 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 449383432 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1474423328 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1025039896 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1025039896 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1025039896 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 449383432 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1474423328 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 397 # Number of read requests accepted
2013-11-01 16:56:34 +01:00
system.physmem.writeReqs 0 # Number of write requests accepted
2016-04-08 18:01:45 +02:00
system.physmem.readBursts 397 # Number of DRAM read bursts, including those serviced by the write queue
2013-11-01 16:56:34 +01:00
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
2016-04-08 18:01:45 +02:00
system.physmem.bytesReadDRAM 25408 # Total number of bytes read from DRAM
2013-11-01 16:56:34 +01:00
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
2016-04-08 18:01:45 +02:00
system.physmem.bytesReadSys 25408 # Total read bytes from the system interface side
2013-11-01 16:56:34 +01:00
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
2016-04-08 18:01:45 +02:00
system.physmem.perBankRdBursts::0 89 # Per bank write bursts
2015-04-30 21:17:43 +02:00
system.physmem.perBankRdBursts::1 45 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.perBankRdBursts::2 20 # Per bank write bursts
2014-09-03 13:42:59 +02:00
system.physmem.perBankRdBursts::3 43 # Per bank write bursts
system.physmem.perBankRdBursts::4 18 # Per bank write bursts
system.physmem.perBankRdBursts::5 32 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.perBankRdBursts::6 35 # Per bank write bursts
system.physmem.perBankRdBursts::7 10 # Per bank write bursts
system.physmem.perBankRdBursts::8 4 # Per bank write bursts
2016-04-08 18:01:45 +02:00
system.physmem.perBankRdBursts::9 9 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.perBankRdBursts::10 28 # Per bank write bursts
system.physmem.perBankRdBursts::11 42 # Per bank write bursts
2016-04-08 18:01:45 +02:00
system.physmem.perBankRdBursts::12 10 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.perBankRdBursts::13 6 # Per bank write bursts
system.physmem.perBankRdBursts::14 0 # Per bank write bursts
system.physmem.perBankRdBursts::15 6 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
2016-04-08 18:01:45 +02:00
system.physmem.totGap 17147000 # Total gap between requests
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2016-04-08 18:01:45 +02:00
system.physmem.readPktSize::6 397 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
2016-04-08 18:01:45 +02:00
system.physmem.rdQLenPdf::0 207 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
2014-09-03 13:42:59 +02:00
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
2015-09-15 15:14:09 +02:00
system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation
2016-04-08 18:01:45 +02:00
system.physmem.bytesPerActivate::mean 391.111111 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 256.618090 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 341.397843 # Bytes accessed per row activation
2015-09-15 15:14:09 +02:00
system.physmem.bytesPerActivate::0-127 13 20.63% 20.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 18 28.57% 49.21% # Bytes accessed per row activation
2016-04-08 18:01:45 +02:00
system.physmem.bytesPerActivate::256-383 7 11.11% 60.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 6 9.52% 69.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 4 6.35% 76.19% # Bytes accessed per row activation
2015-09-15 15:14:09 +02:00
system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 2 3.17% 82.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 2 3.17% 85.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 9 14.29% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation
2016-04-08 18:01:45 +02:00
system.physmem.totQLat 3287250 # Total ticks spent queuing
system.physmem.totMemAccLat 10731000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 1985000 # Total ticks spent in databus transfers
system.physmem.avgQLat 8280.23 # Average queueing delay per DRAM burst
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2016-04-08 18:01:45 +02:00
system.physmem.avgMemAccLat 27030.23 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1474.42 # Average DRAM read bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
2016-04-08 18:01:45 +02:00
system.physmem.avgRdBWSys 1474.42 # Average system read bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2016-04-08 18:01:45 +02:00
system.physmem.busUtil 11.52 # Data bus utilization in percentage
system.physmem.busUtilRead 11.52 # Data bus utilization in percentage for reads
2013-11-01 16:56:34 +01:00
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
2015-07-03 16:15:03 +02:00
system.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing
2013-11-01 16:56:34 +01:00
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
2016-04-08 18:01:45 +02:00
system.physmem.readRowHits 331 # Number of row buffer hits during reads
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
2016-04-08 18:01:45 +02:00
system.physmem.readRowHitRate 83.38 # Row buffer hit rate for reads
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
2016-04-08 18:01:45 +02:00
system.physmem.avgGap 43191.44 # Average gap between requests
system.physmem.pageHitRate 83.38 # Row buffer hit rate, read and write combined
2015-09-15 15:14:09 +02:00
system.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ)
2016-04-08 18:01:45 +02:00
system.physmem_0.readEnergy 2090400 # Energy for read commands per rank (pJ)
2014-12-23 15:31:20 +01:00
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
2016-04-08 18:01:45 +02:00
system.physmem_0.actBackEnergy 10792665 # Energy for active background per rank (pJ)
2015-07-03 16:15:03 +02:00
system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ)
2016-04-08 18:01:45 +02:00
system.physmem_0.totalEnergy 14411520 # Total energy per rank (pJ)
system.physmem_0.averagePower 910.249171 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 69250 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::REF 520000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
2016-04-08 18:01:45 +02:00
system.physmem_0.memoryStateTime::ACT 16107250 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
2015-07-03 16:15:03 +02:00
system.physmem_1.actEnergy 151200 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 82500 # Energy for precharge commands per rank (pJ)
2016-04-08 18:01:45 +02:00
system.physmem_1.readEnergy 764400 # Energy for read commands per rank (pJ)
2014-12-23 15:31:20 +01:00
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
2015-09-15 15:14:09 +02:00
system.physmem_1.actBackEnergy 10407915 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 369750 # Energy for precharge background per rank (pJ)
2016-04-08 18:01:45 +02:00
system.physmem_1.totalEnergy 12792885 # Total energy per rank (pJ)
system.physmem_1.averagePower 808.014211 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 741250 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::REF 520000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
2015-09-15 15:14:09 +02:00
system.physmem_1.memoryStateTime::ACT 14752750 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
2016-06-06 18:16:44 +02:00
system.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
2016-04-08 18:01:45 +02:00
system.cpu.branchPred.lookups 2837 # Number of BP lookups
system.cpu.branchPred.condPredicted 1744 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 464 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 2401 # Number of BTB lookups
system.cpu.branchPred.BTBHits 865 # Number of BTB hits
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2016-04-08 18:01:45 +02:00
system.cpu.branchPred.BTBHitPct 36.026656 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 314 # Number of times the RAS was used to get a target.
2015-04-30 21:17:43 +02:00
system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions.
2016-04-08 18:01:45 +02:00
system.cpu.branchPred.indirectLookups 265 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 14 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 251 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 63 # Number of mispredicted indirect branches.
2014-12-23 15:31:20 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2016-06-06 18:16:44 +02:00
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-06-06 18:16:44 +02:00
system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2012-03-09 15:59:28 +01:00
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
system.cpu.checker.dtb.read_hits 0 # DTB read hits
system.cpu.checker.dtb.read_misses 0 # DTB read misses
system.cpu.checker.dtb.write_hits 0 # DTB write hits
system.cpu.checker.dtb.write_misses 0 # DTB write misses
system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.dtb.read_accesses 0 # DTB read accesses
system.cpu.checker.dtb.write_accesses 0 # DTB write accesses
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.checker.dtb.hits 0 # DTB hits
system.cpu.checker.dtb.misses 0 # DTB misses
system.cpu.checker.dtb.accesses 0 # DTB accesses
2016-06-06 18:16:44 +02:00
system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-06-06 18:16:44 +02:00
system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu.checker.itb.walker.walks 0 # Table walker walks requested
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2012-03-09 15:59:28 +01:00
system.cpu.checker.itb.inst_hits 0 # ITB inst hits
system.cpu.checker.itb.inst_misses 0 # ITB inst misses
system.cpu.checker.itb.read_hits 0 # DTB read hits
system.cpu.checker.itb.read_misses 0 # DTB read misses
system.cpu.checker.itb.write_hits 0 # DTB write hits
system.cpu.checker.itb.write_misses 0 # DTB write misses
system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses
system.cpu.checker.itb.hits 0 # DTB hits
system.cpu.checker.itb.misses 0 # DTB misses
system.cpu.checker.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 13 # Number of system calls
2016-06-06 18:16:44 +02:00
system.cpu.checker.pwrStateResidencyTicks::ON 17232500 # Cumulative time (in ticks) in various power states
2015-04-30 21:17:43 +02:00
system.cpu.checker.numCycles 5391 # number of cpu cycles simulated
2012-03-09 15:59:28 +01:00
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
2016-06-06 18:16:44 +02:00
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-06-06 18:16:44 +02:00
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2012-03-09 15:59:28 +01:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
2016-06-06 18:16:44 +02:00
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-06-06 18:16:44 +02:00
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2012-03-09 15:59:28 +01:00
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
2016-06-06 18:16:44 +02:00
system.cpu.pwrStateResidencyTicks::ON 17232500 # Cumulative time (in ticks) in various power states
2016-04-08 18:01:45 +02:00
system.cpu.numCycles 34466 # number of cpu cycles simulated
2012-03-09 15:59:28 +01:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
2016-04-08 18:01:45 +02:00
system.cpu.fetch.icacheStallCycles 7588 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 12295 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2837 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 1193 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 4873 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 977 # Number of cycles fetch has spent squashing
2015-04-30 21:17:43 +02:00
system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
2016-04-08 18:01:45 +02:00
system.cpu.fetch.PendingTrapStallCycles 246 # Number of stall cycles due to pending traps
2015-04-30 21:17:43 +02:00
system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR
2016-04-08 18:01:45 +02:00
system.cpu.fetch.CacheLines 1961 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 13213 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.120412 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.482171 # Number of instructions fetched each cycle (Total)
2012-03-09 15:59:28 +01:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2016-04-08 18:01:45 +02:00
system.cpu.fetch.rateDist::0 10520 79.62% 79.62% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 264 2.00% 81.62% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 185 1.40% 83.02% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 203 1.54% 84.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 282 2.13% 86.69% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 396 3.00% 89.68% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 139 1.05% 90.74% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 173 1.31% 92.05% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 1051 7.95% 100.00% # Number of instructions fetched each cycle (Total)
2012-03-09 15:59:28 +01:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
2016-04-08 18:01:45 +02:00
system.cpu.fetch.rateDist::total 13213 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.082313 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.356728 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 6291 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 4311 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 2142 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 334 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 431 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 12135 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 489 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 334 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 6519 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 770 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 2303 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 2037 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 1250 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 11429 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 166 # Number of times rename has blocked due to IQ full
2015-07-03 16:15:03 +02:00
system.cpu.rename.LQFullEvents 130 # Number of times rename has blocked due to LQ full
2016-04-08 18:01:45 +02:00
system.cpu.rename.SQFullEvents 1074 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 11638 # Number of destination operands rename has renamed
2016-06-02 15:14:36 +02:00
system.cpu.rename.RenameLookups 52321 # Number of register rename lookups that rename has made
2016-04-08 18:01:45 +02:00
system.cpu.rename.int_rename_lookups 12347 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 199 # Number of floating rename lookups
2014-09-03 13:42:59 +02:00
system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed
2016-04-08 18:01:45 +02:00
system.cpu.rename.UndoneMaps 6144 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 40 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 34 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 441 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 2200 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1540 # Number of stores inserted to the mem dependence unit.
2015-09-15 15:14:09 +02:00
system.cpu.memDep0.conflictingLoads 32 # Number of conflicting loads.
2016-04-08 18:01:45 +02:00
system.cpu.memDep0.conflictingStores 22 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 10167 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 43 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 8103 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 38 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 4832 # Number of squashed instructions iterated over during squash; mainly for profiling
2016-06-02 15:14:36 +02:00
system.cpu.iq.iqSquashedOperandsExamined 12329 # Number of squashed operands that are examined and possibly removed from graph
2016-04-08 18:01:45 +02:00
system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 13213 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.613260 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.341984 # Number of insts issued each cycle
2012-03-09 15:59:28 +01:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2016-04-08 18:01:45 +02:00
system.cpu.iq.issued_per_cycle::0 9987 75.58% 75.58% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 1172 8.87% 84.45% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 771 5.84% 90.29% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 475 3.59% 93.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 345 2.61% 96.50% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 273 2.07% 98.56% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 121 0.92% 99.48% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 59 0.45% 99.92% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 10 0.08% 100.00% # Number of insts issued each cycle
2012-03-09 15:59:28 +01:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
2016-04-08 18:01:45 +02:00
system.cpu.iq.issued_per_cycle::total 13213 # Number of insts issued each cycle
2012-03-09 15:59:28 +01:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2016-04-08 18:01:45 +02:00
system.cpu.iq.fu_full::IntAlu 9 6.21% 6.21% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 6.21% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 6.21% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.21% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.21% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.21% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 6.21% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.21% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 6.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 6.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.21% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.21% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 65 44.83% 51.03% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 71 48.97% 100.00% # attempts to use FU when none available
2012-03-09 15:59:28 +01:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
2016-04-08 18:01:45 +02:00
system.cpu.iq.FU_type_0::IntAlu 5027 62.04% 62.04% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 7 0.09% 62.13% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.13% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.13% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.13% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.13% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.13% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.13% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.16% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 1882 23.23% 85.39% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 1184 14.61% 100.00% # Type of FU issued
2012-03-09 15:59:28 +01:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2016-04-08 18:01:45 +02:00
system.cpu.iq.FU_type_0::total 8103 # Type of FU issued
system.cpu.iq.rate 0.235101 # Inst issue rate
system.cpu.iq.fu_busy_cnt 145 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.017895 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 29511 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 14929 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 7407 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 91 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 132 # Number of floating instruction queue writes
2015-03-02 11:04:20 +01:00
system.cpu.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses
2016-04-08 18:01:45 +02:00
system.cpu.iq.int_alu_accesses 8205 # Number of integer alu accesses
2014-09-03 13:42:59 +02:00
system.cpu.iq.fp_alu_accesses 43 # Number of floating point alu accesses
2015-09-15 15:14:09 +02:00
system.cpu.iew.lsq.thread0.forwLoads 23 # Number of loads that had data forwarded from stores
2012-03-09 15:59:28 +01:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2016-04-08 18:01:45 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 1173 # Number of loads squashed
2012-10-25 19:14:42 +02:00
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
2015-03-02 11:04:20 +01:00
system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations
2016-04-08 18:01:45 +02:00
system.cpu.iew.lsq.thread0.squashedStores 602 # Number of stores squashed
2012-03-09 15:59:28 +01:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2016-04-08 18:01:45 +02:00
system.cpu.iew.lsq.thread0.rescheduledLoads 31 # Number of loads that were rescheduled
2015-04-30 21:17:43 +02:00
system.cpu.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked
2012-03-09 15:59:28 +01:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2016-04-08 18:01:45 +02:00
system.cpu.iew.iewSquashCycles 334 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 683 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 10219 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 125 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 2200 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 1540 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 31 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall
2015-07-03 16:15:03 +02:00
system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall
2015-03-02 11:04:20 +01:00
system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations
2016-04-08 18:01:45 +02:00
system.cpu.iew.predictedTakenIncorrect 94 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 263 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 357 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 7814 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 1772 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 289 # Number of squashed instructions skipped in execute
2012-03-09 15:59:28 +01:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
2015-04-30 21:17:43 +02:00
system.cpu.iew.exec_nop 9 # number of nop insts executed
2016-04-08 18:01:45 +02:00
system.cpu.iew.exec_refs 2923 # number of memory reference insts executed
system.cpu.iew.exec_branches 1492 # Number of branches executed
system.cpu.iew.exec_stores 1151 # Number of stores executed
system.cpu.iew.exec_rate 0.226716 # Inst execution rate
system.cpu.iew.wb_sent 7536 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 7439 # cumulative count of insts written-back
system.cpu.iew.wb_producers 3504 # num instructions producing a value
system.cpu.iew.wb_consumers 6831 # num instructions consuming a value
system.cpu.iew.wb_rate 0.215836 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.512956 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 4840 # The number of squashed insts skipped by commit
2013-01-08 14:54:16 +01:00
system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards
2016-04-08 18:01:45 +02:00
system.cpu.commit.branchMispredicts 310 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 12359 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.435148 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.280013 # Number of insts commited each cycle
2012-03-09 15:59:28 +01:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2016-04-08 18:01:45 +02:00
system.cpu.commit.committed_per_cycle::0 10307 83.40% 83.40% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 885 7.16% 90.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 420 3.40% 93.96% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 217 1.76% 95.71% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 108 0.87% 96.59% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 219 1.77% 98.36% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 55 0.45% 98.80% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 39 0.32% 99.12% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 109 0.88% 100.00% # Number of insts commited each cycle
2012-03-09 15:59:28 +01:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2016-04-08 18:01:45 +02:00
system.cpu.commit.committed_per_cycle::total 12359 # Number of insts commited each cycle
2015-04-30 21:17:43 +02:00
system.cpu.commit.committedInsts 4592 # Number of instructions committed
system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed
2012-03-09 15:59:28 +01:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
2014-09-03 13:42:59 +02:00
system.cpu.commit.refs 1965 # Number of memory references committed
system.cpu.commit.loads 1027 # Number of loads committed
2012-03-09 15:59:28 +01:00
system.cpu.commit.membars 12 # Number of memory barriers committed
2015-04-30 21:17:43 +02:00
system.cpu.commit.branches 1008 # Number of branches committed
2012-03-09 15:59:28 +01:00
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
2014-09-03 13:42:59 +02:00
system.cpu.commit.int_insts 4624 # Number of committed integer instructions.
2012-03-09 15:59:28 +01:00
system.cpu.commit.function_calls 82 # Number of function calls committed.
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2015-04-30 21:17:43 +02:00
system.cpu.commit.op_class_0::IntAlu 3406 63.33% 63.33% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 4 0.07% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.41% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.41% # Class of committed instruction
2014-09-03 13:42:59 +02:00
system.cpu.commit.op_class_0::SimdFloatMisc 3 0.06% 63.46% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2015-04-30 21:17:43 +02:00
system.cpu.commit.op_class_0::total 5378 # Class of committed instruction
2016-04-08 18:01:45 +02:00
system.cpu.commit.bw_lim_events 109 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 22311 # The number of ROB reads
system.cpu.rob.rob_writes 21303 # The number of ROB writes
system.cpu.timesIdled 191 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 21253 # Total number of cycles that the CPU has spent unscheduled due to idling
2015-04-30 21:17:43 +02:00
system.cpu.committedInsts 4592 # Number of Instructions Simulated
system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated
2016-04-08 18:01:45 +02:00
system.cpu.cpi 7.505662 # CPI: Cycles Per Instruction
system.cpu.cpi_total 7.505662 # CPI: Total CPI of All Threads
system.cpu.ipc 0.133233 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.133233 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 7659 # number of integer regfile reads
system.cpu.int_regfile_writes 4270 # number of integer regfile writes
2015-03-02 11:04:20 +01:00
system.cpu.fp_regfile_reads 32 # number of floating regfile reads
2016-04-08 18:01:45 +02:00
system.cpu.cc_regfile_reads 27801 # number of cc regfile reads
system.cpu.cc_regfile_writes 3276 # number of cc regfile writes
2016-06-02 15:14:36 +02:00
system.cpu.misc_regfile_reads 2978 # number of misc regfile reads
2013-01-08 14:54:16 +01:00
system.cpu.misc_regfile_writes 24 # number of misc regfile writes
2016-06-06 18:16:44 +02:00
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.replacements 0 # number of replacements
2016-04-08 18:01:45 +02:00
system.cpu.dcache.tags.tagsinuse 88.359063 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 2095 # Total number of references to valid blocks.
2015-09-15 15:14:09 +02:00
system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks.
2016-04-08 18:01:45 +02:00
system.cpu.dcache.tags.avg_refs 14.251701 # Average number of references to valid blocks.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-04-08 18:01:45 +02:00
system.cpu.dcache.tags.occ_blocks::cpu.data 88.359063 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.021572 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.021572 # Average percentage of cache occupancy
2015-09-15 15:14:09 +02:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id
2016-04-08 18:01:45 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id
2015-09-15 15:14:09 +02:00
system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id
2016-04-08 18:01:45 +02:00
system.cpu.dcache.tags.tag_accesses 5339 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 5339 # Number of data accesses
2016-06-06 18:16:44 +02:00
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
2016-04-08 18:01:45 +02:00
system.cpu.dcache.ReadReq_hits::cpu.data 1477 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1477 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 597 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 597 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits
2014-12-23 15:31:20 +01:00
system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
2016-04-08 18:01:45 +02:00
system.cpu.dcache.demand_hits::cpu.data 2074 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 2074 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 2074 # number of overall hits
system.cpu.dcache.overall_hits::total 2074 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 183 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 183 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 316 # number of WriteReq misses
2014-12-23 15:31:20 +01:00
system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
2016-04-08 18:01:45 +02:00
system.cpu.dcache.demand_misses::cpu.data 499 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 499 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 499 # number of overall misses
system.cpu.dcache.overall_misses::total 499 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 10736000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 10736000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 22555500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 22555500 # number of WriteReq miss cycles
2015-07-03 16:15:03 +02:00
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 142000 # number of LoadLockedReq miss cycles
2016-04-08 18:01:45 +02:00
system.cpu.dcache.demand_miss_latency::cpu.data 33291500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 33291500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 33291500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 33291500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1660 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1660 # number of ReadReq accesses(hits+misses)
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
2016-04-08 18:01:45 +02:00
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses)
2014-12-23 15:31:20 +01:00
system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
2016-04-08 18:01:45 +02:00
system.cpu.dcache.demand_accesses::cpu.data 2573 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2573 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2573 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2573 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.110241 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.110241 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.346112 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.346112 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.193937 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.193937 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.193937 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.193937 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58666.666667 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 58666.666667 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71378.164557 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 71378.164557 # average WriteReq miss latency
2015-07-03 16:15:03 +02:00
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71000 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71000 # average LoadLockedReq miss latency
2016-04-08 18:01:45 +02:00
system.cpu.dcache.demand_avg_miss_latency::cpu.data 66716.432866 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 66716.432866 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 66716.432866 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 66716.432866 # average overall miss latency
2015-09-15 15:14:09 +02:00
system.cpu.dcache.blocked_cycles::no_mshrs 145 # number of cycles access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-09-15 15:14:09 +02:00
system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
2015-09-15 15:14:09 +02:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.333333 # average number of cycles each access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-04-08 18:01:45 +02:00
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 274 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 274 # number of WriteReq MSHR hits
2014-12-23 15:31:20 +01:00
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
2016-04-08 18:01:45 +02:00
system.cpu.dcache.demand_mshr_hits::cpu.data 352 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 352 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 352 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 352 # number of overall MSHR hits
2014-12-23 15:31:20 +01:00
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
2016-04-08 18:01:45 +02:00
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7020000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7020000 # number of ReadReq MSHR miss cycles
2015-09-25 13:27:03 +02:00
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3398000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3398000 # number of WriteReq MSHR miss cycles
2016-04-08 18:01:45 +02:00
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10418000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 10418000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10418000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 10418000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.063253 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.063253 # mshr miss rate for ReadReq accesses
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses
2016-04-08 18:01:45 +02:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057132 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.057132 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.057132 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.057132 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66857.142857 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66857.142857 # average ReadReq mshr miss latency
2015-09-25 13:27:03 +02:00
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80904.761905 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80904.761905 # average WriteReq mshr miss latency
2016-04-08 18:01:45 +02:00
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70870.748299 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 70870.748299 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70870.748299 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 70870.748299 # average overall mshr miss latency
2016-06-06 18:16:44 +02:00
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
2016-04-08 18:01:45 +02:00
system.cpu.icache.tags.replacements 2 # number of replacements
system.cpu.icache.tags.tagsinuse 150.405898 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 1577 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 294 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 5.363946 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-04-08 18:01:45 +02:00
system.cpu.icache.tags.occ_blocks::cpu.inst 150.405898 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.073440 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.073440 # Average percentage of cache occupancy
2015-04-30 21:17:43 +02:00
system.cpu.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id
2016-04-08 18:01:45 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id
2015-04-30 21:17:43 +02:00
system.cpu.icache.tags.occ_task_id_percent::1024 0.142578 # Percentage of cache occupancy per task id
2016-04-08 18:01:45 +02:00
system.cpu.icache.tags.tag_accesses 4216 # Number of tag accesses
system.cpu.icache.tags.data_accesses 4216 # Number of data accesses
2016-06-06 18:16:44 +02:00
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
2016-04-08 18:01:45 +02:00
system.cpu.icache.ReadReq_hits::cpu.inst 1577 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1577 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1577 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1577 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1577 # number of overall hits
system.cpu.icache.overall_hits::total 1577 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 384 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 384 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 384 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 384 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 384 # number of overall misses
system.cpu.icache.overall_misses::total 384 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 26669500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 26669500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 26669500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 26669500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 26669500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 26669500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1961 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1961 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1961 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1961 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1961 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1961 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.195818 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.195818 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.195818 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.195818 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.195818 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.195818 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69451.822917 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 69451.822917 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 69451.822917 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 69451.822917 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 69451.822917 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 69451.822917 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 423 # number of cycles access was blocked
2012-03-09 15:59:28 +01:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2014-09-03 13:42:59 +02:00
system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked
2012-03-09 15:59:28 +01:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
2016-04-08 18:01:45 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 84.600000 # average number of cycles each access was blocked
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-04-08 18:01:45 +02:00
system.cpu.icache.writebacks::writebacks 2 # number of writebacks
system.cpu.icache.writebacks::total 2 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 90 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 90 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 90 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 90 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 90 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 90 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 294 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 294 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 294 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 294 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 294 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 294 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21733500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 21733500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21733500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 21733500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21733500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 21733500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149924 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149924 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149924 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.149924 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149924 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.149924 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73923.469388 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73923.469388 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73923.469388 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 73923.469388 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73923.469388 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 73923.469388 # average overall mshr miss latency
2016-06-06 18:16:44 +02:00
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.replacements 0 # number of replacements
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.tags.tagsinuse 187.999052 # Cycle average of tags in use
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks.
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.tags.sampled_refs 355 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.109859 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.158865 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 46.840188 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004308 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001429 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.005737 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 355 # Occupied blocks per task id
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010834 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 3933 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 3933 # Number of data accesses
2016-06-06 18:16:44 +02:00
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 18 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 18 # number of ReadCleanReq hits
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 20 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 20 # number of ReadSharedReq hits
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.demand_hits::cpu.inst 18 # number of demand (read+write) hits
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 38 # number of demand (read+write) hits
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.overall_hits::cpu.inst 18 # number of overall hits
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits
system.cpu.l2cache.overall_hits::total 38 # number of overall hits
2014-06-22 23:33:09 +02:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 276 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 276 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 85 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 85 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 276 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 403 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses
system.cpu.l2cache.overall_misses::total 403 # number of overall misses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3333000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 3333000 # number of ReadExReq miss cycles
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21084500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 21084500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6625500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 6625500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 21084500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 9958500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 31043000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 21084500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 9958500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 31043000 # number of overall miss cycles
system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses)
2014-06-22 23:33:09 +02:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses)
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 294 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 294 # number of ReadCleanReq accesses(hits+misses)
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 105 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 105 # number of ReadSharedReq accesses(hits+misses)
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.demand_accesses::cpu.inst 294 # number of demand (read+write) accesses
2013-01-07 19:05:54 +01:00
system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.demand_accesses::total 441 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 294 # number of overall (read+write) accesses
2013-01-07 19:05:54 +01:00
system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.overall_accesses::total 441 # number of overall (read+write) accesses
2013-01-07 19:05:54 +01:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.938776 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.938776 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.809524 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.809524 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.938776 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.913832 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.938776 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.913832 # miss rate for overall accesses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79357.142857 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79357.142857 # average ReadExReq miss latency
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76393.115942 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76393.115942 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77947.058824 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77947.058824 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76393.115942 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78413.385827 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 77029.776675 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76393.115942 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78413.385827 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 77029.776675 # average overall miss latency
2013-01-07 19:05:54 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 6 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits
2014-06-22 23:33:09 +02:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 276 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 276 # number of ReadCleanReq MSHR misses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 79 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 79 # number of ReadSharedReq MSHR misses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.demand_mshr_misses::cpu.data 121 # number of demand (read+write) MSHR misses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.demand_mshr_misses::total 397 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.overall_mshr_misses::cpu.data 121 # number of overall MSHR misses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.overall_mshr_misses::total 397 # number of overall MSHR misses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2913000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2913000 # number of ReadExReq MSHR miss cycles
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 18324500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 18324500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5436000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5436000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18324500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8349000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 26673500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18324500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8349000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 26673500 # number of overall MSHR miss cycles
2013-01-07 19:05:54 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.938776 # mshr miss rate for ReadCleanReq accesses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.752381 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.752381 # mshr miss rate for ReadSharedReq accesses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for demand accesses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for demand accesses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::total 0.900227 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for overall accesses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for overall accesses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.overall_mshr_miss_rate::total 0.900227 # mshr miss rate for overall accesses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69357.142857 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69357.142857 # average ReadExReq mshr miss latency
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66393.115942 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66393.115942 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68810.126582 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68810.126582 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66393.115942 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67187.657431 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66393.115942 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67187.657431 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 443 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 45 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-06-06 18:16:44 +02:00
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
2016-04-08 18:01:45 +02:00
system.cpu.toL2Bus.trans_dist::ReadResp 399 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution
2016-04-08 18:01:45 +02:00
system.cpu.toL2Bus.trans_dist::ReadCleanReq 294 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.trans_dist::ReadSharedReq 105 # Transaction distribution
2016-04-08 18:01:45 +02:00
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 590 # Packet count per connected master and slave (bytes)
2015-09-15 15:14:09 +02:00
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes)
2016-04-08 18:01:45 +02:00
system.cpu.toL2Bus.pkt_count::total 884 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18944 # Cumulative packet size per connected master and slave (bytes)
2015-09-15 15:14:09 +02:00
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes)
2016-04-08 18:01:45 +02:00
system.cpu.toL2Bus.pkt_size::total 28352 # Cumulative packet size per connected master and slave (bytes)
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
2016-04-08 18:01:45 +02:00
system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.099773 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.300038 # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-04-08 18:01:45 +02:00
system.cpu.toL2Bus.snoop_fanout::0 397 90.02% 90.02% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 44 9.98% 100.00% # Request fanout histogram
2015-05-05 09:22:39 +02:00
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2015-05-05 09:22:39 +02:00
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
2016-04-08 18:01:45 +02:00
system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
2016-04-08 18:01:45 +02:00
system.cpu.toL2Bus.respLayer0.occupancy 441000 # Layer occupancy (ticks)
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%)
2016-04-08 18:01:45 +02:00
system.cpu.toL2Bus.respLayer1.occupancy 223494 # Layer occupancy (ticks)
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%)
2016-06-06 18:16:44 +02:00
system.membus.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
2016-04-08 18:01:45 +02:00
system.membus.trans_dist::ReadResp 355 # Transaction distribution
2014-12-23 15:31:20 +01:00
system.membus.trans_dist::ReadExReq 42 # Transaction distribution
system.membus.trans_dist::ReadExResp 42 # Transaction distribution
2016-04-08 18:01:45 +02:00
system.membus.trans_dist::ReadSharedReq 355 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 794 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 794 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes)
2014-12-23 15:31:20 +01:00
system.membus.snoops 0 # Total snoops (count)
2016-04-08 18:01:45 +02:00
system.membus.snoop_fanout::samples 397 # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-04-08 18:01:45 +02:00
system.membus.snoop_fanout::0 397 100.00% 100.00% # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
2016-04-08 18:01:45 +02:00
system.membus.snoop_fanout::total 397 # Request fanout histogram
system.membus.reqLayer0.occupancy 488000 # Layer occupancy (ticks)
2015-07-03 16:15:03 +02:00
system.membus.reqLayer0.utilization 2.8 # Layer utilization (%)
2016-04-08 18:01:45 +02:00
system.membus.respLayer1.occupancy 2101750 # Layer occupancy (ticks)
2015-07-03 16:15:03 +02:00
system.membus.respLayer1.utilization 12.2 # Layer utilization (%)
2012-03-09 15:59:28 +01:00
---------- End Simulation Statistics ----------
