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gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini

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ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[root]
type=Root
children=system
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
full_system=true
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
sim_quantum=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=LinuxArmSystem
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
atags_addr=134217728
stats: bump stats to reflect ruby tester changes
2015-12-12 23:27:38 +01:00
boot_loader=/dist/m5/system/binaries/boot_emm.arm
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
cache_line_size=64
clk_domain=system.clk_domain
stats: bump stats to reflect ruby tester changes
2015-12-12 23:27:38 +01:00
dtb_filename=/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
early_kernel_symbols=false
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
enable_context_switch_stats_dump=false
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: update stats to after GPU checkin
2016-01-22 16:42:13 +01:00
exit_on_work_items=false
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
flags_addr=469827632
gic_cpu_addr=738205696
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
have_large_asid_64=false
have_lpae=false
have_security=false
have_virtualization=false
highest_el_is_64=false
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
init_param=0
stats: bump stats to reflect ruby tester changes
2015-12-12 23:27:38 +01:00
kernel=/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
kernel_addr_check=true
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
load_addr_mask=268435455
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
load_offset=2147483648
machine_type=VExpress_EMM
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
mem_mode=atomic
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
mem_ranges=2147483648:2415919103
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
memories=system.physmem system.realview.nvmem system.realview.vram
stats: changes to due to recent set of patches
2015-03-09 15:39:09 +01:00
mmap_using_noreserve=false
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
multi_proc=true
stats: updates due to recent chagnesets
2015-11-16 12:08:57 +01:00
multi_thread=false
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
num_work_ids=16
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
panic_on_oops=true
panic_on_panic=true
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
phys_addr_range_64=40
stats: update stats to after GPU checkin
2016-01-22 16:42:13 +01:00
readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
reset_addr_64=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system_port=system.membus.slave[1]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.bridge]
type=Bridge
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
delay=50000
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
req_size=16
resp_size=16
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
master=system.iobus.slave[0]
slave=system.membus.master[0]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.cf0]
type=IdeDisk
children=image
delay=1000000
driveID=master
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
image=system.cf0.image
[system.cf0.image]
type=CowDiskImage
children=child
child=system.cf0.image.child
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
image_file=
read_only=false
table_size=65536
[system.cf0.image.child]
type=RawDiskImage
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: bump stats to reflect ruby tester changes
2015-12-12 23:27:38 +01:00
image_file=/dist/m5/system/disks/linux-aarch32-ael.img
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
read_only=true
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.clk_domain]
type=SrcClockDomain
clock=1000
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
domain_id=-1
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
init_perf_level=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
voltage_domain=system.voltage_domain
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.cpu0]
type=AtomicSimpleCPU
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
branchPred=Null
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
checker=Null
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
cpu_id=0
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
dstage2_mmu=system.cpu0.dstage2_mmu
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
dtb=system.cpu0.dtb
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
fastmem=false
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
function_trace=false
function_trace_start=0
interrupts=system.cpu0.interrupts
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
isa=system.cpu0.isa
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
istage2_mmu=system.cpu0.istage2_mmu
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
itb=system.cpu0.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
simpoint_start_insts=
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
simulate_data_stalls=false
simulate_inst_stalls=false
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
socket_id=0
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
switched_out=false
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system=system
tracer=system.cpu0.tracer
width=1
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
workload=
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
dcache_port=system.cpu0.dcache.cpu_side
icache_port=system.cpu0.icache.cpu_side
[system.cpu0.dcache]
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
type=Cache
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
children=tags
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
addr_ranges=0:18446744073709551615
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
assoc=2
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: updates due to recent chagnesets
2015-11-16 12:08:57 +01:00
clusivity=mostly_incl
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
demand_mshr_reserve=1
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
forward_snoops=true
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
hit_latency=2
stats: Update ARM stats to include programmable oscillators
2015-08-07 16:39:17 +02:00
is_read_only=false
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
max_miss_count=0
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
mshrs=6
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
prefetch_on_access=false
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
prefetcher=Null
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
response_latency=2
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
size=32768
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system=system
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
tags=system.cpu0.dcache.tags
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
tgts_per_mshr=8
write_buffers=16
stats: updates due to recent chagnesets
2015-11-16 12:08:57 +01:00
writeback_clean=true
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
cpu_side=system.cpu0.dcache_port
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
mem_side=system.cpu0.toL2Bus.slave[1]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.cpu0.dcache.tags]
type=LRU
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
assoc=2
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
block_size=64
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
hit_latency=2
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
size=32768
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
[system.cpu0.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
stats: changes to due to recent set of patches
2015-03-09 15:39:09 +01:00
sys=system
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
tlb=system.cpu0.dtb
[system.cpu0.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
[system.cpu0.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.cpu0.dtb]
type=ArmTLB
children=walker
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
is_stage2=false
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
size=64
walker=system.cpu0.dtb.walker
[system.cpu0.dtb.walker]
type=ArmTableWalker
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
is_stage2=false
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
num_squash_per_cycle=2
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
sys=system
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
port=system.cpu0.toL2Bus.slave[3]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.cpu0.icache]
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
type=Cache
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
children=tags
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
addr_ranges=0:18446744073709551615
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
assoc=2
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: updates due to recent chagnesets
2015-11-16 12:08:57 +01:00
clusivity=mostly_incl
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
demand_mshr_reserve=1
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: Update ARM stats to include programmable oscillators
2015-08-07 16:39:17 +02:00
forward_snoops=false
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
hit_latency=1
stats: Update ARM stats to include programmable oscillators
2015-08-07 16:39:17 +02:00
is_read_only=true
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
max_miss_count=0
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
mshrs=2
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
prefetch_on_access=false
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
prefetcher=Null
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
response_latency=1
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
size=32768
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system=system
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
tags=system.cpu0.icache.tags
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
tgts_per_mshr=8
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
write_buffers=8
stats: updates due to recent chagnesets
2015-11-16 12:08:57 +01:00
writeback_clean=true
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
cpu_side=system.cpu0.icache_port
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
mem_side=system.cpu0.toL2Bus.slave[0]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.cpu0.icache.tags]
type=LRU
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
assoc=2
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
block_size=64
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
hit_latency=1
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
size=32768
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.cpu0.interrupts]
type=ArmInterrupts
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
[system.cpu0.isa]
type=ArmISA
stats: updates due to recent chagnesets
2015-11-16 12:08:57 +01:00
decoderFlavour=Generic
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
fpsid=1090793632
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
id_mmfr0=270536963
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
id_mmfr1=0
id_mmfr2=19070976
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
id_mmfr3=34611729
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
id_pfr0=49
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
id_pfr1=4113
midr=1091551472
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pmu=Null
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system=system
[system.cpu0.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
stats: changes to due to recent set of patches
2015-03-09 15:39:09 +01:00
sys=system
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
tlb=system.cpu0.itb
[system.cpu0.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu0.istage2_mmu.stage2_tlb.walker
[system.cpu0.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.cpu0.itb]
type=ArmTLB
children=walker
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
is_stage2=false
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
size=64
walker=system.cpu0.itb.walker
[system.cpu0.itb.walker]
type=ArmTableWalker
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
is_stage2=false
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
num_squash_per_cycle=2
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
sys=system
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
port=system.cpu0.toL2Bus.slave[2]
[system.cpu0.l2cache]
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
type=Cache
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
children=prefetcher tags
addr_ranges=0:18446744073709551615
assoc=16
clk_domain=system.cpu_clk_domain
stats: updates due to recent chagnesets
2015-11-16 12:08:57 +01:00
clusivity=mostly_excl
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
demand_mshr_reserve=1
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
eventq_index=0
forward_snoops=true
hit_latency=12
stats: Update ARM stats to include programmable oscillators
2015-08-07 16:39:17 +02:00
is_read_only=false
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
max_miss_count=0
mshrs=16
prefetch_on_access=true
prefetcher=system.cpu0.l2cache.prefetcher
response_latency=12
sequential_access=false
size=1048576
system=system
tags=system.cpu0.l2cache.tags
tgts_per_mshr=8
write_buffers=8
stats: updates due to recent chagnesets
2015-11-16 12:08:57 +01:00
writeback_clean=false
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
cpu_side=system.cpu0.toL2Bus.master[0]
mem_side=system.toL2Bus.slave[0]
[system.cpu0.l2cache.prefetcher]
type=StridePrefetcher
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
cache_snoop=false
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
clk_domain=system.cpu_clk_domain
degree=8
eventq_index=0
latency=1
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
max_conf=7
min_conf=0
on_data=true
on_inst=true
on_miss=false
on_read=true
on_write=true
queue_filter=true
queue_size=32
queue_squash=true
start_conf=4
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
sys=system
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
table_assoc=4
table_sets=16
tag_prefetch=true
thresh_conf=4
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
use_master_id=true
[system.cpu0.l2cache.tags]
type=RandomRepl
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
hit_latency=12
sequential_access=false
size=1048576
[system.cpu0.toL2Bus]
type=CoherentXBar
stats: updates due to recent chagnesets
2015-11-16 12:08:57 +01:00
children=snoop_filter
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
clk_domain=system.cpu_clk_domain
eventq_index=0
stats: changes to due to recent set of patches
2015-03-09 15:39:09 +01:00
forward_latency=0
frontend_latency=1
response_latency=1
stats: updates due to recent chagnesets
2015-11-16 12:08:57 +01:00
snoop_filter=system.cpu0.toL2Bus.snoop_filter
stats: changes to due to recent set of patches
2015-03-09 15:39:09 +01:00
snoop_response_latency=1
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system=system
use_default_range=false
width=32
master=system.cpu0.l2cache.cpu_side
stats: changes to due to recent set of patches
2015-03-09 15:39:09 +01:00
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
stats: updates due to recent chagnesets
2015-11-16 12:08:57 +01:00
[system.cpu0.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.cpu0.tracer]
type=ExeTracer
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.cpu1]
type=AtomicSimpleCPU
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
branchPred=Null
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
checker=Null
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
cpu_id=1
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
dstage2_mmu=system.cpu1.dstage2_mmu
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
dtb=system.cpu1.dtb
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
fastmem=false
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
function_trace=false
function_trace_start=0
interrupts=system.cpu1.interrupts
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
isa=system.cpu1.isa
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
istage2_mmu=system.cpu1.istage2_mmu
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
itb=system.cpu1.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
simpoint_start_insts=
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
simulate_data_stalls=false
simulate_inst_stalls=false
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
socket_id=0
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
switched_out=false
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system=system
tracer=system.cpu1.tracer
width=1
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
workload=
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
dcache_port=system.cpu1.dcache.cpu_side
icache_port=system.cpu1.icache.cpu_side
[system.cpu1.dcache]
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
type=Cache
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
children=tags
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
addr_ranges=0:18446744073709551615
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
assoc=2
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: updates due to recent chagnesets
2015-11-16 12:08:57 +01:00
clusivity=mostly_incl
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
demand_mshr_reserve=1
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
forward_snoops=true
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
hit_latency=2
stats: Update ARM stats to include programmable oscillators
2015-08-07 16:39:17 +02:00
is_read_only=false
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
max_miss_count=0
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
mshrs=6
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
prefetch_on_access=false
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
prefetcher=Null
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
response_latency=2
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
size=32768
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system=system
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
tags=system.cpu1.dcache.tags
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
tgts_per_mshr=8
write_buffers=16
stats: updates due to recent chagnesets
2015-11-16 12:08:57 +01:00
writeback_clean=true
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
cpu_side=system.cpu1.dcache_port
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
mem_side=system.cpu1.toL2Bus.slave[1]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.cpu1.dcache.tags]
type=LRU
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
assoc=2
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
block_size=64
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
hit_latency=2
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
size=32768
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
[system.cpu1.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
stats: changes to due to recent set of patches
2015-03-09 15:39:09 +01:00
sys=system
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
tlb=system.cpu1.dtb
[system.cpu1.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
[system.cpu1.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.cpu1.dtb]
type=ArmTLB
children=walker
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
is_stage2=false
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
size=64
walker=system.cpu1.dtb.walker
[system.cpu1.dtb.walker]
type=ArmTableWalker
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
is_stage2=false
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
num_squash_per_cycle=2
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
sys=system
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
port=system.cpu1.toL2Bus.slave[3]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.cpu1.icache]
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
type=Cache
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
children=tags
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
addr_ranges=0:18446744073709551615
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
assoc=2
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: updates due to recent chagnesets
2015-11-16 12:08:57 +01:00
clusivity=mostly_incl
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
demand_mshr_reserve=1
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: Update ARM stats to include programmable oscillators
2015-08-07 16:39:17 +02:00
forward_snoops=false
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
hit_latency=1
stats: Update ARM stats to include programmable oscillators
2015-08-07 16:39:17 +02:00
is_read_only=true
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
max_miss_count=0
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
mshrs=2
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
prefetch_on_access=false
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
prefetcher=Null
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
response_latency=1
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
size=32768
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system=system
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
tags=system.cpu1.icache.tags
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
tgts_per_mshr=8
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
write_buffers=8
stats: updates due to recent chagnesets
2015-11-16 12:08:57 +01:00
writeback_clean=true
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
cpu_side=system.cpu1.icache_port
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
mem_side=system.cpu1.toL2Bus.slave[0]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.cpu1.icache.tags]
type=LRU
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
assoc=2
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
block_size=64
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
hit_latency=1
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
size=32768
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.cpu1.interrupts]
type=ArmInterrupts
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
[system.cpu1.isa]
type=ArmISA
stats: updates due to recent chagnesets
2015-11-16 12:08:57 +01:00
decoderFlavour=Generic
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
fpsid=1090793632
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
id_mmfr0=270536963
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
id_mmfr1=0
id_mmfr2=19070976
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
id_mmfr3=34611729
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
id_pfr0=49
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
id_pfr1=4113
midr=1091551472
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pmu=Null
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system=system
[system.cpu1.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
stats: changes to due to recent set of patches
2015-03-09 15:39:09 +01:00
sys=system
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
tlb=system.cpu1.itb
[system.cpu1.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu1.istage2_mmu.stage2_tlb.walker
[system.cpu1.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.cpu1.itb]
type=ArmTLB
children=walker
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
is_stage2=false
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
size=64
walker=system.cpu1.itb.walker
[system.cpu1.itb.walker]
type=ArmTableWalker
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
is_stage2=false
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
num_squash_per_cycle=2
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
sys=system
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
port=system.cpu1.toL2Bus.slave[2]
[system.cpu1.l2cache]
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
type=Cache
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
children=prefetcher tags
addr_ranges=0:18446744073709551615
assoc=16
clk_domain=system.cpu_clk_domain
stats: updates due to recent chagnesets
2015-11-16 12:08:57 +01:00
clusivity=mostly_excl
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
demand_mshr_reserve=1
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
eventq_index=0
forward_snoops=true
hit_latency=12
stats: Update ARM stats to include programmable oscillators
2015-08-07 16:39:17 +02:00
is_read_only=false
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
max_miss_count=0
mshrs=16
prefetch_on_access=true
prefetcher=system.cpu1.l2cache.prefetcher
response_latency=12
sequential_access=false
size=1048576
system=system
tags=system.cpu1.l2cache.tags
tgts_per_mshr=8
write_buffers=8
stats: updates due to recent chagnesets
2015-11-16 12:08:57 +01:00
writeback_clean=false
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
cpu_side=system.cpu1.toL2Bus.master[0]
mem_side=system.toL2Bus.slave[1]
[system.cpu1.l2cache.prefetcher]
type=StridePrefetcher
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
cache_snoop=false
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
clk_domain=system.cpu_clk_domain
degree=8
eventq_index=0
latency=1
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
max_conf=7
min_conf=0
on_data=true
on_inst=true
on_miss=false
on_read=true
on_write=true
queue_filter=true
queue_size=32
queue_squash=true
start_conf=4
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
sys=system
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
table_assoc=4
table_sets=16
tag_prefetch=true
thresh_conf=4
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
use_master_id=true
[system.cpu1.l2cache.tags]
type=RandomRepl
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
hit_latency=12
sequential_access=false
size=1048576
[system.cpu1.toL2Bus]
type=CoherentXBar
stats: updates due to recent chagnesets
2015-11-16 12:08:57 +01:00
children=snoop_filter
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
clk_domain=system.cpu_clk_domain
eventq_index=0
stats: changes to due to recent set of patches
2015-03-09 15:39:09 +01:00
forward_latency=0
frontend_latency=1
response_latency=1
stats: updates due to recent chagnesets
2015-11-16 12:08:57 +01:00
snoop_filter=system.cpu1.toL2Bus.snoop_filter
stats: changes to due to recent set of patches
2015-03-09 15:39:09 +01:00
snoop_response_latency=1
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system=system
use_default_range=false
width=32
master=system.cpu1.l2cache.cpu_side
stats: changes to due to recent set of patches
2015-03-09 15:39:09 +01:00
slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
stats: updates due to recent chagnesets
2015-11-16 12:08:57 +01:00
[system.cpu1.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.cpu1.tracer]
type=ExeTracer
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
domain_id=-1
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
init_perf_level=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
voltage_domain=system.voltage_domain
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.intrctrl]
type=IntrControl
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
sys=system
[system.iobus]
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
type=NoncoherentXBar
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: changes to due to recent set of patches
2015-03-09 15:39:09 +01:00
forward_latency=1
frontend_latency=2
response_latency=2
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
use_default_range=false
stats: changes to due to recent set of patches
2015-03-09 15:39:09 +01:00
width=16
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.iocache]
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
type=Cache
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
children=tags
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
addr_ranges=2147483648:2415919103
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
assoc=8
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to recent chagnesets
2015-11-16 12:08:57 +01:00
clusivity=mostly_incl
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
demand_mshr_reserve=1
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
forward_snoops=false
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
hit_latency=50
stats: Update ARM stats to include programmable oscillators
2015-08-07 16:39:17 +02:00
is_read_only=false
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
max_miss_count=0
mshrs=20
prefetch_on_access=false
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
prefetcher=Null
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
response_latency=50
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
size=1024
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system=system
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
tags=system.iocache.tags
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
tgts_per_mshr=12
write_buffers=8
stats: updates due to recent chagnesets
2015-11-16 12:08:57 +01:00
writeback_clean=false
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
cpu_side=system.iobus.master[25]
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
mem_side=system.membus.slave[3]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.iocache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
hit_latency=50
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
size=1024
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.l2c]
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
type=Cache
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
children=tags
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
addr_ranges=0:18446744073709551615
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
assoc=8
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: updates due to recent chagnesets
2015-11-16 12:08:57 +01:00
clusivity=mostly_incl
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
demand_mshr_reserve=1
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
forward_snoops=true
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
hit_latency=20
stats: Update ARM stats to include programmable oscillators
2015-08-07 16:39:17 +02:00
is_read_only=false
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
max_miss_count=0
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
mshrs=20
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
prefetch_on_access=false
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
prefetcher=Null
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
response_latency=20
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
size=4194304
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system=system
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
tags=system.l2c.tags
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
tgts_per_mshr=12
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
write_buffers=8
stats: updates due to recent chagnesets
2015-11-16 12:08:57 +01:00
writeback_clean=false
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
cpu_side=system.toL2Bus.master[0]
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
mem_side=system.membus.slave[2]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.l2c.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
hit_latency=20
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
size=4194304
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.membus]
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
type=CoherentXBar
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
children=badaddr_responder
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: changes to due to recent set of patches
2015-03-09 15:39:09 +01:00
forward_latency=4
frontend_latency=3
response_latency=2
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
snoop_filter=Null
stats: changes to due to recent set of patches
2015-03-09 15:39:09 +01:00
snoop_response_latency=4
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
system=system
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
use_default_range=false
stats: changes to due to recent set of patches
2015-03-09 15:39:09 +01:00
width=16
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
default=system.membus.badaddr_responder.pio
stats: Update ARM stats to include programmable oscillators
2015-08-07 16:39:17 +02:00
master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.membus.badaddr_responder]
type=IsaFake
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
fake_mem=false
pio_addr=0
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
pio_size=8
ret_bad_addr=true
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=warn
pio=system.membus.default
[system.physmem]
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
type=SimpleMemory
bandwidth=73.000000
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
conf_table_reported=true
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
in_addr_map=true
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
latency=30000
latency_var=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
null=false
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
range=2147483648:2415919103
port=system.membus.master[5]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.realview]
type=RealView
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
intrctrl=system.intrctrl
system=system
[system.realview.aaci_fake]
type=AmbaFake
amba_id=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
ignore_access=false
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio_addr=470024192
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system=system
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio=system.iobus.master[18]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.realview.cf_ctrl]
type=IdeController
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
BAR0=471465984
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
BAR0LegacyIO=true
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
BAR0Size=256
BAR1=471466240
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
BAR1LegacyIO=true
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
BAR1Size=4096
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
BAR2=1
BAR2LegacyIO=false
BAR2Size=8
BAR3=1
BAR3LegacyIO=false
BAR3Size=4
BAR4=1
BAR4LegacyIO=false
BAR4Size=16
BAR5=1
BAR5LegacyIO=false
BAR5Size=0
BIST=0
CacheLineSize=0
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
CapabilityPtr=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
CardbusCIS=0
ClassCode=1
Command=1
DeviceID=28945
ExpansionROM=0
HeaderType=0
InterruptLine=31
InterruptPin=1
LatencyTimer=0
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
LegacyIOBase=0
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
MSICAPMsgAddr=0
MSICAPMsgCtrl=0
MSICAPMsgData=0
MSICAPMsgUpperAddr=0
MSICAPNextCapability=0
MSICAPPendingBits=0
MSIXCAPBaseOffset=0
MSIXCAPCapId=0
MSIXCAPNextCapability=0
MSIXMsgCtrl=0
MSIXPbaOffset=0
MSIXTableOffset=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
MaximumLatency=0
MinimumGrant=0
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
PMCAPBaseOffset=0
PMCAPCapId=0
PMCAPCapabilities=0
PMCAPCtrlStatus=0
PMCAPNextCapability=0
PXCAPBaseOffset=0
PXCAPCapId=0
PXCAPCapabilities=0
PXCAPDevCap2=0
PXCAPDevCapabilities=0
PXCAPDevCtrl=0
PXCAPDevCtrl2=0
PXCAPDevStatus=0
PXCAPLinkCap=0
PXCAPLinkCtrl=0
PXCAPLinkStatus=0
PXCAPNextCapability=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
ProgIF=133
Revision=0
Status=640
SubClassCode=1
SubsystemID=0
SubsystemVendorID=0
VendorID=32902
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
config_latency=20000
ctrl_offset=2
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
disks=
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
host=system.realview.pci_host
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
io_shift=2
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
pci_bus=2
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pci_dev=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
pci_func=0
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=30000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system=system
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
dma=system.iobus.slave[2]
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
pio=system.iobus.master[9]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.realview.clcd]
type=Pl111
amba_id=1315089
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
enable_capture=true
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
gic=system.realview.gic
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
int_num=46
pio_addr=471793664
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
pio_latency=10000
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
pixel_clock=41667
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system=system
vnc=system.vncserver
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
dma=system.iobus.slave[1]
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
pio=system.iobus.master[5]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
stats: Update to reflect changes to RealView platform code
2015-12-04 01:19:05 +01:00
[system.realview.dcc]
type=SubSystem
children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
eventq_index=0
[system.realview.dcc.osc_cpu]
type=RealViewOsc
dcc=0
device=0
eventq_index=0
freq=16667
parent=system.realview.realview_io
position=0
site=1
voltage_domain=system.voltage_domain
[system.realview.dcc.osc_ddr]
type=RealViewOsc
dcc=0
device=8
eventq_index=0
freq=25000
parent=system.realview.realview_io
position=0
site=1
voltage_domain=system.voltage_domain
[system.realview.dcc.osc_hsbm]
type=RealViewOsc
dcc=0
device=4
eventq_index=0
freq=25000
parent=system.realview.realview_io
position=0
site=1
voltage_domain=system.voltage_domain
[system.realview.dcc.osc_pxl]
type=RealViewOsc
dcc=0
device=5
eventq_index=0
freq=42105
parent=system.realview.realview_io
position=0
site=1
voltage_domain=system.voltage_domain
[system.realview.dcc.osc_smb]
type=RealViewOsc
dcc=0
device=6
eventq_index=0
freq=20000
parent=system.realview.realview_io
position=0
site=1
voltage_domain=system.voltage_domain
[system.realview.dcc.osc_sys]
type=RealViewOsc
dcc=0
device=7
eventq_index=0
freq=16667
parent=system.realview.realview_io
position=0
site=1
voltage_domain=system.voltage_domain
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
[system.realview.energy_ctrl]
type=EnergyCtrl
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
dvfs_handler=system.dvfs_handler
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio_addr=470286336
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system=system
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio=system.iobus.master[22]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
[system.realview.ethernet]
type=IGbE
BAR0=0
BAR0LegacyIO=false
BAR0Size=131072
BAR1=0
BAR1LegacyIO=false
BAR1Size=0
BAR2=0
BAR2LegacyIO=false
BAR2Size=0
BAR3=0
BAR3LegacyIO=false
BAR3Size=0
BAR4=0
BAR4LegacyIO=false
BAR4Size=0
BAR5=0
BAR5LegacyIO=false
BAR5Size=0
BIST=0
CacheLineSize=0
CapabilityPtr=0
CardbusCIS=0
ClassCode=2
Command=0
DeviceID=4213
ExpansionROM=0
HeaderType=0
InterruptLine=1
InterruptPin=1
LatencyTimer=0
LegacyIOBase=0
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
MSICAPMsgAddr=0
MSICAPMsgCtrl=0
MSICAPMsgData=0
MSICAPMsgUpperAddr=0
MSICAPNextCapability=0
MSICAPPendingBits=0
MSIXCAPBaseOffset=0
MSIXCAPCapId=0
MSIXCAPNextCapability=0
MSIXMsgCtrl=0
MSIXPbaOffset=0
MSIXTableOffset=0
MaximumLatency=0
MinimumGrant=255
PMCAPBaseOffset=0
PMCAPCapId=0
PMCAPCapabilities=0
PMCAPCtrlStatus=0
PMCAPNextCapability=0
PXCAPBaseOffset=0
PXCAPCapId=0
PXCAPCapabilities=0
PXCAPDevCap2=0
PXCAPDevCapabilities=0
PXCAPDevCtrl=0
PXCAPDevCtrl2=0
PXCAPDevStatus=0
PXCAPLinkCap=0
PXCAPLinkCtrl=0
PXCAPLinkStatus=0
PXCAPNextCapability=0
ProgIF=0
Revision=0
Status=0
SubClassCode=0
SubsystemID=4104
SubsystemVendorID=32902
VendorID=32902
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
clk_domain=system.clk_domain
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
config_latency=20000
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
eventq_index=0
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
fetch_comp_delay=10000
fetch_delay=10000
hardware_address=00:90:00:00:00:01
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
host=system.realview.pci_host
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pci_bus=0
pci_dev=0
pci_func=0
phy_epid=896
phy_pid=680
pio_latency=30000
rx_desc_cache_size=64
rx_fifo_size=393216
rx_write_delay=0
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system=system
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
tx_desc_cache_size=64
tx_fifo_size=393216
tx_read_delay=0
wb_comp_delay=10000
wb_delay=10000
dma=system.iobus.slave[4]
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
pio=system.iobus.master[24]
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
[system.realview.generic_timer]
type=GenericTimer
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
gic=system.realview.gic
stats: Update ARM stats to include programmable oscillators
2015-08-07 16:39:17 +02:00
int_phys=29
int_virt=27
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system=system
[system.realview.gic]
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
type=Pl390
clk_domain=system.clk_domain
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
cpu_addr=738205696
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
cpu_pio_delay=10000
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
dist_addr=738201600
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
dist_pio_delay=10000
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
int_latency=10000
it_lines=128
platform=system.realview
system=system
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
pio=system.membus.master[2]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
[system.realview.hdlcd]
type=HDLcd
amba_id=1314816
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
enable_capture=true
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
gic=system.realview.gic
int_num=117
pio_addr=721420288
pio_latency=10000
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
pixel_buffer_size=2048
pixel_chunk=32
stats: Update to reflect changes to RealView platform code
2015-12-04 01:19:05 +01:00
pxl_clk=system.realview.dcc.osc_pxl
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system=system
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
vnc=system.vncserver
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
workaround_dma_line_count=true
stats: Update ARM stats to include programmable oscillators
2015-08-07 16:39:17 +02:00
workaround_swap_rb=true
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
dma=system.membus.slave[0]
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
pio=system.iobus.master[6]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
[system.realview.ide]
type=IdeController
BAR0=1
BAR0LegacyIO=false
BAR0Size=8
BAR1=1
BAR1LegacyIO=false
BAR1Size=4
BAR2=1
BAR2LegacyIO=false
BAR2Size=8
BAR3=1
BAR3LegacyIO=false
BAR3Size=4
BAR4=1
BAR4LegacyIO=false
BAR4Size=16
BAR5=1
BAR5LegacyIO=false
BAR5Size=0
BIST=0
CacheLineSize=0
CapabilityPtr=0
CardbusCIS=0
ClassCode=1
Command=0
DeviceID=28945
ExpansionROM=0
HeaderType=0
InterruptLine=2
InterruptPin=2
LatencyTimer=0
LegacyIOBase=0
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
MSICAPMsgAddr=0
MSICAPMsgCtrl=0
MSICAPMsgData=0
MSICAPMsgUpperAddr=0
MSICAPNextCapability=0
MSICAPPendingBits=0
MSIXCAPBaseOffset=0
MSIXCAPCapId=0
MSIXCAPNextCapability=0
MSIXMsgCtrl=0
MSIXPbaOffset=0
MSIXTableOffset=0
MaximumLatency=0
MinimumGrant=0
PMCAPBaseOffset=0
PMCAPCapId=0
PMCAPCapabilities=0
PMCAPCtrlStatus=0
PMCAPNextCapability=0
PXCAPBaseOffset=0
PXCAPCapId=0
PXCAPCapabilities=0
PXCAPDevCap2=0
PXCAPDevCapabilities=0
PXCAPDevCtrl=0
PXCAPDevCtrl2=0
PXCAPDevStatus=0
PXCAPLinkCap=0
PXCAPLinkCtrl=0
PXCAPLinkStatus=0
PXCAPNextCapability=0
ProgIF=133
Revision=0
Status=640
SubClassCode=1
SubsystemID=0
SubsystemVendorID=0
VendorID=32902
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
config_latency=20000
ctrl_offset=0
disks=system.cf0
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
host=system.realview.pci_host
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
io_shift=0
pci_bus=0
pci_dev=1
pci_func=0
pio_latency=30000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system=system
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
dma=system.iobus.slave[3]
pio=system.iobus.master[23]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.realview.kmi0]
type=Pl050
amba_id=1314896
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
gic=system.realview.gic
int_delay=1000000
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
int_num=44
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
is_mouse=false
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio_addr=470155264
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system=system
vnc=system.vncserver
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
pio=system.iobus.master[7]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.realview.kmi1]
type=Pl050
amba_id=1314896
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
gic=system.realview.gic
int_delay=1000000
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
int_num=45
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
is_mouse=true
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio_addr=470220800
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system=system
vnc=system.vncserver
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
pio=system.iobus.master[8]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.realview.l2x0_fake]
type=IsaFake
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
fake_mem=false
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio_addr=739246080
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
pio_size=4095
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio=system.iobus.master[12]
[system.realview.lan_fake]
type=IsaFake
clk_domain=system.clk_domain
eventq_index=0
fake_mem=false
pio_addr=436207616
pio_latency=100000
pio_size=65535
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[19]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.realview.local_cpu_timer]
type=CpuLocalTimer
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
gic=system.realview.gic
int_num_timer=29
int_num_watchdog=30
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio_addr=738721792
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system=system
stats: Update ARM stats to include programmable oscillators
2015-08-07 16:39:17 +02:00
pio=system.membus.master[4]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
stats: Update to reflect changes to RealView platform code
2015-12-04 01:19:05 +01:00
[system.realview.mcc]
type=SubSystem
children=osc_clcd osc_mcc osc_peripheral osc_system_bus
eventq_index=0
[system.realview.mcc.osc_clcd]
type=RealViewOsc
dcc=0
device=1
eventq_index=0
freq=42105
parent=system.realview.realview_io
position=0
site=0
voltage_domain=system.voltage_domain
[system.realview.mcc.osc_mcc]
type=RealViewOsc
dcc=0
device=0
eventq_index=0
freq=20000
parent=system.realview.realview_io
position=0
site=0
voltage_domain=system.voltage_domain
[system.realview.mcc.osc_peripheral]
type=RealViewOsc
dcc=0
device=2
eventq_index=0
freq=41667
parent=system.realview.realview_io
position=0
site=0
voltage_domain=system.voltage_domain
[system.realview.mcc.osc_system_bus]
type=RealViewOsc
dcc=0
device=4
eventq_index=0
freq=41667
parent=system.realview.realview_io
position=0
site=0
voltage_domain=system.voltage_domain
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.realview.mmc_fake]
type=AmbaFake
amba_id=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
ignore_access=false
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio_addr=470089728
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system=system
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio=system.iobus.master[21]
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
[system.realview.nvmem]
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
type=SimpleMemory
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
bandwidth=73.000000
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
conf_table_reported=false
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
in_addr_map=true
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
latency=30000
latency_var=0
null=false
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
range=0:67108863
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
port=system.membus.master[1]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
[system.realview.pci_host]
type=GenericPciHost
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
clk_domain=system.clk_domain
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
conf_base=805306368
conf_device_bits=16
conf_size=268435456
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
eventq_index=0
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
pci_dma_base=0
pci_mem_base=0
pci_pio_base=0
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
platform=system.realview
system=system
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
pio=system.iobus.master[2]
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.realview.realview_io]
type=RealViewCtrl
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
idreg=35979264
pio_addr=469827584
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
proc_id0=335544320
proc_id1=335544320
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system=system
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
pio=system.iobus.master[1]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
ARM: Update stats for IT and conditional branch changes
2012-03-21 16:36:45 +01:00
[system.realview.rtc]
type=PL031
amba_id=3412017
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for IT and conditional branch changes
2012-03-21 16:36:45 +01:00
gic=system.realview.gic
int_delay=100000
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
int_num=36
pio_addr=471269376
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system=system
ARM: Update stats for IT and conditional branch changes
2012-03-21 16:36:45 +01:00
time=Thu Jan 1 00:00:00 2009
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio=system.iobus.master[10]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.realview.sp810_fake]
type=AmbaFake
amba_id=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
ignore_access=true
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio_addr=469893120
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system=system
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio=system.iobus.master[16]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.realview.timer0]
type=Sp804
amba_id=1316868
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
clock0=1000000
clock1=1000000
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
gic=system.realview.gic
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
int_num0=34
int_num1=34
pio_addr=470876160
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system=system
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
pio=system.iobus.master[3]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.realview.timer1]
type=Sp804
amba_id=1316868
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
clock0=1000000
clock1=1000000
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
gic=system.realview.gic
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
int_num0=35
int_num1=35
pio_addr=470941696
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system=system
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
pio=system.iobus.master[4]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.realview.uart]
type=Pl011
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
end_on_eot=false
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
gic=system.realview.gic
int_delay=100000
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
int_num=37
pio_addr=470351872
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
platform=system.realview
system=system
terminal=system.terminal
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
pio=system.iobus.master[0]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.realview.uart1_fake]
type=AmbaFake
amba_id=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
ignore_access=false
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio_addr=470417408
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system=system
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio=system.iobus.master[13]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.realview.uart2_fake]
type=AmbaFake
amba_id=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
ignore_access=false
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio_addr=470482944
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system=system
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio=system.iobus.master[14]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.realview.uart3_fake]
type=AmbaFake
amba_id=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
ignore_access=false
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio_addr=470548480
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system=system
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio=system.iobus.master[15]
[system.realview.usb_fake]
type=IsaFake
clk_domain=system.clk_domain
eventq_index=0
fake_mem=false
pio_addr=452984832
pio_latency=100000
pio_size=131071
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[20]
[system.realview.vgic]
type=VGic
clk_domain=system.clk_domain
eventq_index=0
gic=system.realview.gic
hv_addr=738213888
pio_delay=10000
platform=system.realview
ppint=25
system=system
vcpu_addr=738222080
stats: Update ARM stats to include programmable oscillators
2015-08-07 16:39:17 +02:00
pio=system.membus.master[3]
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
[system.realview.vram]
type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=false
eventq_index=0
in_addr_map=true
latency=30000
latency_var=0
null=false
range=402653184:436207615
port=system.iobus.master[11]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.realview.watchdog_fake]
type=AmbaFake
amba_id=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
ignore_access=false
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio_addr=470745088
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system=system
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
pio=system.iobus.master[17]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.terminal]
type=Terminal
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
intr_control=system.intrctrl
number=0
output=true
port=3456
[system.toL2Bus]
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
type=CoherentXBar
stats: updates due to recent chagnesets
2015-11-16 12:08:57 +01:00
children=snoop_filter
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: changes to due to recent set of patches
2015-03-09 15:39:09 +01:00
forward_latency=0
frontend_latency=1
response_latency=1
stats: updates due to recent chagnesets
2015-11-16 12:08:57 +01:00
snoop_filter=system.toL2Bus.snoop_filter
stats: changes to due to recent set of patches
2015-03-09 15:39:09 +01:00
snoop_response_latency=1
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
system=system
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
use_default_range=false
stats: changes to due to recent set of patches
2015-03-09 15:39:09 +01:00
width=32
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
master=system.l2c.cpu_side
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
stats: updates due to recent chagnesets
2015-11-16 12:08:57 +01:00
[system.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.vncserver]
type=VncServer
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
frame_capture=false
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
number=0
port=5900
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.voltage_domain]
type=VoltageDomain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
voltage=1.000000
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