2011-08-15 03:34:17 +02:00
---------- Begin Simulation Statistics ----------
2015-11-16 12:08:57 +01:00
sim_seconds 5.152314 # Number of seconds simulated
sim_ticks 5152313559000 # Number of ticks simulated
final_tick 5152313559000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2011-08-15 03:34:17 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
2015-12-02 15:58:24 +01:00
host_inst_rate 120887 # Simulator instruction rate (inst/s)
host_op_rate 238950 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1530523119 # Simulator tick rate (ticks/s)
host_mem_usage 767492 # Number of bytes of host memory used
host_seconds 3366.37 # Real time elapsed on the host
2015-11-16 12:08:57 +01:00
sim_insts 406949634 # Number of instructions simulated
sim_ops 804396566 # Number of ops (including micro ops) simulated
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2015-11-06 09:26:50 +01:00
system.physmem.bytes_read::cpu.dtb.walker 4096 # Number of bytes read from this memory
2015-09-25 13:27:03 +02:00
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
2015-11-16 12:08:57 +01:00
system.physmem.bytes_read::cpu.inst 1035776 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10724352 # Number of bytes read from this memory
2014-11-12 15:05:25 +01:00
system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
2015-11-16 12:08:57 +01:00
system.physmem.bytes_read::total 11792896 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1035776 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1035776 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 9542784 # Number of bytes written to this memory
system.physmem.bytes_written::total 9542784 # Number of bytes written to this memory
2015-11-06 09:26:50 +01:00
system.physmem.num_reads::cpu.dtb.walker 64 # Number of read requests responded to by this memory
2015-09-25 13:27:03 +02:00
system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
2015-11-16 12:08:57 +01:00
system.physmem.num_reads::cpu.inst 16184 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 167568 # Number of read requests responded to by this memory
2014-11-12 15:05:25 +01:00
system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
2015-11-16 12:08:57 +01:00
system.physmem.num_reads::total 184264 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 149106 # Number of write requests responded to by this memory
system.physmem.num_writes::total 149106 # Number of write requests responded to by this memory
2015-11-06 09:26:50 +01:00
system.physmem.bw_read::cpu.dtb.walker 795 # Total read bandwidth from this memory (bytes/s)
2015-09-25 13:27:03 +02:00
system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
2015-11-16 12:08:57 +01:00
system.physmem.bw_read::cpu.inst 201031 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2081463 # Total read bandwidth from this memory (bytes/s)
2015-11-06 09:26:50 +01:00
system.physmem.bw_read::pc.south_bridge.ide 5503 # Total read bandwidth from this memory (bytes/s)
2015-11-16 12:08:57 +01:00
system.physmem.bw_read::total 2288854 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 201031 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 201031 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1852136 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1852136 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1852136 # Total bandwidth to/from this memory (bytes/s)
2015-11-06 09:26:50 +01:00
system.physmem.bw_total::cpu.dtb.walker 795 # Total bandwidth to/from this memory (bytes/s)
2015-09-25 13:27:03 +02:00
system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
2015-11-16 12:08:57 +01:00
system.physmem.bw_total::cpu.inst 201031 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2081463 # Total bandwidth to/from this memory (bytes/s)
2015-11-06 09:26:50 +01:00
system.physmem.bw_total::pc.south_bridge.ide 5503 # Total bandwidth to/from this memory (bytes/s)
2015-11-16 12:08:57 +01:00
system.physmem.bw_total::total 4140990 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 184264 # Number of read requests accepted
system.physmem.writeReqs 149106 # Number of write requests accepted
system.physmem.readBursts 184264 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 149106 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 11780160 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 12736 # Total number of bytes read from write queue
system.physmem.bytesWritten 9541632 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 11792896 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 9542784 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 199 # Number of DRAM read bursts serviced by the write queue
2015-07-03 16:15:03 +02:00
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
2015-11-16 12:08:57 +01:00
system.physmem.neitherReadNorWriteReqs 58128 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 11264 # Per bank write bursts
system.physmem.perBankRdBursts::1 10595 # Per bank write bursts
system.physmem.perBankRdBursts::2 12318 # Per bank write bursts
system.physmem.perBankRdBursts::3 11595 # Per bank write bursts
system.physmem.perBankRdBursts::4 11491 # Per bank write bursts
system.physmem.perBankRdBursts::5 10948 # Per bank write bursts
system.physmem.perBankRdBursts::6 11084 # Per bank write bursts
system.physmem.perBankRdBursts::7 11123 # Per bank write bursts
2015-11-06 09:26:50 +01:00
system.physmem.perBankRdBursts::8 10622 # Per bank write bursts
2015-11-16 12:08:57 +01:00
system.physmem.perBankRdBursts::9 11029 # Per bank write bursts
2015-11-06 09:26:50 +01:00
system.physmem.perBankRdBursts::10 11540 # Per bank write bursts
2015-11-16 12:08:57 +01:00
system.physmem.perBankRdBursts::11 11371 # Per bank write bursts
2015-11-06 09:26:50 +01:00
system.physmem.perBankRdBursts::12 12384 # Per bank write bursts
2015-11-16 12:08:57 +01:00
system.physmem.perBankRdBursts::13 12484 # Per bank write bursts
system.physmem.perBankRdBursts::14 11992 # Per bank write bursts
2015-11-06 09:26:50 +01:00
system.physmem.perBankRdBursts::15 12225 # Per bank write bursts
2015-11-16 12:08:57 +01:00
system.physmem.perBankWrBursts::0 9588 # Per bank write bursts
system.physmem.perBankWrBursts::1 9011 # Per bank write bursts
system.physmem.perBankWrBursts::2 9691 # Per bank write bursts
system.physmem.perBankWrBursts::3 9485 # Per bank write bursts
system.physmem.perBankWrBursts::4 9599 # Per bank write bursts
system.physmem.perBankWrBursts::5 9316 # Per bank write bursts
system.physmem.perBankWrBursts::6 9059 # Per bank write bursts
system.physmem.perBankWrBursts::7 9052 # Per bank write bursts
2015-11-06 09:26:50 +01:00
system.physmem.perBankWrBursts::8 8752 # Per bank write bursts
2015-11-16 12:08:57 +01:00
system.physmem.perBankWrBursts::9 9407 # Per bank write bursts
2015-11-06 09:26:50 +01:00
system.physmem.perBankWrBursts::10 9210 # Per bank write bursts
2015-11-16 12:08:57 +01:00
system.physmem.perBankWrBursts::11 8756 # Per bank write bursts
system.physmem.perBankWrBursts::12 9659 # Per bank write bursts
system.physmem.perBankWrBursts::13 9383 # Per bank write bursts
system.physmem.perBankWrBursts::14 9487 # Per bank write bursts
system.physmem.perBankWrBursts::15 9633 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
2015-11-16 12:08:57 +01:00
system.physmem.numWrRetry 6 # Number of times write queue was full causing retry
system.physmem.totGap 5152313509500 # Total gap between requests
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2015-11-16 12:08:57 +01:00
system.physmem.readPktSize::6 184264 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
2015-11-16 12:08:57 +01:00
system.physmem.writePktSize::6 149106 # Write request sizes (log2)
2015-11-06 09:26:50 +01:00
system.physmem.rdQLenPdf::0 169844 # What read queue length does an incoming req see
2015-11-16 12:08:57 +01:00
system.physmem.rdQLenPdf::1 11471 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 1942 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 461 # What read queue length does an incoming req see
2015-11-06 09:26:50 +01:00
system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 40 # What read queue length does an incoming req see
2015-11-16 12:08:57 +01:00
system.physmem.rdQLenPdf::6 36 # What read queue length does an incoming req see
2015-11-06 09:26:50 +01:00
system.physmem.rdQLenPdf::7 37 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 26 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 33 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see
2015-11-16 12:08:57 +01:00
system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see
2015-11-06 09:26:50 +01:00
system.physmem.rdQLenPdf::12 24 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 23 # What read queue length does an incoming req see
2015-11-16 12:08:57 +01:00
system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see
2015-09-15 15:14:09 +02:00
system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see
2015-11-06 09:26:50 +01:00
system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see
2015-11-16 12:08:57 +01:00
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
2014-09-03 13:42:59 +02:00
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
2014-03-23 16:12:19 +01:00
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
2013-10-16 16:44:12 +02:00
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
2013-06-27 11:49:51 +02:00
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
2015-11-16 12:08:57 +01:00
system.physmem.wrQLenPdf::15 2273 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 2969 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 7394 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 7367 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 8312 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 8280 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 9465 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 8746 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 9965 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 9927 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 9938 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 11756 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 9034 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 8390 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 8612 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 7922 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 7664 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 7491 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 338 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 240 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 199 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 193 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 214 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 203 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 145 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 172 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 129 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 198 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 117 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 140 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 103 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 97 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 129 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 139 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 148 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 98 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 76 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 62 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 85 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 59 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 40 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 62 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 46 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 25 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 35 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 34 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 13 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 11 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 36 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 73162 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 291.431727 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 174.195666 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 313.031817 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 28160 38.49% 38.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 17784 24.31% 62.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 7754 10.60% 73.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 4294 5.87% 79.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2960 4.05% 83.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 2393 3.27% 86.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1365 1.87% 88.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1117 1.53% 89.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 7335 10.03% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 73162 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 7284 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 25.269357 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 562.815412 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 7283 99.99% 99.99% # Reads before turning the bus around for writes
2014-03-23 16:12:19 +01:00
system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes
2015-11-16 12:08:57 +01:00
system.physmem.rdPerTurnAround::total 7284 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 7284 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 20.467875 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.652190 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 13.050833 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 6239 85.65% 85.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 170 2.33% 87.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 40 0.55% 88.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 173 2.38% 90.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 22 0.30% 91.21% # Writes before turning the bus around for reads
2015-11-06 09:26:50 +01:00
system.physmem.wrPerTurnAround::36-39 151 2.07% 93.29% # Writes before turning the bus around for reads
2015-11-16 12:08:57 +01:00
system.physmem.wrPerTurnAround::40-43 103 1.41% 94.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 10 0.14% 94.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 24 0.33% 95.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 33 0.45% 95.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 7 0.10% 95.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 8 0.11% 95.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 223 3.06% 98.89% # Writes before turning the bus around for reads
2015-11-06 09:26:50 +01:00
system.physmem.wrPerTurnAround::68-71 4 0.05% 98.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 9 0.12% 99.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 29 0.40% 99.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 2 0.03% 99.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 2 0.03% 99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 1 0.01% 99.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 6 0.08% 99.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 2 0.03% 99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123 1 0.01% 99.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 3 0.04% 99.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 18 0.25% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 1 0.01% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155 1 0.01% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 1 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167 1 0.01% 100.00% # Writes before turning the bus around for reads
2015-11-16 12:08:57 +01:00
system.physmem.wrPerTurnAround::total 7284 # Writes before turning the bus around for reads
system.physmem.totQLat 2101117298 # Total ticks spent queuing
system.physmem.totMemAccLat 5552336048 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 920325000 # Total ticks spent in databus transfers
system.physmem.avgQLat 11415.08 # Average queueing delay per DRAM burst
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2015-11-16 12:08:57 +01:00
system.physmem.avgMemAccLat 30165.08 # Average memory access latency per DRAM burst
2015-09-25 13:27:03 +02:00
system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.85 # Average system write bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2015-03-02 11:04:20 +01:00
system.physmem.busUtil 0.03 # Data bus utilization in percentage
2013-11-01 16:56:34 +01:00
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
2015-07-03 16:15:03 +02:00
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
2015-09-25 13:27:03 +02:00
system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing
2015-11-06 09:26:50 +01:00
system.physmem.avgWrQLen 22.81 # Average write queue length when enqueuing
2015-11-16 12:08:57 +01:00
system.physmem.readRowHits 150235 # Number of row buffer hits during reads
system.physmem.writeRowHits 109755 # Number of row buffer hits during writes
system.physmem.readRowHitRate 81.62 # Row buffer hit rate for reads
2015-11-06 09:26:50 +01:00
system.physmem.writeRowHitRate 73.61 # Row buffer hit rate for writes
2015-11-16 12:08:57 +01:00
system.physmem.avgGap 15455240.45 # Average gap between requests
2015-11-06 09:26:50 +01:00
system.physmem.pageHitRate 78.04 # Row buffer hit rate, read and write combined
2015-11-16 12:08:57 +01:00
system.physmem_0.actEnergy 269725680 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 147171750 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 705252600 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 484710480 # Energy for write commands per rank (pJ)
2015-11-06 09:26:50 +01:00
system.physmem_0.refreshEnergy 336523814640 # Energy for refresh commands per rank (pJ)
2015-11-16 12:08:57 +01:00
system.physmem_0.actBackEnergy 132965791830 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 2974749226500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 3445845693480 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.796291 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 4948684136224 # Time in different power states
2015-11-06 09:26:50 +01:00
system.physmem_0.memoryStateTime::REF 172046940000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
2015-11-16 12:08:57 +01:00
system.physmem_0.memoryStateTime::ACT 31582322276 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
2015-11-16 12:08:57 +01:00
system.physmem_1.actEnergy 283379040 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 154621500 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 730446600 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 481379760 # Energy for write commands per rank (pJ)
2015-11-06 09:26:50 +01:00
system.physmem_1.refreshEnergy 336523814640 # Energy for refresh commands per rank (pJ)
2015-11-16 12:08:57 +01:00
system.physmem_1.actBackEnergy 133234904790 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 2974513162500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 3445921708830 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.811045 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 4948281584736 # Time in different power states
2015-11-06 09:26:50 +01:00
system.physmem_1.memoryStateTime::REF 172046940000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
2015-11-16 12:08:57 +01:00
system.physmem_1.memoryStateTime::ACT 31981299014 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
2015-11-16 12:08:57 +01:00
system.cpu.branchPred.lookups 86361942 # Number of BP lookups
system.cpu.branchPred.condPredicted 86361942 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 844867 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 79712463 # Number of BTB lookups
system.cpu.branchPred.BTBHits 77809670 # Number of BTB hits
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2015-11-16 12:08:57 +01:00
system.cpu.branchPred.BTBHitPct 97.612929 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1539914 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 177576 # Number of incorrect RAS predictions.
2014-11-12 15:05:25 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2014-01-24 22:29:33 +01:00
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
2015-11-16 12:08:57 +01:00
system.cpu.numCycles 465537238 # number of cpu cycles simulated
2011-08-15 03:34:17 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
2015-11-16 12:08:57 +01:00
system.cpu.fetch.icacheStallCycles 27283425 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 426658175 # Number of instructions fetch has processed
system.cpu.fetch.Branches 86361942 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 79349584 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 433433945 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1774834 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 138611 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles 62197 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 198243 # Number of stall cycles due to pending traps
2015-11-06 09:26:50 +01:00
system.cpu.fetch.PendingQuiesceStallCycles 56 # Number of stall cycles due to pending quiesce instructions
2015-11-16 12:08:57 +01:00
system.cpu.fetch.IcacheWaitRetryStallCycles 777 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 8943730 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 426192 # Number of outstanding Icache misses that were squashed
2015-11-06 09:26:50 +01:00
system.cpu.fetch.ItlbSquashes 4516 # Number of outstanding ITLB misses that were squashed
2015-11-16 12:08:57 +01:00
system.cpu.fetch.rateDist::samples 462004671 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.822565 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.015508 # Number of instructions fetched each cycle (Total)
2011-08-15 03:34:17 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2015-11-16 12:08:57 +01:00
system.cpu.fetch.rateDist::0 297416009 64.38% 64.38% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 2127138 0.46% 64.84% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 72011199 15.59% 80.42% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 1542030 0.33% 80.76% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 2092912 0.45% 81.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 2282044 0.49% 81.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 1471797 0.32% 82.02% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1847192 0.40% 82.42% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 81214350 17.58% 100.00% # Number of instructions fetched each cycle (Total)
2011-08-15 03:34:17 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
2015-11-16 12:08:57 +01:00
system.cpu.fetch.rateDist::total 462004671 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.185510 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.916486 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 22519882 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 281035605 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 150243041 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 7318726 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 887417 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 834212570 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 887417 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 25306548 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 229981312 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 14515163 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 154096108 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 37218123 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 830907338 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 454391 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 12058587 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 208124 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 22290402 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 992604792 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 1804097397 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 1109074070 # Number of integer rename lookups
2015-11-06 09:26:50 +01:00
system.cpu.rename.fp_rename_lookups 286 # Number of floating rename lookups
2015-11-16 12:08:57 +01:00
system.cpu.rename.CommittedMaps 961885827 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 30718963 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 460377 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 463475 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 38191150 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 17040621 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 10018939 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1267546 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 1072117 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 825695768 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 1151715 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 820812543 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 215202 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 22450912 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 33825927 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 141995 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 462004671 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.776633 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 2.399879 # Number of insts issued each cycle
2011-08-15 03:34:17 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2015-11-16 12:08:57 +01:00
system.cpu.iq.issued_per_cycle::0 278825933 60.35% 60.35% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 13663917 2.96% 63.31% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 9689323 2.10% 65.41% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 6980180 1.51% 66.92% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 74150960 16.05% 82.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 4285873 0.93% 83.89% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 72643996 15.72% 99.62% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 1183653 0.26% 99.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 580836 0.13% 100.00% # Number of insts issued each cycle
2011-08-15 03:34:17 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
2015-11-16 12:08:57 +01:00
system.cpu.iq.issued_per_cycle::total 462004671 # Number of insts issued each cycle
2011-08-15 03:34:17 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2015-11-16 12:08:57 +01:00
system.cpu.iq.fu_full::IntAlu 1923038 72.06% 72.06% # attempts to use FU when none available
2015-11-06 09:26:50 +01:00
system.cpu.iq.fu_full::IntMult 0 0.00% 72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 72.06% # attempts to use FU when none available
2015-11-16 12:08:57 +01:00
system.cpu.iq.fu_full::MemRead 586062 21.96% 94.02% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 159510 5.98% 100.00% # attempts to use FU when none available
2011-08-15 03:34:17 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2015-11-16 12:08:57 +01:00
system.cpu.iq.FU_type_0::No_OpClass 284391 0.03% 0.03% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 792925473 96.60% 96.64% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 149981 0.02% 96.66% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 126333 0.02% 96.67% # Type of FU issued
2015-11-06 09:26:50 +01:00
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.67% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.67% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 89 0.00% 96.67% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.67% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.67% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.67% # Type of FU issued
2015-11-16 12:08:57 +01:00
system.cpu.iq.FU_type_0::MemRead 18051798 2.20% 98.87% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 9274478 1.13% 100.00% # Type of FU issued
2011-08-15 03:34:17 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2015-11-16 12:08:57 +01:00
system.cpu.iq.FU_type_0::total 820812543 # Type of FU issued
system.cpu.iq.rate 1.763151 # Inst issue rate
system.cpu.iq.fu_busy_cnt 2668610 # FU busy when requested
2015-11-06 09:26:50 +01:00
system.cpu.iq.fu_busy_rate 0.003251 # FU busy rate (busy events/executed inst)
2015-11-16 12:08:57 +01:00
system.cpu.iq.int_inst_queue_reads 2106513130 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 849310448 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 816528938 # Number of integer instruction queue wakeup accesses
2015-11-06 09:26:50 +01:00
system.cpu.iq.fp_inst_queue_reads 438 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 438 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 154 # Number of floating instruction queue wakeup accesses
2015-11-16 12:08:57 +01:00
system.cpu.iq.int_alu_accesses 823196553 # Number of integer alu accesses
2015-11-06 09:26:50 +01:00
system.cpu.iq.fp_alu_accesses 209 # Number of floating point alu accesses
2015-11-16 12:08:57 +01:00
system.cpu.iew.lsq.thread0.forwLoads 1863533 # Number of loads that had data forwarded from stores
2011-08-15 03:34:17 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2015-11-16 12:08:57 +01:00
system.cpu.iew.lsq.thread0.squashedLoads 3085538 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 14402 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 13954 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 1597584 # Number of stores squashed
2011-08-15 03:34:17 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2015-11-16 12:08:57 +01:00
system.cpu.iew.lsq.thread0.rescheduledLoads 2095829 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 68627 # Number of times an access to memory failed due to the cache being blocked
2011-08-15 03:34:17 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2015-11-16 12:08:57 +01:00
system.cpu.iew.iewSquashCycles 887417 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 206161533 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 15636111 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 826847483 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 165160 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 17040642 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 10018939 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 682638 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 383814 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 14427518 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 13954 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 477334 # Number of branches that were predicted taken incorrectly
2015-12-02 15:58:24 +01:00
system.cpu.iew.predictedNotTakenIncorrect 506558 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 983892 # Number of branch mispredicts detected at execute
2015-11-16 12:08:57 +01:00
system.cpu.iew.iewExecutedInsts 819301527 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 17680087 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1386795 # Number of squashed instructions skipped in execute
2011-08-15 03:34:17 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
2015-11-16 12:08:57 +01:00
system.cpu.iew.exec_refs 26745143 # number of memory reference insts executed
system.cpu.iew.exec_branches 82994335 # Number of branches executed
system.cpu.iew.exec_stores 9065056 # Number of stores executed
system.cpu.iew.exec_rate 1.759905 # Inst execution rate
system.cpu.iew.wb_sent 818828086 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 816529092 # cumulative count of insts written-back
system.cpu.iew.wb_producers 638693519 # num instructions producing a value
system.cpu.iew.wb_consumers 1046716801 # num instructions consuming a value
system.cpu.iew.wb_rate 1.753950 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.610188 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 22326581 # The number of squashed insts skipped by commit
2015-11-06 09:26:50 +01:00
system.cpu.commit.commitNonSpecStalls 1009720 # The number of times commit has been forced to stall to communicate backwards
2015-11-16 12:08:57 +01:00
system.cpu.commit.branchMispredicts 855503 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 458638769 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.753878 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.647523 # Number of insts commited each cycle
2011-08-15 03:34:17 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2015-11-16 12:08:57 +01:00
system.cpu.commit.committed_per_cycle::0 288181414 62.83% 62.83% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 11088145 2.42% 65.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 3640328 0.79% 66.05% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 74471829 16.24% 82.28% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 2429591 0.53% 82.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1624239 0.35% 83.17% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 1000805 0.22% 83.39% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 70851455 15.45% 98.83% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 5350963 1.17% 100.00% # Number of insts commited each cycle
2011-08-15 03:34:17 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2015-11-16 12:08:57 +01:00
system.cpu.commit.committed_per_cycle::total 458638769 # Number of insts commited each cycle
system.cpu.commit.committedInsts 406949634 # Number of instructions committed
system.cpu.commit.committedOps 804396566 # Number of ops (including micro ops) committed
2011-08-15 03:34:17 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
2015-11-16 12:08:57 +01:00
system.cpu.commit.refs 22376458 # Number of memory references committed
system.cpu.commit.loads 13955103 # Number of loads committed
2015-11-06 09:26:50 +01:00
system.cpu.commit.membars 448031 # Number of memory barriers committed
2015-11-16 12:08:57 +01:00
system.cpu.commit.branches 82000860 # Number of branches committed
2015-01-11 01:06:43 +01:00
system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
2015-11-16 12:08:57 +01:00
system.cpu.commit.int_insts 733378889 # Number of committed integer instructions.
2015-11-06 09:26:50 +01:00
system.cpu.commit.function_calls 1155590 # Number of function calls committed.
2015-11-16 12:08:57 +01:00
system.cpu.commit.op_class_0::No_OpClass 171811 0.02% 0.02% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 781584496 97.16% 97.19% # Class of committed instruction
2015-11-06 09:26:50 +01:00
system.cpu.commit.op_class_0::IntMult 144575 0.02% 97.20% # Class of committed instruction
2015-11-16 12:08:57 +01:00
system.cpu.commit.op_class_0::IntDiv 121797 0.02% 97.22% # Class of committed instruction
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction
2015-01-11 01:06:43 +01:00
system.cpu.commit.op_class_0::FloatCvt 16 0.00% 97.22% # Class of committed instruction
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::FloatMult 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction
2015-11-16 12:08:57 +01:00
system.cpu.commit.op_class_0::MemRead 13952516 1.73% 98.95% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 8421355 1.05% 100.00% # Class of committed instruction
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2015-11-16 12:08:57 +01:00
system.cpu.commit.op_class_0::total 804396566 # Class of committed instruction
system.cpu.commit.bw_lim_events 5350963 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 1279932650 # The number of ROB reads
system.cpu.rob.rob_writes 1656830555 # The number of ROB writes
system.cpu.timesIdled 287928 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 3532567 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 9839087291 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 406949634 # Number of Instructions Simulated
system.cpu.committedOps 804396566 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 1.143968 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.143968 # CPI: Total CPI of All Threads
system.cpu.ipc 0.874151 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.874151 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 1088094227 # number of integer regfile reads
system.cpu.int_regfile_writes 653527011 # number of integer regfile writes
2015-11-06 09:26:50 +01:00
system.cpu.fp_regfile_reads 154 # number of floating regfile reads
2015-11-16 12:08:57 +01:00
system.cpu.cc_regfile_reads 414885669 # number of cc regfile reads
system.cpu.cc_regfile_writes 320973068 # number of cc regfile writes
system.cpu.misc_regfile_reads 264298420 # number of misc regfile reads
2015-09-25 13:27:03 +02:00
system.cpu.misc_regfile_writes 400155 # number of misc regfile writes
2015-11-16 12:08:57 +01:00
system.cpu.dcache.tags.replacements 1656768 # number of replacements
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.tagsinuse 511.992170 # Cycle average of tags in use
2015-11-16 12:08:57 +01:00
system.cpu.dcache.tags.total_refs 18961019 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1657280 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 11.441047 # Average number of references to valid blocks.
2015-09-25 13:27:03 +02:00
system.cpu.dcache.tags.warmup_cycle 65644500 # Cycle when the warmup percentage was hit.
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.occ_blocks::cpu.data 511.992170 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999985 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999985 # Average percentage of cache occupancy
2014-01-24 22:29:33 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2015-11-16 12:08:57 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 190 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id
2014-01-24 22:29:33 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2015-11-16 12:08:57 +01:00
system.cpu.dcache.tags.tag_accesses 87666283 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 87666283 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 10818711 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 10818711 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 8076378 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 8076378 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 63033 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 63033 # number of SoftPFReq hits
system.cpu.dcache.demand_hits::cpu.data 18895089 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 18895089 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 18958122 # number of overall hits
system.cpu.dcache.overall_hits::total 18958122 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1802383 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1802383 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 335313 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 335313 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 406423 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 406423 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 2137696 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2137696 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2544119 # number of overall misses
system.cpu.dcache.overall_misses::total 2544119 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 30109912500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 30109912500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 21130469723 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 21130469723 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 51240382223 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 51240382223 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 51240382223 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 51240382223 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 12621094 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 12621094 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 8411691 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 8411691 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 469456 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 469456 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 21032785 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 21032785 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 21502241 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 21502241 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.142807 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.142807 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039863 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.039863 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.865732 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.865732 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.101636 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.101636 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.118319 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.118319 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16705.612792 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16705.612792 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63017.150313 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 63017.150313 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23969.910700 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 23969.910700 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 20140.717562 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 20140.717562 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 552645 # number of cycles access was blocked
2015-09-25 13:27:03 +02:00
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-11-16 12:08:57 +01:00
system.cpu.dcache.blocked::no_mshrs 52313 # number of cycles access was blocked
2015-09-25 13:27:03 +02:00
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
2015-11-16 12:08:57 +01:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.564200 # average number of cycles each access was blocked
2015-09-25 13:27:03 +02:00
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2011-08-15 03:34:17 +02:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
2015-11-16 12:08:57 +01:00
system.cpu.dcache.writebacks::writebacks 1559051 # number of writebacks
system.cpu.dcache.writebacks::total 1559051 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 836185 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 836185 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44844 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 44844 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 881029 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 881029 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 881029 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 881029 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 966198 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 966198 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290469 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 290469 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402930 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 402930 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1256667 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1256667 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1659597 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1659597 # number of overall MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 573460 # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total 573460 # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13902 # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total 13902 # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 587362 # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total 587362 # number of overall MSHR uncacheable misses
2015-11-16 12:08:57 +01:00
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14276500000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 14276500000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19191766223 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 19191766223 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6799993500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6799993500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33468266223 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 33468266223 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40268259723 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 40268259723 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 98146110500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 98146110500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2778958000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2778958000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100925068500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 100925068500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076554 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076554 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034532 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034532 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.858291 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.858291 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059748 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.059748 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077183 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.077183 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14775.956895 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14775.956895 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66071.650410 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66071.650410 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16876.364381 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16876.364381 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26632.565527 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26632.565527 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24263.878353 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 24263.878353 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171147.264848 # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171147.264848 # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 199896.273917 # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 199896.273917 # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171827.711871 # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171827.711871 # average overall mshr uncacheable latency
2011-08-15 03:34:17 +02:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-11-16 12:08:57 +01:00
system.cpu.dtb_walker_cache.tags.replacements 70166 # number of replacements
system.cpu.dtb_walker_cache.tags.tagsinuse 15.821895 # Cycle average of tags in use
system.cpu.dtb_walker_cache.tags.total_refs 109067 # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.sampled_refs 70181 # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.tags.avg_refs 1.554082 # Average number of references to valid blocks.
2015-11-06 09:26:50 +01:00
system.cpu.dtb_walker_cache.tags.warmup_cycle 199860126500 # Cycle when the warmup percentage was hit.
2015-11-16 12:08:57 +01:00
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.821895 # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.988868 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_percent::total 0.988868 # Average percentage of cache occupancy
2015-07-03 16:15:03 +02:00
system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
2015-11-16 12:08:57 +01:00
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
2015-07-03 16:15:03 +02:00
system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id
2015-11-16 12:08:57 +01:00
system.cpu.dtb_walker_cache.tags.tag_accesses 431964 # Number of tag accesses
system.cpu.dtb_walker_cache.tags.data_accesses 431964 # Number of data accesses
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 109068 # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total 109068 # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 109068 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total 109068 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 109068 # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total 109068 # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 71276 # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total 71276 # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 71276 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total 71276 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 71276 # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total 71276 # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 917687000 # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 917687000 # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 917687000 # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total 917687000 # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 917687000 # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total 917687000 # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 180344 # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total 180344 # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 180344 # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total 180344 # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 180344 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total 180344 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.395222 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.395222 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.395222 # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.395222 # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.395222 # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.395222 # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12875.119255 # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12875.119255 # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12875.119255 # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12875.119255 # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12875.119255 # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12875.119255 # average overall miss latency
2014-11-12 15:05:25 +01:00
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
2015-11-16 12:08:57 +01:00
system.cpu.dtb_walker_cache.writebacks::writebacks 21382 # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total 21382 # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 71276 # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 71276 # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 71276 # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total 71276 # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 71276 # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total 71276 # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 846411000 # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 846411000 # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 846411000 # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 846411000 # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 846411000 # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 846411000 # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.395222 # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.395222 # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.395222 # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.395222 # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.395222 # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.395222 # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11875.119255 # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11875.119255 # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11875.119255 # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 11875.119255 # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11875.119255 # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 11875.119255 # average overall mshr miss latency
2014-11-12 15:05:25 +01:00
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-11-16 12:08:57 +01:00
system.cpu.icache.tags.replacements 977252 # number of replacements
system.cpu.icache.tags.tagsinuse 509.169999 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 7899773 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 977764 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 8.079427 # Average number of references to valid blocks.
2015-11-06 09:26:50 +01:00
system.cpu.icache.tags.warmup_cycle 150383300500 # Cycle when the warmup percentage was hit.
2015-11-16 12:08:57 +01:00
system.cpu.icache.tags.occ_blocks::cpu.inst 509.169999 # Average occupied blocks per requestor
2015-11-06 09:26:50 +01:00
system.cpu.icache.tags.occ_percent::cpu.inst 0.994473 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.994473 # Average percentage of cache occupancy
2015-09-15 15:14:09 +02:00
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2015-11-16 12:08:57 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id
2015-09-15 15:14:09 +02:00
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2015-11-16 12:08:57 +01:00
system.cpu.icache.tags.tag_accesses 9921559 # Number of tag accesses
system.cpu.icache.tags.data_accesses 9921559 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 7899773 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 7899773 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 7899773 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 7899773 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 7899773 # number of overall hits
system.cpu.icache.overall_hits::total 7899773 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1043950 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1043950 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1043950 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1043950 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1043950 # number of overall misses
system.cpu.icache.overall_misses::total 1043950 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 15700851982 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 15700851982 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 15700851982 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 15700851982 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 15700851982 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 15700851982 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 8943723 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 8943723 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 8943723 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 8943723 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 8943723 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 8943723 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.116724 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.116724 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.116724 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.116724 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.116724 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.116724 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15039.850550 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 15039.850550 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 15039.850550 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 15039.850550 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 15039.850550 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 15039.850550 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 15298 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.cpu.icache.blocked_cycles::no_targets 183 # number of cycles access was blocked
2015-11-16 12:08:57 +01:00
system.cpu.icache.blocked::no_mshrs 490 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked
2015-11-16 12:08:57 +01:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 31.220408 # average number of cycles each access was blocked
2015-11-06 09:26:50 +01:00
system.cpu.icache.avg_blocked_cycles::no_targets 91.500000 # average number of cycles each access was blocked
2014-11-12 15:05:25 +01:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
2015-11-16 12:08:57 +01:00
system.cpu.icache.writebacks::writebacks 977252 # number of writebacks
system.cpu.icache.writebacks::total 977252 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 66114 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 66114 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 66114 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 66114 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 66114 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 66114 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 977836 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 977836 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 977836 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 977836 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 977836 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 977836 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13829997488 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 13829997488 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13829997488 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 13829997488 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13829997488 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 13829997488 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.109332 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.109332 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.109332 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.109332 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.109332 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.109332 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14143.473433 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14143.473433 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14143.473433 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 14143.473433 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14143.473433 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 14143.473433 # average overall mshr miss latency
2014-11-12 15:05:25 +01:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-11-16 12:08:57 +01:00
system.cpu.itb_walker_cache.tags.replacements 13555 # number of replacements
system.cpu.itb_walker_cache.tags.tagsinuse 6.033283 # Cycle average of tags in use
system.cpu.itb_walker_cache.tags.total_refs 24087 # Total number of references to valid blocks.
system.cpu.itb_walker_cache.tags.sampled_refs 13571 # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.tags.avg_refs 1.774888 # Average number of references to valid blocks.
2015-11-06 09:26:50 +01:00
system.cpu.itb_walker_cache.tags.warmup_cycle 5119783334000 # Cycle when the warmup percentage was hit.
2015-11-16 12:08:57 +01:00
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.033283 # Average occupied blocks per requestor
2015-11-06 09:26:50 +01:00
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.377080 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_percent::total 0.377080 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id
2015-09-25 13:27:03 +02:00
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2015-11-16 12:08:57 +01:00
system.cpu.itb_walker_cache.tags.tag_accesses 91500 # Number of tag accesses
system.cpu.itb_walker_cache.tags.data_accesses 91500 # Number of data accesses
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 24085 # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total 24085 # number of ReadReq hits
2014-11-12 15:05:25 +01:00
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
2015-11-16 12:08:57 +01:00
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 24087 # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total 24087 # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 24087 # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total 24087 # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 14442 # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total 14442 # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 14442 # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total 14442 # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 14442 # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total 14442 # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 176053500 # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total 176053500 # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 176053500 # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total 176053500 # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 176053500 # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total 176053500 # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 38527 # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total 38527 # number of ReadReq accesses(hits+misses)
2014-11-12 15:05:25 +01:00
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
2015-11-16 12:08:57 +01:00
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 38529 # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total 38529 # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 38529 # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total 38529 # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.374854 # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.374854 # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.374835 # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total 0.374835 # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.374835 # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total 0.374835 # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12190.382219 # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 12190.382219 # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12190.382219 # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 12190.382219 # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12190.382219 # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 12190.382219 # average overall miss latency
2014-11-12 15:05:25 +01:00
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
2015-11-16 12:08:57 +01:00
system.cpu.itb_walker_cache.writebacks::writebacks 2646 # number of writebacks
system.cpu.itb_walker_cache.writebacks::total 2646 # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 14442 # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 14442 # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 14442 # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total 14442 # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 14442 # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total 14442 # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 161611500 # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 161611500 # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 161611500 # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 161611500 # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 161611500 # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 161611500 # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.374854 # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.374854 # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.374835 # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.374835 # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.374835 # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.374835 # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 11190.382219 # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11190.382219 # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 11190.382219 # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 11190.382219 # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 11190.382219 # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 11190.382219 # average overall mshr miss latency
2014-11-12 15:05:25 +01:00
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-11-16 12:08:57 +01:00
system.cpu.l2cache.tags.replacements 111866 # number of replacements
system.cpu.l2cache.tags.tagsinuse 64806.585136 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 4895184 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 176146 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 27.790492 # Average number of references to valid blocks.
2014-11-12 15:05:25 +01:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-11-16 12:08:57 +01:00
system.cpu.l2cache.tags.occ_blocks::writebacks 50665.331172 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 16.461611 # Average occupied blocks per requestor
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.139358 # Average occupied blocks per requestor
2015-11-16 12:08:57 +01:00
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3133.879154 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 10990.773840 # Average occupied blocks per requestor
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.occ_percent::writebacks 0.773092 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000251 # Average percentage of cache occupancy
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047819 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.167706 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.988870 # Average percentage of cache occupancy
2015-11-16 12:08:57 +01:00
system.cpu.l2cache.tags.occ_task_id_blocks::1024 64280 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 693 # Occupied blocks per task id
2015-11-16 12:08:57 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3370 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6095 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54078 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.980835 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 43505464 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 43505464 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 1583079 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 1583079 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 976106 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 976106 # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 322 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 322 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 155501 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 155501 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 961509 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 961509 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 64508 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 12006 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1332683 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 1409197 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 64508 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 12006 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 961509 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 1488184 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2526207 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 64508 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 12006 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 961509 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 1488184 # number of overall hits
system.cpu.l2cache.overall_hits::total 2526207 # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1468 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 1468 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 132819 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 132819 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16187 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 16187 # number of ReadCleanReq misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker 64 # number of ReadSharedReq misses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker 5 # number of ReadSharedReq misses
2015-11-16 12:08:57 +01:00
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 35692 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 35761 # number of ReadSharedReq misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_misses::cpu.dtb.walker 64 # number of demand (read+write) misses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
2015-11-16 12:08:57 +01:00
system.cpu.l2cache.demand_misses::cpu.inst 16187 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 168511 # number of demand (read+write) misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_misses::total 184767 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 64 # number of overall misses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
2015-11-16 12:08:57 +01:00
system.cpu.l2cache.overall_misses::cpu.inst 16187 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 168511 # number of overall misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_misses::total 184767 # number of overall misses
2015-11-16 12:08:57 +01:00
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 60416500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 60416500 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16987025000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 16987025000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2173573500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 2173573500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.dtb.walker 9251500 # number of ReadSharedReq miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.itb.walker 665000 # number of ReadSharedReq miss cycles
2015-11-16 12:08:57 +01:00
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4801171500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 4811088000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 9251500 # number of demand (read+write) miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 665000 # number of demand (read+write) miss cycles
2015-11-16 12:08:57 +01:00
system.cpu.l2cache.demand_miss_latency::cpu.inst 2173573500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 21788196500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 23971686500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 9251500 # number of overall miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 665000 # number of overall miss cycles
2015-11-16 12:08:57 +01:00
system.cpu.l2cache.overall_miss_latency::cpu.inst 2173573500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 21788196500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 23971686500 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 1583079 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 1583079 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 976106 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 976106 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1790 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 1790 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 288320 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 288320 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 977696 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 977696 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker 64572 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker 12011 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1368375 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 1444958 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 64572 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 12011 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 977696 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1656695 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2710974 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 64572 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 12011 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 977696 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1656695 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2710974 # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.820112 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.820112 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.460665 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.460665 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.016556 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.016556 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker 0.000991 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker 0.000416 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.026083 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024749 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000991 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000416 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016556 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.101715 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.068155 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000991 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000416 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016556 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.101715 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.068155 # miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 41155.653951 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 41155.653951 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127896.046499 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127896.046499 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134278.958423 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134278.958423 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.dtb.walker 144554.687500 # average ReadSharedReq miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.itb.walker 133000 # average ReadSharedReq miss latency
2015-11-16 12:08:57 +01:00
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 134516.740446 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 134534.492883 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 144554.687500 # average overall miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 133000 # average overall miss latency
2015-11-16 12:08:57 +01:00
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134278.958423 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 129298.363312 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 129740.086163 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 144554.687500 # average overall miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 133000 # average overall miss latency
2015-11-16 12:08:57 +01:00
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134278.958423 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 129298.363312 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 129740.086163 # average overall miss latency
2014-11-12 15:05:25 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
2015-11-16 12:08:57 +01:00
system.cpu.l2cache.writebacks::writebacks 102439 # number of writebacks
system.cpu.l2cache.writebacks::total 102439 # number of writebacks
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 3 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 2 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 2 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 2 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 2 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 9 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 9 # number of CleanEvict MSHR misses
2015-11-16 12:08:57 +01:00
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1468 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 1468 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 132819 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 132819 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16184 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16184 # number of ReadCleanReq MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.dtb.walker 64 # number of ReadSharedReq MSHR misses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.itb.walker 5 # number of ReadSharedReq MSHR misses
2015-11-16 12:08:57 +01:00
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 35690 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 35759 # number of ReadSharedReq MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 64 # number of demand (read+write) MSHR misses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses
2015-11-16 12:08:57 +01:00
system.cpu.l2cache.demand_mshr_misses::cpu.inst 16184 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 168509 # number of demand (read+write) MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_mshr_misses::total 184762 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 64 # number of overall MSHR misses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses
2015-11-16 12:08:57 +01:00
system.cpu.l2cache.overall_mshr_misses::cpu.inst 16184 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 168509 # number of overall MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_mshr_misses::total 184762 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 573460 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 573460 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 13902 # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 13902 # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 587362 # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 587362 # number of overall MSHR uncacheable misses
2015-11-16 12:08:57 +01:00
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 104998500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 104998500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15658835000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15658835000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2011501500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2011501500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker 8611500 # number of ReadSharedReq MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker 615000 # number of ReadSharedReq MSHR miss cycles
2015-11-16 12:08:57 +01:00
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4444509500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4453736000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 8611500 # number of demand (read+write) MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 615000 # number of demand (read+write) MSHR miss cycles
2015-11-16 12:08:57 +01:00
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2011501500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20103344500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 22124072500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 8611500 # number of overall MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 615000 # number of overall MSHR miss cycles
2015-11-16 12:08:57 +01:00
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2011501500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20103344500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 22124072500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 90977820000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 90977820000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2619013000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2619013000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 93596833000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 93596833000 # number of overall MSHR uncacheable cycles
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2015-11-16 12:08:57 +01:00
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.820112 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.820112 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.460665 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.460665 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016553 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016553 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker 0.000991 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.000416 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026082 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024747 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000991 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000416 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016553 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101714 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.068153 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000991 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000416 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016553 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101714 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.068153 # mshr miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71524.863760 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71524.863760 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117896.046499 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117896.046499 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124289.514335 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124289.514335 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 134554.687500 # average ReadSharedReq mshr miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 123000 # average ReadSharedReq mshr miss latency
2015-11-16 12:08:57 +01:00
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124530.947044 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124548.673061 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 134554.687500 # average overall mshr miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency
2015-11-16 12:08:57 +01:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124289.514335 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 119301.310316 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 119743.629642 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 134554.687500 # average overall mshr miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency
2015-11-16 12:08:57 +01:00
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124289.514335 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 119301.310316 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 119743.629642 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 158647.194225 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158647.194225 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188391.094807 # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 188391.094807 # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159351.188875 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 159351.188875 # average overall mshr uncacheable latency
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-11-16 12:08:57 +01:00
system.cpu.toL2Bus.snoop_filter.tot_requests 5440904 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2708527 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 66581 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 1244 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1244 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.trans_dist::ReadReq 573460 # Transaction distribution
2015-11-16 12:08:57 +01:00
system.cpu.toL2Bus.trans_dist::ReadResp 3006380 # Transaction distribution
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.trans_dist::WriteReq 13902 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 13902 # Transaction distribution
2015-11-16 12:08:57 +01:00
system.cpu.toL2Bus.trans_dist::WritebackDirty 1732191 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 976106 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 117351 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 2287 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 2287 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 288332 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 288332 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 977836 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1455618 # Transaction distribution
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.trans_dist::MessageReq 1647 # Transaction distribution
system.cpu.toL2Bus.trans_dist::BadAddressError 4 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.trans_dist::InvalidateReq 46720 # Transaction distribution
2015-11-16 12:08:57 +01:00
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2931638 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6148755 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 31077 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 165763 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 9277233 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 125043328 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207521115 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 938048 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5501056 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 339003547 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 219501 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 3519248 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.019893 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.161869 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2015-11-16 12:08:57 +01:00
system.cpu.toL2Bus.snoop_fanout::0 3461036 98.35% 98.35% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 46415 1.32% 99.66% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 11797 0.34% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2015-11-16 12:08:57 +01:00
system.cpu.toL2Bus.snoop_fanout::total 3519248 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 5581428473 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
2015-11-16 12:08:57 +01:00
system.cpu.toL2Bus.snoopLayer0.occupancy 673784 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2015-11-16 12:08:57 +01:00
system.cpu.toL2Bus.respLayer0.occupancy 1468574841 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2015-11-16 12:08:57 +01:00
system.cpu.toL2Bus.respLayer1.occupancy 3067922715 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
2015-11-16 12:08:57 +01:00
system.cpu.toL2Bus.respLayer2.occupancy 21677471 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2015-11-16 12:08:57 +01:00
system.cpu.toL2Bus.respLayer3.occupancy 106983360 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.trans_dist::ReadReq 212021 # Transaction distribution
system.iobus.trans_dist::ReadResp 212021 # Transaction distribution
system.iobus.trans_dist::WriteReq 57726 # Transaction distribution
system.iobus.trans_dist::WriteResp 57726 # Transaction distribution
system.iobus.trans_dist::MessageReq 1647 # Transaction distribution
system.iobus.trans_dist::MessageResp 1647 # Transaction distribution
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 400004 # Packet count per connected master and slave (bytes)
2015-04-14 18:01:11 +02:00
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
2014-11-22 02:22:19 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
2015-01-07 09:31:09 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27824 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.iobus.pkt_count_system.bridge.master::total 444236 # Packet count per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95258 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95258 # Packet count per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3294 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3294 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 542788 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 200002 # Cumulative packet size per connected master and slave (bytes)
2015-04-14 18:01:11 +02:00
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
2014-11-22 02:22:19 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
2015-01-07 09:31:09 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13912 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.iobus.pkt_size_system.bridge.master::total 228398 # Cumulative packet size per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027816 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027816 # Cumulative packet size per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6588 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6588 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 3262802 # Cumulative packet size per connected master and slave (bytes)
2015-11-16 12:08:57 +01:00
system.iobus.reqLayer0.occupancy 3986144 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer1.occupancy 43000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer2.occupancy 6500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2015-11-16 12:08:57 +01:00
system.iobus.reqLayer3.occupancy 10452000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer4.occupancy 146500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer5.occupancy 1029000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer6.occupancy 94000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer7.occupancy 58500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer8.occupancy 32500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer9.occupancy 300003000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
2015-11-16 12:08:57 +01:00
system.iobus.reqLayer10.occupancy 1174500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer11.occupancy 212500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
2014-11-22 02:22:19 +01:00
system.iobus.reqLayer13.occupancy 2000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2015-11-16 12:08:57 +01:00
system.iobus.reqLayer14.occupancy 24568000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer16.occupancy 10000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer18.occupancy 11500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
2015-11-16 12:08:57 +01:00
system.iobus.reqLayer19.occupancy 241169809 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer20.occupancy 1085500 # Layer occupancy (ticks)
2014-11-22 02:22:19 +01:00
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.respLayer0.occupancy 433230000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.iobus.respLayer1.occupancy 50170000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.respLayer2.occupancy 1647000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.iocache.tags.replacements 47574 # number of replacements
2015-11-16 12:08:57 +01:00
system.iocache.tags.tagsinuse 0.140717 # Cycle average of tags in use
2014-11-12 15:05:25 +01:00
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
2015-09-25 13:27:03 +02:00
system.iocache.tags.sampled_refs 47590 # Sample count of references to valid blocks.
2014-11-12 15:05:25 +01:00
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
2015-11-06 09:26:50 +01:00
system.iocache.tags.warmup_cycle 4999394542000 # Cycle when the warmup percentage was hit.
2015-11-16 12:08:57 +01:00
system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.140717 # Average occupied blocks per requestor
2015-11-06 09:26:50 +01:00
system.iocache.tags.occ_percent::pc.south_bridge.ide 0.008795 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.008795 # Average percentage of cache occupancy
2014-11-12 15:05:25 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2015-09-25 13:27:03 +02:00
system.iocache.tags.tag_accesses 428661 # Number of tag accesses
system.iocache.tags.data_accesses 428661 # Number of data accesses
system.iocache.ReadReq_misses::pc.south_bridge.ide 909 # number of ReadReq misses
system.iocache.ReadReq_misses::total 909 # number of ReadReq misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses
2015-09-25 13:27:03 +02:00
system.iocache.demand_misses::pc.south_bridge.ide 909 # number of demand (read+write) misses
system.iocache.demand_misses::total 909 # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide 909 # number of overall misses
system.iocache.overall_misses::total 909 # number of overall misses
2015-11-16 12:08:57 +01:00
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 147582673 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 147582673 # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 6073068136 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 6073068136 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide 147582673 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 147582673 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide 147582673 # number of overall miss cycles
system.iocache.overall_miss_latency::total 147582673 # number of overall miss cycles
2015-09-25 13:27:03 +02:00
system.iocache.ReadReq_accesses::pc.south_bridge.ide 909 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses)
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses)
2015-09-25 13:27:03 +02:00
system.iocache.demand_accesses::pc.south_bridge.ide 909 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 909 # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide 909 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 909 # number of overall (read+write) accesses
2014-11-12 15:05:25 +01:00
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2014-11-12 15:05:25 +01:00
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2015-11-16 12:08:57 +01:00
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 162357.176018 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 162357.176018 # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 129988.615925 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 129988.615925 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 162357.176018 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 162357.176018 # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 162357.176018 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 162357.176018 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 921 # number of cycles access was blocked
2014-11-12 15:05:25 +01:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.iocache.blocked::no_mshrs 104 # number of cycles access was blocked
2014-11-12 15:05:25 +01:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2015-11-16 12:08:57 +01:00
system.iocache.avg_blocked_cycles::no_mshrs 8.855769 # average number of cycles each access was blocked
2014-11-12 15:05:25 +01:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2014-12-02 12:08:25 +01:00
system.iocache.fast_writes 0 # number of fast writes performed
2014-11-12 15:05:25 +01:00
system.iocache.cache_copies 0 # number of cache copies performed
2015-04-30 05:35:23 +02:00
system.iocache.writebacks::writebacks 46667 # number of writebacks
system.iocache.writebacks::total 46667 # number of writebacks
2015-09-25 13:27:03 +02:00
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 909 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 909 # number of ReadReq MSHR misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 46720 # number of WriteLineReq MSHR misses
2015-09-25 13:27:03 +02:00
system.iocache.demand_mshr_misses::pc.south_bridge.ide 909 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 909 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide 909 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 909 # number of overall MSHR misses
2015-11-16 12:08:57 +01:00
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 102132673 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 102132673 # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3737068136 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 3737068136 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 102132673 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 102132673 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 102132673 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 102132673 # number of overall MSHR miss cycles
2014-11-12 15:05:25 +01:00
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2014-11-12 15:05:25 +01:00
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2015-11-16 12:08:57 +01:00
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 112357.176018 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 112357.176018 # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 79988.615925 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79988.615925 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 112357.176018 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 112357.176018 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 112357.176018 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 112357.176018 # average overall mshr miss latency
2014-11-12 15:05:25 +01:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-11-06 09:26:50 +01:00
system.membus.trans_dist::ReadReq 573460 # Transaction distribution
2015-11-16 12:08:57 +01:00
system.membus.trans_dist::ReadResp 626308 # Transaction distribution
2015-11-06 09:26:50 +01:00
system.membus.trans_dist::WriteReq 13902 # Transaction distribution
system.membus.trans_dist::WriteResp 13902 # Transaction distribution
2015-11-16 12:08:57 +01:00
system.membus.trans_dist::WritebackDirty 149106 # Transaction distribution
system.membus.trans_dist::CleanEvict 9689 # Transaction distribution
system.membus.trans_dist::UpgradeReq 2235 # Transaction distribution
system.membus.trans_dist::UpgradeResp 1738 # Transaction distribution
2015-11-06 09:26:50 +01:00
system.membus.trans_dist::ReadExReq 132555 # Transaction distribution
2015-11-16 12:08:57 +01:00
system.membus.trans_dist::ReadExResp 132549 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 52852 # Transaction distribution
2015-11-06 09:26:50 +01:00
system.membus.trans_dist::MessageReq 1647 # Transaction distribution
system.membus.trans_dist::MessageResp 1647 # Transaction distribution
system.membus.trans_dist::BadAddressError 4 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution
system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution
2015-11-06 09:26:50 +01:00
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3294 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total 3294 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 444236 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 730488 # Packet count per connected master and slave (bytes)
2015-11-16 12:08:57 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 484041 # Packet count per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 8 # Packet count per connected master and slave (bytes)
2015-11-16 12:08:57 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1658773 # Packet count per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141815 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 141815 # Packet count per connected master and slave (bytes)
2015-11-16 12:08:57 +01:00
system.membus.pkt_count::total 1803882 # Packet count per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6588 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::total 6588 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 228398 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1460973 # Cumulative packet size per connected master and slave (bytes)
2015-11-16 12:08:57 +01:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18320640 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20010011 # Cumulative packet size per connected master and slave (bytes)
2015-07-03 16:15:03 +02:00
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3015040 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 3015040 # Cumulative packet size per connected master and slave (bytes)
2015-11-16 12:08:57 +01:00
system.membus.pkt_size::total 23031639 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 1655 # Total snoops (count)
system.membus.snoop_fanout::samples 982723 # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.membus.snoop_fanout::mean 1.001676 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.040904 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2015-11-16 12:08:57 +01:00
system.membus.snoop_fanout::1 981076 99.83% 99.83% # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.membus.snoop_fanout::2 1647 0.17% 100.00% # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
2015-05-05 09:22:39 +02:00
system.membus.snoop_fanout::max_value 2 # Request fanout histogram
2015-11-16 12:08:57 +01:00
system.membus.snoop_fanout::total 982723 # Request fanout histogram
system.membus.reqLayer0.occupancy 338949500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2015-11-16 12:08:57 +01:00
system.membus.reqLayer1.occupancy 369068500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
2015-11-16 12:08:57 +01:00
system.membus.reqLayer2.occupancy 3985856 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
2015-11-16 12:08:57 +01:00
system.membus.reqLayer3.occupancy 1013663510 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.membus.reqLayer4.occupancy 5500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
2015-11-16 12:08:57 +01:00
system.membus.respLayer0.occupancy 2338856 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
2015-11-16 12:08:57 +01:00
system.membus.respLayer2.occupancy 2140705292 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
2015-11-16 12:08:57 +01:00
system.membus.respLayer4.occupancy 85841188 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
2015-09-15 15:14:09 +02:00
system.pc.south_bridge.ide.disks0.dma_read_txs 29 # Number of DMA read transactions (not PRD).
2014-11-12 15:05:25 +01:00
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
2011-08-15 03:34:17 +02:00
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
