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gem5/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt

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X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
---------- Begin Simulation Statistics ----------
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
sim_seconds 5.184733 # Number of seconds simulated
sim_ticks 5184732721500 # Number of ticks simulated
final_tick 5184732721500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
host_inst_rate 808289 # Simulator instruction rate (inst/s)
host_op_rate 1558079 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 32570584041 # Simulator tick rate (ticks/s)
host_mem_usage 654268 # Number of bytes of host memory used
host_seconds 159.18 # Real time elapsed on the host
sim_insts 128667033 # Number of instructions simulated
sim_ops 248022101 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.bytes_read::cpu.inst 825344 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9044928 # Number of bytes read from this memory
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.bytes_read::total 9898944 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 825344 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 825344 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 8133056 # Number of bytes written to this memory
system.physmem.bytes_written::total 8133056 # Number of bytes written to this memory
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.num_reads::cpu.inst 12896 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 141327 # Number of read requests responded to by this memory
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.num_reads::total 154671 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 127079 # Number of write requests responded to by this memory
system.physmem.num_writes::total 127079 # Number of write requests responded to by this memory
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.bw_read::cpu.inst 159187 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1744531 # Total read bandwidth from this memory (bytes/s)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.bw_read::pc.south_bridge.ide 5468 # Total read bandwidth from this memory (bytes/s)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.bw_read::total 1909249 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 159187 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 159187 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1568655 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1568655 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1568655 # Total bandwidth to/from this memory (bytes/s)
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.bw_total::cpu.inst 159187 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1744531 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.bw_total::pc.south_bridge.ide 5468 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.bw_total::total 3477903 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 154671 # Number of read requests accepted
system.physmem.writeReqs 127079 # Number of write requests accepted
system.physmem.readBursts 154671 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 127079 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 9888768 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 10176 # Total number of bytes read from write queue
system.physmem.bytesWritten 8131392 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 9898944 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 8133056 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 159 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 48348 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 9772 # Per bank write bursts
system.physmem.perBankRdBursts::1 9412 # Per bank write bursts
system.physmem.perBankRdBursts::2 9829 # Per bank write bursts
system.physmem.perBankRdBursts::3 9622 # Per bank write bursts
system.physmem.perBankRdBursts::4 9563 # Per bank write bursts
system.physmem.perBankRdBursts::5 9355 # Per bank write bursts
system.physmem.perBankRdBursts::6 9720 # Per bank write bursts
system.physmem.perBankRdBursts::7 9664 # Per bank write bursts
system.physmem.perBankRdBursts::8 9219 # Per bank write bursts
system.physmem.perBankRdBursts::9 9313 # Per bank write bursts
system.physmem.perBankRdBursts::10 9431 # Per bank write bursts
system.physmem.perBankRdBursts::11 9415 # Per bank write bursts
system.physmem.perBankRdBursts::12 9985 # Per bank write bursts
system.physmem.perBankRdBursts::13 10194 # Per bank write bursts
system.physmem.perBankRdBursts::14 10163 # Per bank write bursts
system.physmem.perBankRdBursts::15 9855 # Per bank write bursts
system.physmem.perBankWrBursts::0 8316 # Per bank write bursts
system.physmem.perBankWrBursts::1 7960 # Per bank write bursts
system.physmem.perBankWrBursts::2 8144 # Per bank write bursts
system.physmem.perBankWrBursts::3 8236 # Per bank write bursts
system.physmem.perBankWrBursts::4 8504 # Per bank write bursts
system.physmem.perBankWrBursts::5 7731 # Per bank write bursts
system.physmem.perBankWrBursts::6 7974 # Per bank write bursts
system.physmem.perBankWrBursts::7 7835 # Per bank write bursts
system.physmem.perBankWrBursts::8 7118 # Per bank write bursts
system.physmem.perBankWrBursts::9 7555 # Per bank write bursts
system.physmem.perBankWrBursts::10 7609 # Per bank write bursts
system.physmem.perBankWrBursts::11 7637 # Per bank write bursts
system.physmem.perBankWrBursts::12 8092 # Per bank write bursts
system.physmem.perBankWrBursts::13 8095 # Per bank write bursts
system.physmem.perBankWrBursts::14 8240 # Per bank write bursts
system.physmem.perBankWrBursts::15 8007 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.numWrRetry 3 # Number of times write queue was full causing retry
system.physmem.totGap 5184732588500 # Total gap between requests
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.readPktSize::6 154671 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.writePktSize::6 127079 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 151205 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 2887 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 48 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 40 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 33 # What read queue length does an incoming req see
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.rdQLenPdf::7 35 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 30 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.wrQLenPdf::15 2360 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 2863 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 6760 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 6764 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 6407 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 6343 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 6364 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 8198 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 8634 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 10421 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 9012 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 8283 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 7047 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 7628 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 7472 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 6195 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 6206 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 6107 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 234 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 187 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 258 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 145 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 184 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 176 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 206 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 206 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 193 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 126 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 134 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 112 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 157 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 188 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 176 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 142 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 163 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 117 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 136 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 145 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 114 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 95 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 132 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 82 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 57 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 36 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 28 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 39 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 16 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 55882 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 322.466912 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 190.971568 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 335.231986 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 19566 35.01% 35.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 13855 24.79% 59.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 5752 10.29% 70.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3280 5.87% 75.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2436 4.36% 80.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1597 2.86% 83.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1106 1.98% 85.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 958 1.71% 86.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 7332 13.12% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 55882 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 5902 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 26.177906 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 623.301246 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 5901 99.98% 99.98% # Reads before turning the bus around for writes
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.rdPerTurnAround::total 5902 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 5902 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 21.527109 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 19.363013 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 14.814592 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 4841 82.02% 82.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 49 0.83% 82.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 261 4.42% 87.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 70 1.19% 88.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 69 1.17% 89.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 251 4.25% 93.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 22 0.37% 94.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 13 0.22% 94.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 15 0.25% 94.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 5 0.08% 94.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 7 0.12% 94.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 5 0.08% 95.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 235 3.98% 99.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 3 0.05% 99.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 5 0.08% 99.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 8 0.14% 99.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 1 0.02% 99.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 2 0.03% 99.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 2 0.03% 99.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 1 0.02% 99.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 27 0.46% 99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151 2 0.03% 99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155 1 0.02% 99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163 1 0.02% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167 3 0.05% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179 1 0.02% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-203 1 0.02% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::204-207 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 5902 # Writes before turning the bus around for reads
system.physmem.totQLat 1454171981 # Total ticks spent queuing
system.physmem.totMemAccLat 4351271981 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 772560000 # Total ticks spent in databus transfers
system.physmem.avgQLat 9411.39 # Average queueing delay per DRAM burst
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.avgMemAccLat 28161.39 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1.91 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1.91 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.57 # Average system write bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.busUtil 0.03 # Data bus utilization in percentage
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.avgWrQLen 24.52 # Average write queue length when enqueuing
system.physmem.readRowHits 126926 # Number of row buffer hits during reads
system.physmem.writeRowHits 98756 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.15 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 77.71 # Row buffer hit rate for writes
system.physmem.avgGap 18401890.29 # Average gap between requests
system.physmem.pageHitRate 80.15 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 207522000 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 113231250 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 600100800 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 419256000 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 338641458480 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 134001495225 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 2993293881750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 3467276945505 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.747605 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 4979520185732 # Time in different power states
system.physmem_0.memoryStateTime::REF 173129580000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem_0.memoryStateTime::ACT 32082834268 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem_1.actEnergy 214945920 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 117282000 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 605085000 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 404047440 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 338641458480 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 134530881300 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 2992829508000 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 3467343208140 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.760386 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 4978746411720 # Time in different power states
system.physmem_1.memoryStateTime::REF 173129580000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem_1.memoryStateTime::ACT 32855777030 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.numCycles 10369465443 # number of cpu cycles simulated
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.committedInsts 128667033 # Number of instructions committed
system.cpu.committedOps 248022101 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 232599125 # Number of integer alu accesses
stats: changes due to recent changesets.
2015-01-11 01:06:43 +01:00
system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.num_func_calls 2317363 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 23194478 # number of instructions that are conditional controls
system.cpu.num_int_insts 232599125 # number of integer instructions
stats: changes due to recent changesets.
2015-01-11 01:06:43 +01:00
system.cpu.num_fp_insts 48 # number of float instructions
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.num_int_register_reads 435753384 # number of times the integer registers were read
system.cpu.num_int_register_writes 198362025 # number of times the integer registers were written
stats: changes due to recent changesets.
2015-01-11 01:06:43 +01:00
system.cpu.num_fp_register_reads 48 # number of times the floating registers were read
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.num_cc_register_reads 133133176 # number of times the CC registers were read
system.cpu.num_cc_register_writes 95670461 # number of times the CC registers were written
system.cpu.num_mem_refs 22356642 # number of memory refs
system.cpu.num_load_insts 13946240 # Number of load instructions
system.cpu.num_store_insts 8410402 # Number of store instructions
system.cpu.num_idle_cycles 9769457503.998116 # Number of idle cycles
system.cpu.num_busy_cycles 600007939.001884 # Number of busy cycles
system.cpu.not_idle_fraction 0.057863 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.942137 # Percentage of idle cycles
system.cpu.Branches 26370667 # Number of branches fetched
system.cpu.op_class::No_OpClass 172538 0.07% 0.07% # Class of executed instruction
system.cpu.op_class::IntAlu 225235379 90.81% 90.88% # Class of executed instruction
system.cpu.op_class::IntMult 140393 0.06% 90.94% # Class of executed instruction
system.cpu.op_class::IntDiv 123647 0.05% 90.99% # Class of executed instruction
stats: changes due to recent changesets.
2015-01-11 01:06:43 +01:00
system.cpu.op_class::FloatAdd 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::FloatCvt 16 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 90.99% # Class of executed instruction
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.op_class::MemRead 13941273 5.62% 96.61% # Class of executed instruction
system.cpu.op_class::MemWrite 8410402 3.39% 100.00% # Class of executed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.op_class::total 248023648 # Class of executed instruction
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dcache.tags.replacements 1621027 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.996962 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 20151381 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1621539 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 12.427318 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 54359500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.996962 # Average occupied blocks per requestor
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dcache.tags.tag_accesses 88751069 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 88751069 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 12012436 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 12012436 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 8077606 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 8077606 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 59170 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 59170 # number of SoftPFReq hits
system.cpu.dcache.demand_hits::cpu.data 20090042 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 20090042 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 20149212 # number of overall hits
system.cpu.dcache.overall_hits::total 20149212 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 905821 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 905821 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 324802 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 324802 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 402538 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 402538 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 1230623 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1230623 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1633161 # number of overall misses
system.cpu.dcache.overall_misses::total 1633161 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 12812474000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 12812474000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 12127378479 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 12127378479 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 24939852479 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 24939852479 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 24939852479 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 24939852479 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 12918257 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 12918257 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 8402408 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 8402408 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 461708 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 461708 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 21320665 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 21320665 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 21782373 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 21782373 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070119 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.070119 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038656 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.038656 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.871845 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.871845 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.057720 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.057720 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.074976 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.074976 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14144.598105 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14144.598105 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37337.758016 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 37337.758016 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 20266.037998 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 20266.037998 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15270.908673 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 15270.908673 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 5798 # number of cycles access was blocked
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dcache.blocked::no_mshrs 72 # number of cycles access was blocked
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 80.527778 # average number of cycles each access was blocked
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dcache.writebacks::writebacks 1537873 # number of writebacks
system.cpu.dcache.writebacks::total 1537873 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 288 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 288 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9093 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 9093 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 9381 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 9381 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 9381 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 9381 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 905533 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 905533 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315709 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 315709 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402504 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 402504 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1221242 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1221242 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1623746 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1623746 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 572954 # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total 572954 # number of ReadReq MSHR uncacheable
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13916 # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total 13916 # number of WriteReq MSHR uncacheable
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 586870 # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total 586870 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11904745500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 11904745500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11312729479 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 11312729479 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5814985000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5814985000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23217474979 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 23217474979 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29032459979 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 29032459979 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94684333500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94684333500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2622247500 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2622247500 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 97306581000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 97306581000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070097 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070097 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037574 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037574 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871772 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871772 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057280 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.057280 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074544 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.074544 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13146.672181 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13146.672181 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35832.774736 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35832.774736 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14447.024129 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14447.024129 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19011.363005 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19011.363005 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17879.927020 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17879.927020 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 165256.431581 # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 165256.431581 # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188433.996838 # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188433.996838 # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 165806.023480 # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 165806.023480 # average overall mshr uncacheable latency
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dtb_walker_cache.tags.replacements 7782 # number of replacements
system.cpu.dtb_walker_cache.tags.tagsinuse 5.044171 # Cycle average of tags in use
system.cpu.dtb_walker_cache.tags.total_refs 13071 # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.sampled_refs 7797 # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.tags.avg_refs 1.676414 # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.warmup_cycle 5158049844500 # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.044171 # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315261 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315261 # Average percentage of cache occupancy
stats: changes due to recent changesets.
2015-01-11 01:06:43 +01:00
system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
stats: changes due to recent changesets.
2015-01-11 01:06:43 +01:00
system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dtb_walker_cache.tags.tag_accesses 53116 # Number of tag accesses
system.cpu.dtb_walker_cache.tags.data_accesses 53116 # Number of data accesses
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13073 # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total 13073 # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13073 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total 13073 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13073 # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total 13073 # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8990 # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total 8990 # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8990 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total 8990 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8990 # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total 8990 # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 97324000 # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 97324000 # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 97324000 # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total 97324000 # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 97324000 # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total 97324000 # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22063 # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total 22063 # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22063 # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total 22063 # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22063 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total 22063 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.407470 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.407470 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.407470 # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.407470 # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.407470 # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.407470 # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10825.806452 # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10825.806452 # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10825.806452 # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10825.806452 # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10825.806452 # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10825.806452 # average overall miss latency
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dtb_walker_cache.writebacks::writebacks 3106 # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total 3106 # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8990 # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8990 # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8990 # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total 8990 # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8990 # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total 8990 # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 88334000 # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 88334000 # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 88334000 # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 88334000 # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 88334000 # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 88334000 # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.407470 # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.407470 # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.407470 # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.407470 # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.407470 # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.407470 # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 9825.806452 # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9825.806452 # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 9825.806452 # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 9825.806452 # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 9825.806452 # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 9825.806452 # average overall mshr miss latency
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.icache.tags.replacements 792637 # number of replacements
system.cpu.icache.tags.tagsinuse 510.330403 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 144952019 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 793149 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 182.755093 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 161555480500 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 510.330403 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.996739 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.996739 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 289 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.icache.tags.tag_accesses 146538331 # Number of tag accesses
system.cpu.icache.tags.data_accesses 146538331 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 144952019 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 144952019 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 144952019 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 144952019 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 144952019 # number of overall hits
system.cpu.icache.overall_hits::total 144952019 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 793156 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 793156 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 793156 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 793156 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 793156 # number of overall misses
system.cpu.icache.overall_misses::total 793156 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 11221653000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 11221653000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 11221653000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 11221653000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 11221653000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 11221653000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 145745175 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 145745175 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 145745175 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 145745175 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 145745175 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 145745175 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005442 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.005442 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.005442 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.005442 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.005442 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.005442 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14148.103274 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14148.103274 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14148.103274 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14148.103274 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14148.103274 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14148.103274 # average overall miss latency
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 793156 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 793156 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 793156 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 793156 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 793156 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 793156 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10428497000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 10428497000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10428497000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 10428497000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10428497000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 10428497000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005442 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005442 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005442 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.005442 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005442 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.005442 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13148.103274 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13148.103274 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13148.103274 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 13148.103274 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13148.103274 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13148.103274 # average overall mshr miss latency
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.itb_walker_cache.tags.replacements 3538 # number of replacements
system.cpu.itb_walker_cache.tags.tagsinuse 3.060279 # Cycle average of tags in use
system.cpu.itb_walker_cache.tags.total_refs 7930 # Total number of references to valid blocks.
system.cpu.itb_walker_cache.tags.sampled_refs 3549 # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.tags.avg_refs 2.234432 # Average number of references to valid blocks.
system.cpu.itb_walker_cache.tags.warmup_cycle 5161245744500 # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.060279 # Average occupied blocks per requestor
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191267 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_percent::total 0.191267 # Average percentage of cache occupancy
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 11 # Occupied blocks per task id
stats: changes due to recent changesets.
2015-01-11 01:06:43 +01:00
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.687500 # Percentage of cache occupancy per task id
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.itb_walker_cache.tags.tag_accesses 29062 # Number of tag accesses
system.cpu.itb_walker_cache.tags.data_accesses 29062 # Number of data accesses
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7929 # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total 7929 # number of ReadReq hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7931 # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total 7931 # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7931 # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total 7931 # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4400 # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total 4400 # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4400 # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total 4400 # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4400 # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total 4400 # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 45407000 # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total 45407000 # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 45407000 # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total 45407000 # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 45407000 # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total 45407000 # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12329 # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total 12329 # number of ReadReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12331 # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total 12331 # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12331 # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total 12331 # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.356882 # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.356882 # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.356824 # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total 0.356824 # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.356824 # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total 0.356824 # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10319.772727 # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10319.772727 # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10319.772727 # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10319.772727 # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10319.772727 # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10319.772727 # average overall miss latency
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.itb_walker_cache.writebacks::writebacks 796 # number of writebacks
system.cpu.itb_walker_cache.writebacks::total 796 # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4400 # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4400 # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4400 # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total 4400 # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4400 # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total 4400 # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 41007000 # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 41007000 # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 41007000 # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 41007000 # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 41007000 # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 41007000 # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.356882 # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.356882 # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.356824 # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.356824 # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.356824 # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.356824 # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9319.772727 # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9319.772727 # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9319.772727 # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9319.772727 # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9319.772727 # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9319.772727 # average overall mshr miss latency
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.tags.replacements 87263 # number of replacements
system.cpu.l2cache.tags.tagsinuse 64757.225173 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 4369524 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 151965 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 28.753489 # Average number of references to valid blocks.
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.tags.occ_blocks::writebacks 50419.617435 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.145028 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3328.329800 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 11009.132909 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.769342 # Average percentage of cache occupancy
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.050786 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.167986 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.988117 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 64702 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2890 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5302 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56392 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987274 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 39224493 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 39224493 # Number of data accesses
system.cpu.l2cache.Writeback_hits::writebacks 1541775 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 1541775 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 307 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 307 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 199754 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 199754 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 780246 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 780246 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 6724 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 3018 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1278797 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 1288539 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 6724 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 3018 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 780246 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 1478551 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2268539 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 6724 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 3018 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 780246 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 1478551 # number of overall hits
system.cpu.l2cache.overall_hits::total 2268539 # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1367 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 1367 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 113781 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 113781 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 12897 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 12897 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker 5 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 28476 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 28481 # number of ReadSharedReq misses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.demand_misses::cpu.inst 12897 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 142257 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 155159 # number of demand (read+write) misses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.overall_misses::cpu.inst 12897 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 142257 # number of overall misses
system.cpu.l2cache.overall_misses::total 155159 # number of overall misses
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 21508500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 21508500 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8694302000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 8694302000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1043096500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 1043096500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.itb.walker 401500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2328492500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 2328894000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 401500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 1043096500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 11022794500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 12066292500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 401500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 1043096500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 11022794500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 12066292500 # number of overall miss cycles
system.cpu.l2cache.Writeback_accesses::writebacks 1541775 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 1541775 # number of Writeback accesses(hits+misses)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1674 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 1674 # number of UpgradeReq accesses(hits+misses)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 313535 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 313535 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 793143 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 793143 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker 6724 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker 3023 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1307273 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 1317020 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6724 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 3023 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 793143 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1620808 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2423698 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6724 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 3023 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 793143 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1620808 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2423698 # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.816607 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.816607 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.362897 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.362897 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.016261 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.016261 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker 0.001654 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.021783 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.021625 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001654 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016261 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.087769 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.064017 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001654 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016261 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.087769 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.064017 # miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15734.089247 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15734.089247 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76412.599643 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76412.599643 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80879.002869 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80879.002869 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.itb.walker 80300 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81770.350471 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81770.092342 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 80300 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80879.002869 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77485.076306 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 77767.274215 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 80300 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80879.002869 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77485.076306 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 77767.274215 # average overall miss latency
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.writebacks::writebacks 80412 # number of writebacks
system.cpu.l2cache.writebacks::total 80412 # number of writebacks
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 30 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 30 # number of CleanEvict MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1367 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 1367 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113781 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 113781 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 12897 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 12897 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.itb.walker 5 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 28476 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 28481 # number of ReadSharedReq MSHR misses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.demand_mshr_misses::cpu.inst 12897 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 142257 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 155159 # number of demand (read+write) MSHR misses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.overall_mshr_misses::cpu.inst 12897 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 142257 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 155159 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 572954 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 572954 # number of ReadReq MSHR uncacheable
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 13916 # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 13916 # number of WriteReq MSHR uncacheable
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 586870 # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 586870 # number of overall MSHR uncacheable misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29036000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29036000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7556492000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7556492000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 914126500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 914126500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker 351500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2043732500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2044084000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 351500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 914126500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9600224500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 10514702500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 351500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 914126500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9600224500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 10514702500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 87522404500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 87522404500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2462213500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2462213500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89984618000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89984618000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.816607 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.816607 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362897 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362897 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016261 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016261 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.001654 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.021783 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.021625 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001654 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016261 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087769 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.064017 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001654 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016261 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087769 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.064017 # mshr miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21240.673007 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21240.673007 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66412.599643 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66412.599643 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70879.002869 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70879.002869 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 70300 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71770.350471 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71770.092342 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 70300 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70879.002869 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67485.076306 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67767.274215 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 70300 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70879.002869 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67485.076306 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67767.274215 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 152756.424600 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 152756.424600 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 176933.996838 # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176933.996838 # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 153329.728901 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 153329.728901 # average overall mshr uncacheable latency
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.trans_dist::ReadReq 572954 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 2687857 # Transaction distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.toL2Bus.trans_dist::WriteReq 13916 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 13916 # Transaction distribution
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.trans_dist::Writeback 1668857 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 884964 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 2182 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 2182 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 313540 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 313540 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 793156 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1322272 # Transaction distribution
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.toL2Bus.trans_dist::MessageReq 1652 # Transaction distribution
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.trans_dist::InvalidateReq 46720 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2378925 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6040657 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8974 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 20226 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 8448782 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50761152 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203819691 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 244416 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 629120 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 255454379 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 189246 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 5626152 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 3.032703 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.177859 # Request fanout histogram
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.snoop_fanout::3 5442159 96.73% 96.73% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4 183993 3.27% 100.00% # Request fanout histogram
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.snoop_fanout::total 5626152 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 4269812500 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.snoopLayer0.occupancy 480000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.respLayer0.occupancy 1189734000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.respLayer1.occupancy 3013374987 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.respLayer2.occupancy 6600000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.respLayer3.occupancy 13485000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.trans_dist::ReadReq 226549 # Transaction distribution
system.iobus.trans_dist::ReadResp 226549 # Transaction distribution
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iobus.trans_dist::WriteReq 57726 # Transaction distribution
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.trans_dist::WriteResp 57726 # Transaction distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.trans_dist::MessageReq 1652 # Transaction distribution
system.iobus.trans_dist::MessageResp 1652 # Transaction distribution
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 429188 # Packet count per connected master and slave (bytes)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
x86: Update stats for the new Linux delay port.
2014-11-22 02:22:19 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27824 # Packet count per connected master and slave (bytes)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.pkt_count_system.bridge.master::total 473420 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95130 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95130 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3304 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3304 # Packet count per connected master and slave (bytes)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.pkt_count::total 571854 # Packet count per connected master and slave (bytes)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 214594 # Cumulative packet size per connected master and slave (bytes)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
x86: Update stats for the new Linux delay port.
2014-11-22 02:22:19 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13912 # Cumulative packet size per connected master and slave (bytes)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.pkt_size_system.bridge.master::total 242990 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027304 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027304 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6608 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6608 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.pkt_size::total 3276902 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 3939784 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 8813000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 77000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.reqLayer9.occupancy 214595000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
x86: Update stats for the new Linux delay port.
2014-11-22 02:22:19 +01:00
system.iobus.reqLayer13.occupancy 2000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
stats: x86: Update stats for the CPUID change.
2015-01-07 09:31:09 +01:00
system.iobus.reqLayer14.occupancy 20815000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
x86: Update stats for the new Linux delay port.
2014-11-22 02:22:19 +01:00
system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
x86: Update stats for the new Linux delay port.
2014-11-22 02:22:19 +01:00
system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.reqLayer19.occupancy 242362178 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
x86: Update stats for the new Linux delay port.
2014-11-22 02:22:19 +01:00
system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.respLayer0.occupancy 462414000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.respLayer1.occupancy 50042000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.respLayer2.occupancy 1652000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.tags.replacements 47510 # number of replacements
system.iocache.tags.tagsinuse 0.095938 # Cycle average of tags in use
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.tags.sampled_refs 47526 # Sample count of references to valid blocks.
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.tags.warmup_cycle 5046145075000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.095938 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005996 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.005996 # Average percentage of cache occupancy
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.tags.tag_accesses 428085 # Number of tag accesses
system.iocache.tags.data_accesses 428085 # Number of data accesses
system.iocache.ReadReq_misses::pc.south_bridge.ide 845 # number of ReadReq misses
system.iocache.ReadReq_misses::total 845 # number of ReadReq misses
system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses
system.iocache.demand_misses::pc.south_bridge.ide 845 # number of demand (read+write) misses
system.iocache.demand_misses::total 845 # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide 845 # number of overall misses
system.iocache.overall_misses::total 845 # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 134017694 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 134017694 # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 5509470484 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 5509470484 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide 134017694 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 134017694 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide 134017694 # number of overall miss cycles
system.iocache.overall_miss_latency::total 134017694 # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide 845 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 845 # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide 845 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 845 # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide 845 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 845 # number of overall (read+write) accesses
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158600.821302 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 158600.821302 # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 117925.310017 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 117925.310017 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 158600.821302 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 158600.821302 # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 158600.821302 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 158600.821302 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 341 # number of cycles access was blocked
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.blocked::no_mshrs 28 # number of cycles access was blocked
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.avg_blocked_cycles::no_mshrs 12.178571 # average number of cycles each access was blocked
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.fast_writes 0 # number of fast writes performed
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.cache_copies 0 # number of cache copies performed
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.iocache.writebacks::writebacks 46667 # number of writebacks
system.iocache.writebacks::total 46667 # number of writebacks
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 845 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 845 # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 46720 # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide 845 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 845 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide 845 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 845 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 91767694 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 91767694 # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3173470484 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 3173470484 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 91767694 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 91767694 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 91767694 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 91767694 # number of overall MSHR miss cycles
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 108600.821302 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 108600.821302 # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 67925.310017 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67925.310017 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 108600.821302 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 108600.821302 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 108600.821302 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 108600.821302 # average overall mshr miss latency
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.trans_dist::ReadReq 572954 # Transaction distribution
system.membus.trans_dist::ReadResp 615177 # Transaction distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.trans_dist::WriteReq 13916 # Transaction distribution
system.membus.trans_dist::WriteResp 13916 # Transaction distribution
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.trans_dist::Writeback 127079 # Transaction distribution
system.membus.trans_dist::CleanEvict 7222 # Transaction distribution
system.membus.trans_dist::UpgradeReq 2154 # Transaction distribution
system.membus.trans_dist::UpgradeResp 1646 # Transaction distribution
system.membus.trans_dist::ReadExReq 113502 # Transaction distribution
system.membus.trans_dist::ReadExResp 113502 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 42223 # Transaction distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.trans_dist::MessageReq 1652 # Transaction distribution
system.membus.trans_dist::MessageResp 1652 # Transaction distribution
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution
system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3304 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total 3304 # Packet count per connected master and slave (bytes)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 473420 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 700320 # Packet count per connected master and slave (bytes)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 400152 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1573892 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141767 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 141767 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1718963 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6608 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::total 6608 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 242990 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1400637 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15016960 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16660587 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3015040 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 3015040 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 19682235 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 1580 # Total snoops (count)
system.membus.snoop_fanout::samples 927896 # Request fanout histogram
system.membus.snoop_fanout::mean 1.001780 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.042157 # Request fanout histogram
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.snoop_fanout::1 926244 99.82% 99.82% # Request fanout histogram
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.membus.snoop_fanout::2 1652 0.18% 100.00% # Request fanout histogram
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.membus.snoop_fanout::max_value 2 # Request fanout histogram
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.snoop_fanout::total 927896 # Request fanout histogram
system.membus.reqLayer0.occupancy 359896000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.reqLayer1.occupancy 527973000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.reqLayer2.occupancy 3304000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.reqLayer3.occupancy 848970266 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.respLayer0.occupancy 1652000 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.respLayer2.occupancy 2157850870 # Layer occupancy (ticks)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.respLayer4.occupancy 85904679 # Layer occupancy (ticks)
x86: Update the stats for the x86 FS o3 boot test.
2014-11-17 09:16:36 +01:00
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink