Commit graph

902 commits

Author SHA1 Message Date
Korey Sewell
b49511ae48 inorder: timing for inst forwarding
when insts execute, they mark the time they finish to be used for subsequent isnts
they may need forwarding of data. However, the regdepmap was using the wrong
value to index into the destination operands of the instruction to be forwarded.
Thus, in some cases, we are checking to see if the 3rd destination register
for an instruction is executed at a certain time, when there is only 1 dest. register
valid. Thus, we get a bad, uninitialized time value that will stall forwarding
causing performance loss but still the correct execution.
2010-04-10 23:31:36 -04:00
Nathan Binkert
141f61d83a ruby: get rid of gems_common/util.hh and .cc and use stuff in src/base 2010-04-02 11:20:32 -07:00
Nathan Binkert
f1c3f3044b ruby: get "using namespace" out of headers
In addition to obvious changes, this required a slight change to the slicc
grammar to allow types with :: in them.  Otherwise slicc barfs on std::string
which we need for the headers that slicc generates.
2010-04-02 11:20:32 -07:00
Nathan Binkert
60ae1d2b10 style: cleanup the Ruby Tester 2010-03-29 20:39:02 -04:00
Korey Sewell
1c98bc5a56 m5: merge inorder updates 2010-03-27 02:23:00 -04:00
Korey Sewell
ac316d45e8 inorder: write-hints bug fix
make sure to only read 1 src reg. for write-hint and any other similar
'store' instruction. Reading the source reg when its not necessary
can cause the simulator to read from uninitialized values
2010-03-27 01:40:05 -04:00
Timothy M. Jones
6b293c73fd CPU: Added comments to address translation classes. 2010-03-25 12:43:52 +00:00
Steve Reinhardt
f066bfc2f5 cpu: get rid of uncached access "events"
These recordEvent() calls could cause crashes since they
access the req pointer after it's potentially been
deleted during a failed translation call.  (Similar
problem to the traceData bug fixed in the previous cset.)

Moving them above the translation call (as was done
recentlyi in cset 8b2b8e5e7d35) avoids the crash
but doesn't work, since at that point we don't know if
the access is uncached or not.

It's not clear why these calls are there, and no one
seems to use them, so we'll just delete them.  If they
are needed, they should be moved to somewhere that's
guaranteed to be after the translation completes but
before the request is possibly deleted, e.g., in
finishTranslation().
2010-03-23 08:50:59 -07:00
Steve Reinhardt
4d77ea7a57 cpu: fix exec tracing memory corruption bug
Accessing traceData (to call setAddress() and/or setData())
after initiating a timing translation was causing crashes,
since a failed translation could delete the traceData
object before returning.

It turns out that there was never a need to access traceData
after initiating the translation, as the traced data was
always available earlier; this ordering was merely
historical.  Furthermore, traceData->setAddress() and
traceData->setData() were being called both from the CPU
model and the ISA definition, often redundantly.

This patch standardizes all setAddress and setData calls
for memory instructions to be in the CPU models and not
in the ISA definition.  It also moves those calls above
the translation calls to eliminate the crashes.
2010-03-23 08:50:57 -07:00
Korey Sewell
2620e08722 inorder: import name for addtl. bpred stats 2010-03-22 17:19:48 -04:00
Maximilien Breughe
0170e851de inorder: fix squash bug in branch predictor 2010-03-22 16:59:12 -04:00
Korey Sewell
4ac245737d inorder: fix address list bug 2010-03-22 15:38:28 -04:00
Brad Beckmann
4ee3b0da45 TimingSimpleCPU: Fixed uncacacheable request read bug
Previously the recording of an uncached read occurred after the request was
possibly deleted within the translateTiming function.
2010-03-21 21:22:20 -07:00
Nathan Binkert
140785d24c ruby: get rid of std-includes.hh
Do not use "using namespace std;" in headers
Include header files as needed
2010-03-10 18:33:11 -08:00
Nathan Binkert
f0b4259e98 cpu_models: get rid of cpu_models.py and move the stuff into SCons 2010-02-26 18:14:48 -08:00
Timothy M. Jones
a5feaa6a69 BaseDynInst: Preserve the faults returned from read and write.
When implementing timing address translations instead of atomic, I
forgot to preserve the faults that are returned from the read and
write calls.  This patch reinstates them.
2010-02-20 20:11:58 +00:00
Timothy M. Jones
29e8bcead5 O3PCU: Split loads and stores that cross cache line boundaries.
When each load or store is sent to the LSQ, we check whether it will cross a
cache line boundary and, if so, split it in two. This creates two TLB
translations and two memory requests. Care has to be taken if the first
packet of a split load is sent but the second blocks the cache. Similarly,
for a store, if the first packet cannot be sent, we must store the second
one somewhere to retry later.

This modifies the LSQSenderState class to record both packets in a split
load or store.

Finally, a new const variable, HasUnalignedMemAcc, is added to each ISA
to indicate whether unaligned memory accesses are allowed. This is used
throughout the changed code so that compiler can optimise away code dealing
with split requests for ISAs that don't need them.
2010-02-12 19:53:20 +00:00
Timothy M. Jones
7fe9f92cfc BaseDynInst: Make the TLB translation timing instead of atomic.
This initiates a timing translation and passes the read or write on to the
processor before waiting for it to finish. Once the translation is finished,
the instruction's state is updated via the 'finish' function. A new
DataTranslation class is created to handle this.

The idea is taken from the implementation of timing translations in
TimingSimpleCPU by Gabe Black. This patch also separates out the timing
translations from this CPU and uses the new DataTranslation class.
2010-02-12 19:53:19 +00:00
Korey Sewell
c7f6e2661c inorder: double delete inst bug
Make sure that instructions are dereferenced/deleted twice by marking they are
on the remove list
2010-01-31 18:30:59 -05:00
Korey Sewell
9357e353fc inorder: inst count mgmt 2010-01-31 18:30:48 -05:00
Korey Sewell
be6724f7e7 inorder: implement split stores 2010-01-31 18:30:43 -05:00
Korey Sewell
6939482c49 inorder: implement split loads 2010-01-31 18:30:35 -05:00
Korey Sewell
ea8909925f inorder: add activity stats 2010-01-31 18:30:24 -05:00
Korey Sewell
f3bc2df663 inorder: object cleanup in destructors 2010-01-31 18:30:08 -05:00
Korey Sewell
1a89e8f4cb inorder: user per-thread dummy insts/reqs 2010-01-31 18:29:59 -05:00
Korey Sewell
002f1b8b7e inorder: add execution unit stats 2010-01-31 18:29:49 -05:00
Korey Sewell
82c5a754e6 inorder: recvRetry bug fix
- on certain retry requests you can get an assertion failure
- fix by allowing the request to literally "Retry" itself
  if it wasnt successful before, and then block any requests
  through cache port while waiting for the cache to be
  made available for access
2010-01-31 18:29:18 -05:00
Korey Sewell
349d86c0e4 inorder-stats: add prereq to basic stat
only show requests processed when the resource is actually in use
2010-01-31 18:29:06 -05:00
Korey Sewell
0b29c2d057 inorder: ctxt switch stats
- m5 line enforcement on use_def.cc,hh
2010-01-31 18:28:59 -05:00
Korey Sewell
ffa9ecb1fa inorder: pipeline stage stats
add idle/run/utilization stats for each pipeline stage
2010-01-31 18:28:51 -05:00
Korey Sewell
4d749472e3 inorder: enforce stage bandwidth
each stage keeps track of insts_processed on a per_thread basis but we should
be keeping that on a total basis inorder to enforce stage width limits
2010-01-31 18:28:31 -05:00
Korey Sewell
b4e0ef7837 inorder: set thread status'
set Active/Suspended/Halted status for threads.  useful for system when determining
if/when to exit simulation
2010-01-31 18:28:12 -05:00
Korey Sewell
5e0b8337ed inorder: add/remove halt/deallocate context respectively
Halt is called from the exit() system call while
deallocate is unused. So to clear up things, just
use halt and remove deallocate.
2010-01-31 18:28:05 -05:00
Korey Sewell
069b38c0d5 inorder: track last branch committed
when threads are switching in/out the CPU, we need to keep
track of special cases like branches. Add appropriate
variables in ThreadState t track this and then use
these variables when updating pc after context switch
2010-01-31 18:27:58 -05:00
Korey Sewell
aacc5cb205 inorder: add updatePC event to resPool
this will be used for when a thread comes back from a cache miss, it needs to update the PCs
because the inst might of been a branch or delayslot in which the next PC isnt always
a straight addition
2010-01-31 18:27:49 -05:00
Korey Sewell
90d3b45a56 inorder: ready thread wakeup
allow a thread to wakeup and be activated after
it has been in suspended state and another
thread is switched out. Need to give
pipeline stages a "activateThread" function
so that can get to their suspended instruction
when the time is right.
2010-01-31 18:27:38 -05:00
Korey Sewell
3eb04b4ad7 inorder: add threadmodel flag
this prints out messages relative to what
threading model is being used (smt, switch-on-miss, single, etc.)
2010-01-31 18:27:25 -05:00
Korey Sewell
611a8642c2 inorder: mem. mgmt. update
update address List and address Map to take
into account multiple threads
2010-01-31 18:27:12 -05:00
Korey Sewell
4dbc2f1718 inorder: suspend in respool
give resources their own specific
activity to do for a "suspend" event
instead of defaulting to deactivating the thread for a
suspend thread event. This really matters
for the fetch sequence unit which wants to remove the
thread from fetching while other units want to
ignore a thread suspension. If you deactivate a thread
in a resource then you may lose some of the allotted
bandwidth that the thread is taking up...
2010-01-31 18:27:02 -05:00
Korey Sewell
4ea296e296 inorder: fetch thread bug
dont check total # of threads but instead all
active threads
2010-01-31 18:26:54 -05:00
Korey Sewell
96b493d315 inorder: ready/suspend status fns
update/add in the use of isThreadReady & isThreadSuspended
functions.Check in activateThread what list a thread is
on so it can be managed accordingly.
2010-01-31 18:26:47 -05:00
Korey Sewell
d9eaa2fe21 inorder-cleanup: remove unused thread functions 2010-01-31 18:26:40 -05:00
Korey Sewell
e1fcc64980 inorder: activate thread on cache miss
-Support ability to activate next ready thread after a cache miss
through the activateNextReadyContext/Thread() functions
-To support this a "readyList" of thread ids is added
-After a cache miss, thread will suspend and then call
activitynextreadythread
2010-01-31 18:26:32 -05:00
Korey Sewell
4a945aab19 inorder: add event priority offset
allow for events to schedule themselves later if desired. this is important
because of cases like where you need to activate a thread only after the previous
thread has been deactivated. The ordering there has to be enforced
2010-01-31 18:26:26 -05:00
Korey Sewell
eac5eac67a inorder: squash on memory stall
add code to recognize memory stalls in resources and the pipeline as well
as squash a thread if there is a stall and we are in the switch on cache miss
model
2010-01-31 18:26:13 -05:00
Korey Sewell
d8e0935af2 inorder: add insts to cpu event
some events are going to need instruction data when they process, so just
include the instruction in the event construction
2010-01-31 18:26:03 -05:00
Korey Sewell
e8312ab6f7 inorder: switch out buffer
add buffer for instructions to switch out to in a pipeline stage
can't squash the instruction and remove the pipeline so we kind of need
to 'suspend' an instruction at the stage while the memory stall resolves
for the switch on cache miss model
2010-01-31 18:25:48 -05:00
Korey Sewell
a892af7b26 inorder: dont allow early loads
- loads were happening on same cycle as the address was generated which is slightly
unrealistic. Instead, force address generation to be on separate cycle from load
initiation
- also, mark the stages in a more traditional way (F-D-X-M-W)
2010-01-31 18:25:27 -05:00
Korey Sewell
0e96798fe0 configs/inorder: add options for switch-on-miss to inorder cpu 2010-01-31 18:25:13 -05:00
Korey Sewell
7b3b362ba5 inorder: init internal debug cpu counters
- cpuEventNum
- resReqCount
2010-01-31 17:18:15 -05:00
Brad Beckmann
45230a4f6b ruby: added the GEMS ruby tester 2010-01-29 20:29:23 -08:00
Lisa Hsu
9f63548478 since totalInstructions() is impl'ed by all the cpus, make it an abstract base class. 2010-01-12 10:22:46 -08:00
Brad Beckmann
b5d2052fa0 m5: Fixed bug in atomic cpu destructor 2009-11-18 13:55:58 -08:00
Gabe Black
b8120f6c38 Mem: Eliminate the NO_FAULT request flag. 2009-11-10 21:10:18 -08:00
Nathan Binkert
2c5fe6f95e build: fix compile problems pointed out by gcc 4.4 2009-11-04 16:57:01 -08:00
Steve Reinhardt
fbfe92b5b8 o3: get rid of unused physmem pointer 2009-11-04 14:23:25 -08:00
Timothy M. Jones
835a55e7f3 POWER: Add support for the Power ISA
This adds support for the 32-bit, big endian Power ISA. This supports both
integer and floating point instructions based on the Power ISA Book I v2.06.
2009-10-27 09:24:39 -07:00
Gabe Black
010b13c937 ISA: Fix compilation. 2009-10-17 01:13:41 -07:00
Brad Beckmann
28204b2a96 fixed MC146818 checkpointing bug and added isa serialization calls to simple_thread 2009-10-15 15:15:24 -07:00
Korey Sewell
f09f84da6e inorder-debug: print out workload 2009-10-01 09:35:06 -04:00
Lisa Hsu
1290a5f340 commit Soumyaroop's bug catch about max_insts_all_threads 2009-09-29 18:03:10 -04:00
Steve Reinhardt
4bec4702e9 O3: Add flag to control whether faulting instructions are traced.
When enabled, faulting instructions appear in the trace twice
(once when they fault and again when they're re-executed).
This flag is set by the Exec compound flag for backwards compatibility.
2009-09-26 10:50:50 -07:00
Steve Reinhardt
f28ea7a6c9 O3: Mark fetch stage as active if it faults.
Otherwise if the rest of the pipeline is idle then
fault will never propagate to commit to be handled,
causing CPU to deadlock.
2009-09-26 10:50:50 -07:00
Korey Sewell
25d1f2728a inorder-debug: fix cpu tick debug message 2009-09-25 11:18:55 -04:00
Nathan Binkert
d9f39c8ce7 arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh 2009-09-23 08:34:21 -07:00
Nathan Binkert
9a8cb7db7e python: Move more code into m5.util allow SCons to use that code.
Get rid of misc.py and just stick misc things in __init__.py
Move utility functions out of SCons files and into m5.util
Move utility type stuff from m5/__init__.py to m5/util/__init__.py
Remove buildEnv from m5 and allow access only from m5.defines
Rename AddToPath to addToPath while we're moving it to m5.util
Rename read_command to readCommand while we're moving it
Rename compare_versions to compareVersions while we're moving it.

--HG--
rename : src/python/m5/convert.py => src/python/m5/util/convert.py
rename : src/python/m5/smartdict.py => src/python/m5/util/smartdict.py
2009-09-22 15:24:16 -07:00
Korey Sewell
6f7e196113 inorder-mdu: multiplier latency fix
mdu was workign incorrectly for 4+ latency due to incorrectly assuming
multiply was finished the next stage
2009-09-17 15:45:27 -04:00
Soumyaroop Roy
83eebe0464 inorder-smt: remove hardcoded values
allows for the 2T hello world example to work in inorder model
2009-09-16 09:47:38 -04:00
Korey Sewell
badb2382a8 inorder-alpha-fs: edit inorder model to compile FS mode 2009-09-15 01:44:48 -04:00
Polina Dudnik
ca0e0c3683 SCons fix to always make MemTest object 2009-09-01 10:38:25 -05:00
Gabe Black
ce63e50364 Atomic CPU: Respect the NO_ACCESS request flag. 2009-08-23 14:15:15 -07:00
Steve Reinhardt
a13a706a20 Fix setting of INST_FETCH flag for O3 CPU.
It's still broken in inorder.
Also enhance DPRINTFs in cache and physical memory so we
can see more easily whether it's getting set or not.
2009-08-01 22:50:14 -07:00
Gabe Black
2871a13ab3 Simple CPU: Make the simple CPU handle the IntRegs trace flag. 2009-07-29 00:15:26 -07:00
Gabe Black
8ec235c7b1 ARM: Make native trace print out what instruction caused an error. 2009-07-27 00:54:09 -07:00
Korey Sewell
44f80e7ca5 o3-smt: enforce numThreads parameter for SMT SE mode 2009-07-25 00:50:27 -04:00
Gabe Black
3e8e813218 CPU: Separate out native trace into ISA (in)dependent code and SimObjects.
--HG--
rename : src/cpu/nativetrace.cc => src/arch/sparc/nativetrace.cc
rename : src/cpu/nativetrace.hh => src/arch/sparc/nativetrace.hh
rename : src/cpu/NativeTrace.py => src/arch/x86/X86NativeTrace.py
2009-07-19 23:54:56 -07:00
Gabe Black
c9a27d85b9 Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions. 2009-07-08 23:02:22 -07:00
Gabe Black
b398b8ff1b Registers: Add a registers.hh file as an ISA switched header.
This file is for register indices, Num* constants, and register types.
copyRegs and copyMiscRegs were moved to utility.hh and utility.cc.

--HG--
rename : src/arch/alpha/regfile.hh => src/arch/alpha/registers.hh
rename : src/arch/arm/regfile.hh => src/arch/arm/registers.hh
rename : src/arch/mips/regfile.hh => src/arch/mips/registers.hh
rename : src/arch/sparc/regfile.hh => src/arch/sparc/registers.hh
rename : src/arch/x86/regfile.hh => src/arch/x86/registers.hh
2009-07-08 23:02:21 -07:00
Gabe Black
5c37d10624 Registers: Eliminate the ISA defined RegFile class. 2009-07-08 23:02:21 -07:00
Gabe Black
43345bff6c Registers: Move the PCs out of the ISAs and into the CPUs. 2009-07-08 23:02:21 -07:00
Gabe Black
1b29f1621d ARM, Simple CPU: Fix an index and add assert checks. 2009-07-08 23:02:21 -07:00
Gabe Black
a480ba00b9 Registers: Eliminate the ISA defined integer register file. 2009-07-08 23:02:20 -07:00
Gabe Black
0cb180ea0d Registers: Eliminate the ISA defined floating point register file. 2009-07-08 23:02:20 -07:00
Gabe Black
25884a8773 Registers: Get rid of the float register width parameter. 2009-07-08 23:02:20 -07:00
Gabe Black
32daf6fc3f Registers: Add an ISA object which replaces the MiscRegFile.
This object encapsulates (or will eventually) the identity and characteristics
of the ISA in the CPU.
2009-07-08 23:02:20 -07:00
Nathan Binkert
6faf377b53 types: clean up types, especially signed vs unsigned 2009-06-04 23:21:12 -07:00
Nathan Binkert
4e34266245 move: put predictor includes and cc files into the same place
--HG--
rename : src/cpu/2bit_local_pred.cc => src/cpu/pred/2bit_local.cc
rename : src/cpu/o3/2bit_local_pred.hh => src/cpu/pred/2bit_local.hh
rename : src/cpu/btb.cc => src/cpu/pred/btb.cc
rename : src/cpu/o3/btb.hh => src/cpu/pred/btb.hh
rename : src/cpu/ras.cc => src/cpu/pred/ras.cc
rename : src/cpu/o3/ras.hh => src/cpu/pred/ras.hh
rename : src/cpu/tournament_pred.cc => src/cpu/pred/tournament.cc
rename : src/cpu/o3/tournament_pred.hh => src/cpu/pred/tournament.hh
2009-06-04 21:50:20 -07:00
Nathan Binkert
47877cf2db types: add a type for thread IDs and try to use it everywhere 2009-05-26 09:23:13 -07:00
Nathan Binkert
8d2e51c7f5 includes: sort includes again 2009-05-17 14:34:52 -07:00
Nathan Binkert
eef3a2e142 types: Move stuff for global types into src/base/types.hh
--HG--
rename : src/sim/host.hh => src/base/types.hh
2009-05-17 14:34:50 -07:00
Korey Sewell
a032d91016 cpus: add InOrderCPU to default build
regressions need this so they build the model
2009-05-12 20:55:21 -04:00
Korey Sewell
6c88730540 inorder-resources: delete events
make sure unrecognized events in the resource pool are deleted and also delete resource events in destructor
2009-05-12 15:01:16 -04:00
Korey Sewell
db2b721380 inorder-tlb-cunit: merge the TLB as implicit to any memory access
TLBUnit no longer used and we also get rid of memAccSize and memAccFlags functions added to ISA and StaticInst
since TLB is not a separate resource to acquire. Instead, TLB access is done before any read/write to memory
and the result is checked before it's sent out to memory.
* * *
2009-05-12 15:01:16 -04:00
Korey Sewell
3a057bdbb1 inorder-tlb: squash insts in TLB correctly
TLB had a bug where if it was stalled and waiting , it would not squash all instructions older than squashed instruction correctly
* * *
2009-05-12 15:01:16 -04:00
Korey Sewell
f1c97e830b inorder-faults: ignore unalign translation faults for prefetches 2009-05-12 15:01:16 -04:00
Korey Sewell
fe4cd9847d inorder-stc: update interface to handle store conditionals 2009-05-12 15:01:15 -04:00
Korey Sewell
6211fe5d2e inorder-float: Fix storage of FP results
inorder was incorrectly storing FP values and confusing the integer/fp storage view of floating point operations. A big issue was knowing trying to infer when were doing single or double precision access
because this lets you know the size of value to store (32-64 bits). This isnt exactly straightforward since alpha uses all 64-bit regs while mips/sparc uses a dual-reg view. by getting this value from
the actual floating point register file, the model can figure out what it needs to store
2009-05-12 15:01:15 -04:00
Korey Sewell
3603dd25ef inorder-fetch: update model to use predecoder 2009-05-12 15:01:15 -04:00
Korey Sewell
c9a03f549b inorder-mem: clean up allocation/deletion of requests/packets
* * *
2009-05-12 15:01:15 -04:00
Korey Sewell
1c7e988272 inorder-mem: skeleton support for prefetch/writehints 2009-05-12 15:01:15 -04:00