Commit graph

7393 commits

Author SHA1 Message Date
Michael LeBeane
6e4c51fa99 dev: Add a DmaCallback class to DmaDevice
This patch introduces the DmaCallback helper class, which registers a callback
to fire after a sequence of (potentially non-contiguous) DMA transfers on a
DmaPort completes.
2016-09-13 23:14:24 -04:00
Michael LeBeane
f17a5faf44 sim, syscall_emul: Add mmap to EmulatedDriver
Add support for calling mmap on an EmulatedDriver file descriptor.
2016-09-13 23:12:46 -04:00
Michael LeBeane
6a668d0c0c gpu-compute: Fix bug with return in cfg
Connecting basic blocks would stop too early in kernels where ret was not the
last instruction.  This patch allows basic blocks after the ret instruction
to be properly connected.
2016-09-13 23:11:20 -04:00
Michael LeBeane
febab25957 dev: Exit correctly in dist-gem5
The receiver thread in dist_iface is allowed to directly exit the simulation.
This can cause exit to be called twice if the main thread simultaneously wants
to exit the simulation.  Therefore, have the receiver thread enqueue a request
to exit on the primary event queue for the main simulation thread to handle.
2016-09-13 23:08:34 -04:00
Michael LeBeane
cc58148fe1 misc: Remove FullSystem check for networking components
Ethernet devices are currently only hooked up if running in FS mode.  Much of
the Ethernet networking code is generic and can be used to build non-Ethernet
device models.  Some of these device models do not require a complex driver
stack and can be built to use an EmulatedDriver in SE mode. This patch enables
etherent interfaces to properly connect regardless of whether the simulation
is in FS or SE mode.
2016-09-13 23:06:32 -04:00
Matt Poremba
4c903d0412 base: Output all AddrRange parameters to config.ini
Currently only 'start' and 'end' of AddrRange are printed in config.ini.
This causes address ranges to be overlapping when loading a c++-only
config with interleaved addresses using CxxConfigManger. This patch adds
prints for the interleave and XOR bits to config.ini such that address
ranges are properly setup with cxx config.
2016-09-13 23:06:18 -04:00
Andreas Sandberg
3329de1e86 dev, arm: Add a customizable NoMali GPU model
Add a customizable NoMali GPU model and an example Mali T760
configuration. Unlike the normal NoMali model (NoMaliGpu), the
NoMaliCustopmGpu model exposes all the important GPU ID registers to
Python. This makes it possible to implement custom GPU configurations
by without changing the underlying NoMali library.

Change-Id: I4fdba05844c3589893aa1a4c11dc376ec33d4e9e
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
2016-09-06 10:22:38 +01:00
David Hashe
f3ccaab1e9 cpu, mem, sim: Change how KVM maps memory
Only map memories into the KVM guest address space that are
marked as usable by KVM. Create BackingStoreEntry class
containing flags for is_conf_reported, in_addr_map, and
kvm_map.
2016-08-22 11:41:05 -04:00
Andreas Sandberg
d80a613990 dev: Revert 0a316996de76 [dev, sim: Added missing override...]
This changeset reverts the changset "dev, sim: Added missing override
keywords to fix CLANG compilation (OSX)" which was incorrectly rebased.

Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-08-16 10:59:15 +01:00
Andreas Sandberg
2c05f5207d cpu: Add missing override in Minor's exec context
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-08-15 12:00:37 +01:00
Reiley Jeapaul
ff8257c7c2 cpu: Fixed clang errors. Added 'override' keyword for virtual functions.
Change-Id: Ic37311443ca11ee6d95bceffea599e054e7aa110
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-08-15 12:00:36 +01:00
Nikos Nikoleris
25ce5db3a3 mem: Print an MSHR without triggering any assertions
Previously printing an mshr would trigger an assertion if the MSHR was
not in service or if the targets list was empty. This patch changes
the print function to bypasses the accessor functions for
postInvalidate and postDowngrade and avoid the relevant assertions. It
also checks if the targets list is empty before calling print on it.

Change-Id: Ic18bee6cb088f63976112eba40e89501237cfe62
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-08-15 12:00:36 +01:00
Matteo Andreozzi
4c494965ab dev, sim: Added missing override keywords to fix CLANG compilation (OSX)
Change-Id: Ice5fa11e77d06576eaa42149f5fa340a769d8b01
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-08-15 12:00:35 +01:00
Nikos Nikoleris
698767e538 cpu, arch: fix the type used for the request flags
Change-Id: I183b9942929c873c3272ce6d1abd4ebc472c7132
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-08-15 12:00:35 +01:00
Nikos Nikoleris
ee7d8fdcb2 mem: Add support for secure packets in the snoop filter
Secure and non-secure data can coexist in the cache and therefore the
snoop filter should treat differently packets with secure and non
secure accesses. This patch uses the lower bits of the line address to
keep track of whether the packet is addressing secure memory or not.

Change-Id: I54a5e614dad566a5083582bede86c86896f2c2c1
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com>
Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>
2016-08-12 14:11:45 +01:00
Andreas Hansson
080d4e08d6 mem: Add snoop filter to SystemXBar by default
This patch changes the default behaviour of the SystemXBar, adding a
snoop filter. With the recent updates to the snoop filter allocation
behaviour this change no longer causes problems for the regressions
without caches.

Change-Id: Ibe0cd437b71b2ede9002384126553679acc69cc1
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>
2016-08-12 14:11:45 +01:00
Andreas Hansson
a23e914519 mem: Use FromCache attribute in snoop filter allocation
This patch improves the snoop filter allocation decisions by not only
looking at whether a port is snooping or not, but also if the packet
actually came from a cache. The issue with only looking at isSnooping
is that the CPU ports, for example, are snooping, but not actually
caching. Previously we ended up incorrectly allocating entries in
systems without caches (such as the atomic and timing quick
regressions). Eventually these misguided allocations caused the snoop
filter to panic due to an excessive size.

On the request path we now include the fromCache check on the packet
itself, and for responses we check if we actually have a snoop-filter
entry.

Change-Id: Idd2dbc4f00c7e07d331e9a02658aee30d0350d7e
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com>
Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>
2016-08-12 14:11:45 +01:00
Andreas Hansson
721efa4d09 mem: Update mostly exclusive policy even further
This patch takes yet another step in maintaining the clusivity, in
that it allows a mostly-inclusive cache to hold on to blocks even when
responding to a ReadExReq or UpgradeReq. Previously the cache simply
invalidated these blocks, but there is no strict need to do so.

The most important part of this patch is that we simply mark the block
clean when satisfying the upstream request where the cache is allowed
to keep the block. The only tricky part of the patch is in the memory
management of deferred snoops, where we need to distinguish the cases
where only the packet was copied (we expected to respond), and the
cases where we created an entirely new packet and request (we kept it
only to replay later).

The code in satisfyRequest is definitely ready for some refactoring
after this.

Change-Id: I201ddc7b2582eaa46fb8cff0c7ad09e02d64b0fc
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>
2016-08-12 14:11:45 +01:00
Andreas Hansson
94f94fbc55 mem: Update mostly exclusive cache policy to cover more cases
This patch changes how the mostly exclusive policy is enforced to
ensure that we drop blocks when we should. As part of this change, the
actual invalidation due to the clusivity enforcement is moved outside
the hit handling, to a separate method maintainClusivity. For the
timing mode that means we can deal with all MSHR targets before taking
any action and possibly dropping the block. The method
satisfyCpuSideRequest is also renamed satisfyRequest as part of this
change (since we only ever see requests from the cpu-side port).

Change-Id: If6f3d1e0c3e7be9a67b72a55e4fc2ec4a90fd3d2
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>
2016-08-12 14:11:45 +01:00
Andreas Hansson
2509553403 mem: Add a FromCache packet attribute
This patch adds a FromCache attribute to the packet, and updates a
number of the existing request commands to reflect that the request
originates from a cache. The attribute simplifies checking if a
requests came from a cache or not, and this is used by both the cache
and snoop filter in follow-on patches.

Change-Id: Ib0a7a080bbe4d6036ddd84b46fd45bc7eb41cd8f
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Steve Reinhardt <stever@gmail.com>
2016-08-12 14:11:45 +01:00
Andreas Sandberg
f540f1a230 arm, dev: Add support for listing DMA ports in new platforms
When using a Ruby memory system, the Ruby configuration scripts expect
to get a list of DMA ports to create the necessary DMA sequencers. Add
support in the utility functions that wire up devices to append DMA
ports to a list instead of connecting them to the IO bus. These
functions are currently only used by the VExpress_GEM5_V1 platform.

Change-Id: I46059e46b0f69e7be5f267e396811bd3caa3ed63
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Brad Beckmann <brad.beckmann@amd.com>
2016-08-10 15:27:26 +01:00
Andreas Sandberg
26dc0017d2 ruby: Implement support for functional accesses to PIO ranges
There are cases where we want to put boot ROMs on the PIO bus. Ruby
currently doesn't support functional accesses to such memories since
functional accesses are always assumed to go to physical memory. Add
the required support for routing functional accesses to the PIO bus.

Change-Id: Ia5b0fcbe87b9642bfd6ff98a55f71909d1a804e3
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brad Beckmann <brad.beckmann@amd.com>
Reviewed-by: Michael LeBeane <michael.lebeane@amd.com>
2016-08-10 15:27:13 +01:00
Andreas Sandberg
38d34ecf0d arm: Don't report the boot ROM as a memory in config tables
The boot ROM shouldn't be used as a memory by the kernel. Memories
have a flag to indicate this which is set for some platforms. Update
all platforms to consistently set this flag to indicate that the boot
ROM shouldn't be reported as normal memory.

Change-Id: I2bf0273e99d2a668e4e8d59f535c1910c745aa7b
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Brad Beckmann <brad.beckmann@amd.com>

--HG--
extra : amend_source : c2cbda38636ea37cbe9ae6977a06b923eab5ba56
2016-08-10 14:49:11 +01:00
Tony Gutierrez
fa5e64987e sim: fix issues with pwrite(); don't enable fstatfs
this patch fixes issues with changeset 11593

use the host's pwrite() syscall for pwrite64Func(),
as opposed to pwrite64(), because pwrite64() does
not work well on all distros.

undo the enabling of fstatfs, as we will add this
in a separate pate.
2016-08-05 17:15:19 -04:00
Tony Gutierrez
0b68475b10 x86, sim: add some syscalls to X86
this patch adds an implementation for the pwrite64 syscall and
enables it for x86_64, and enables fstatfs for x86_64.
2016-08-04 12:32:21 -04:00
Curtis Dunham
ba09d8ac92 arm: s/ctx_id/ctx/ the GIC
Factored out of the larger banked register change.

Change-Id: I947dbdb9c00b4678bea9d4f77b913b7014208690
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-08-02 13:35:47 +01:00
Curtis Dunham
fc8fd0fd18 arm: bank GIC registers per CPU
Updated according to GICv2 documentation.

Change-Id: I5d926d1abf665eecc43ff0f7d6e561e1ee1c390a
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-08-02 13:35:45 +01:00
Curtis Dunham
8b3434a4f2 arm: refactor page table walking
Introduce and use a lookup table.

Using fetchDescriptor() rather than DMA cleanly handles nested paging.

Change-Id: I69ec762f176bd752ba1040890e731826b58d15a6
2016-08-02 10:38:03 +01:00
Dylan Johnson
09218ed397 arm: warn not fail on use of missing miscreg CNTHCTL_EL2
During host bootup, KVM reads/writes to CNTHCTL_EL2. Because this
miscreg has not been implemented, the simulation would end there. This
patch causes the simulation to warn about the read/write instead of fail.

Change-Id: If034bfd0818a9a5e50c5fe86609e945258c96fa3
2016-08-02 10:38:03 +01:00
Dylan Johnson
c15711725d arm: Check TLB stage 2 permissions in AArch64
This fixes a bug where stage 2 lookups used the AArch32
permissions rules even if we were executing in AArch64 mode.

Change-Id: Ia40758f0599667ca7ca15268bd3bf051342c24c1
2016-08-02 10:38:03 +01:00
Dylan Johnson
bce923c189 arm: correctly assign faulting IPA's to HPFAR_EL2
This patch corrects IPA reporting if the translation faults in a
stage 2 lookup.

Change-Id: I0b914527f8a9f98a5e980a131cf9d03e5584b4e9
2016-08-02 10:38:03 +01:00
Dylan Johnson
4d5d47c173 arm: Add TLBI instruction for stage 2 IPA's
This patch adds support for stage 2 TLBI instructions
such as TLBI IPAS2E1_Xt.

Change-Id: I0cd5e8055b0c1003e03439aa5183252f50ea0a88
2016-08-02 10:38:03 +01:00
Dylan Johnson
89511856fe arm: Fix stage 2 memory attribute checking in AArch64
Change-Id: I14c93a5460550051a12129e792a9a9bd522a145c
2016-08-02 10:38:03 +01:00
Dylan Johnson
02fcca9b6f arm: Fix trapping to Hypervisor during MSR/MRS read/write
This patch restricts trapping to hypervisor only if we are in the
correct exception level for the trap to happen.

Change-Id: I0a382b6a572ef835ea36d2702b8a81b633bd3df0
2016-08-02 10:38:03 +01:00
Dylan Johnson
c2271e301d arm: Fix secure state checking in various places
Faults that could potentially be routed to the hypervisor checked
whether or not they were in a secure state without checking if security
was enabled or not. This caused faults not to be routed correctly. This
patch causes secure state checking to first ask if security is enabled.

Change-Id: I179e9b181b27f552734c9bab2b18d05ac579a119
2016-08-02 10:38:02 +01:00
Dylan Johnson
996c1ed33c arm: Fix stage 2 determination in table walker
We recompute if we are doing a stage 2 walk inside of the table walker
but we have already figured it out in the tlb. Pass the information in
to the walk instead of recomputing it.

Change-Id: I39637ce99309b2ddbc30344d45ac9ebf6a203401
2016-08-02 10:38:02 +01:00
Dylan Johnson
eac27759e7 arm: Refactor aarch64 table walk logic to remove redundancy
The functional case is already handled within the fetchDescriptor()
function. We can thus use that function for both atomic and functional
mode when we start the table walk.

Change-Id: Iacaed28cd9024d259fd37a58150efd00ff94d86e
2016-08-02 10:38:02 +01:00
Dylan Johnson
f9a6f68e0b arm: Add check to fault routing for hypervisor/virtualization
This patch adds the option for faults to be routed to the hypervisor
using the pre-existing routeToHyp() functions that are present in each
fault type.

Change-Id: I9735512c094457636b9870456a5be5432288e004
2016-08-02 10:38:02 +01:00
Dylan Johnson
fc6879097b arm: Fix EL perceived at TLB for address translation instructions
During address translation instructions (such as AT S1E1R_Xt) the exception
level can be different than the current exception level. This patch fixes
how the TLB determines what EL to use during these instructions.

Change-Id: Ia9ce229404de9e284bc1f7479fd2c580efd55f8f
2016-08-02 10:38:02 +01:00
Dylan Johnson
2950a95672 arm: Add AArch64 hypervisor call instruction 'hvc'
This patch adds the AArch64 instruction hvc which raises an exception
from EL1 into EL2. The host OS uses this instruction to world switch
into the guest.

Change-Id: I930ee43f4f0abd4b35a68eb2a72e44e3ea6570be
2016-08-02 10:38:02 +01:00
Dylan Johnson
c53a57f74f arm: add stage2 translation support
Change-Id: I8f7c09c7ec3a97149ebebf4b21471b244e6cecc1
2016-08-02 10:38:02 +01:00
Curtis Dunham
49538a7118 arm: enable EL2 support
Change-Id: I59fa4fae98c33d9e5c2185382e1411911d27d341
2016-08-02 10:38:01 +01:00
Dylan Johnson
4fbf40daab arm: invalidate TLB miscreg cache on modification of HSCTLR
Change-Id: I5212c91c56435fe008950ed99feacc6921609226
2016-08-02 10:38:01 +01:00
Dylan Johnson
e727a0eeaa arm: change instruction classes to catch hyp traps
Change-Id: I122918d0e3dfd01ae1a4ca4f19240a069115c8b7
2016-08-02 10:38:01 +01:00
Mitch Hayenga
752f1c1fe9 cpu: Fix Minor SMT WFI/drain interaction issues
The behavior of WFI is to cause minor to cease evaluating
pipeline logic until an interrupt is observed, however
a user may wish to drain the system while a core is sleeping
due to a WFI.  This patch makes WFI drain.  If an actual
drain occurs during a WFI, the CPU is already drained and will
immediately be ready for swapping, checkpointing, etc.  This
should not negatively impact performance as WFI instructions
are 'stream-changing' (treated like unpredicted branches), so
all remaining instructions are wrong-path and will be squashed
rapidly.

Change-Id: I63833d5acb53d8dde78f9f0c9611de0ece385e45
2016-07-21 17:19:16 +01:00
Mitch Hayenga
ff4009ac00 cpu: Add SMT support to MinorCPU
This patch adds SMT support to the MinorCPU.  Currently
RoundRobin or Random thread scheduling are supported.

Change-Id: I91faf39ff881af5918cca05051829fc6261f20e3
2016-07-21 17:19:16 +01:00
Mitch Hayenga
8a476d387c isa: Modify get/check interrupt routines
Make it so that getInterrupt *always* returns an interrupt if
checkInterrupts() returns true.  This fixes/simplifies handling
of interrupts on the SMT FS CPUs (currently minor).
2016-07-21 17:19:15 +01:00
David Guillen Fandos
d25b58036a base: Add total() to Vector2D stat
This patch adds a total() function to the Vector2D
stat type. Similar to other stats such as Scalar or
Vector it is useful to be able to read the total for
a given stat.
2016-07-21 17:19:15 +01:00
David Guillen Fandos
0020662459 mem: Add snoop traffic statistic 2016-07-21 17:19:14 +01:00
Mohammad Alian
c7bf0e9cdd dev, dist: Fixed a scheduling bug in the etherswitch
This patch fixes a bug in etherswitch. When a packet gets inserted
in the output fifo, the txEvent has to always be reschedule,
not only when an event is already scheduled. This can raise
the assertion in the reschedule function.
2016-07-19 09:48:56 -05:00
Andreas Sandberg
e9d0f6db88 base: Fix inverted check in ELF .text size warning 2016-07-11 16:30:35 +01:00
Andreas Sandberg
f471cc22f0 arm: Don't consult the TLB test iface for functional translations
Don't consult the TLB test interface for PA's returned by functional
translations by the AT instruction. We implement this by chaning the
ISA code to synthesize 0-length functional reads for the TLB lookup.
The TLB then bypasses the final PA check in the tester if the size is
zero.

Change-Id: I2487b7f829cea88c37e229e9fc7a4543aced961b
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2016-07-11 10:39:56 +01:00
Andreas Sandberg
30cae3c213 base: Convert ELF .text size check assertion to a warning
The ELF loader currently has an assertion that checks if the size of a
loaded .text secion is non-zero. This is useful in the general case as
an empty text section normally indicates that there is something
strange with the ELF file. However, asserting isn't very useful. This
changeset converts the assert into a warning that tells the user that
something strange is happening.

Change-Id: I313e17847b50a0eca00f6bd00a54c610d626c0f0
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2016-07-11 10:39:30 +01:00
Nikos Nikoleris
f4cc3a4d20 mem: Remove stale argument from a DPRINTF in the cache code
Change-Id: I70dd11c23b45dfc606ef08233d2e50fcc0817505
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-07-11 10:39:22 +01:00
Matthew Poremba
134824e847 ruby: Fix double statistic registration in garnet
Currently garnet will not run due to double statistic registration of new
stats in ClockedObject. This occurs because a temporary array named 'cls'
is being added as a child to garnet internal and external link SimObjects.
This patch simply renames the temporary array which prevents it from
being added as a child object and avoids the assertion that a statistic
was already registered.

Committed by Jason Lowe-Power <jason@lowepower.com>
2016-07-01 10:31:37 -05:00
Matthias Jung
86e9a6ffec ext: Update DRAMPower
Sync DRAMPower to external tool

This patch syncs the DRAMPower library of gem5 to the external
one on github (https://github.com/ravenrd/DRAMPower) of which
I am a maintainer.

The version used is the commit:
902a00a1797c48a9df97ec88868f20e847680ae6
from 07.  May.  2016.

Committed by Jason Lowe-Power <jason@lowepower.com>
2016-07-01 10:31:36 -05:00
Abdul Mutaal Ahmad
7cb0c7bd65 mem: different HMC configuration
In this new hmc configuration we have used the existing components in gem5
mainly [SerialLink] [NoncoherentXbar]& [DRAMCtrl] to define 3 different
architecture for HMC.

Highlights

1- It explores 3 different HMC architectures

2- It creates 4-HMC crossbars and attaches 16 vault controllers with it.
This  will connect vaults to serial links

3- From the previous version, HMCController with round robin funtionality
is being removed and all the serial links are being accessible directly
from user ports

4- Latency incorporated by HMCController (in previous version) is being
added to SerialLink

Committed by Jason Lowe-Power <jason@lowepower.com>
2016-07-01 09:45:21 -05:00
Andreas Hansson
50e9d0df51 scons: Track swig packages when loading embedded swig code
This patch changes how the embedded swig code is loaded to ensure that
gem5 works with swig 3.0.9. For Python 2.7 and above, swig 3.0.9 now
relies on importlib, and actually looks in the appropriate packages,
even for the wrapped C code. However, the swig wrapper does not
explicitly place the module in the right package (it just calls
Py_InitModule), and we have to take explicit action to ensure that the
swig code can be loaded. This patch adds the information to the
generated wrappers and the appropriate calls to set the context as
part of the swig initialisation.

Previous versions of swig used to fall back on looking in the global
namespace for the wrappers (and still do for Python 2.6), but
technically things should not work without the functionality in this
patch.
2016-06-28 03:50:00 -04:00
Nikos Nikoleris
1fac3a292a arm: Mark uninitialized new TLB entries as not valid
Previously when we initialized the TLB we would allocate a number of
TLB entries which would be marked as valid. As a result the TLB
contained an entry which would be considered a valid entry for the 0
page.

Change-Id: I23ace86426a171a4f6200ebeb29ad57c21647036
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-06-20 15:51:31 +01:00
Reiley Jeapaul
0e80ee7778 sim: Added library include to fix build errors on clang-703.0.31
The use of array tuples, requires an explicit include of the array library

Change-Id: I06730051777a97edf80e41a5604184b387b12239
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-06-20 15:34:41 +01:00
Nikos Nikoleris
40e4453ddc mem: Fix the snoop filter when there is a downstream addr mapper
The snoop filter handles requests in two steps which preceed and
follow the call to send the packet downstream. An address mapper could
possibly change the address of the packet when it is sent downstream
breaking the snoop filter assumption that the address is unchanged

Change-Id: Ib2db755e9ebef4f2f7c0169a46b1b11185ffbe79
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-06-20 15:11:18 +01:00
Andreas Sandberg
efb7fb6f85 mem: Resolve TrafficGen trace relative to the config
The traffic generator currently resolves relative trace paths relative
to gem5's current working directory. This can lead to surprising
results for relative paths where the expectation would normally be
that they are resolved relative to the configuration file. This
changeset implements config-relative trace file lookups. The old
behavior is kept as a fallback for configs that expect that behavior.

Change-Id: I1bda4e16725842666ffc37dcb6838c23a6ff138c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2016-06-20 14:49:37 +01:00
Andreas Sandberg
37bb0d0fb3 kern, arm: Dump dmesg on kernel panic/oops
Add helper functions to dump the guest kernel's dmesg buffer to a text
file in m5out. This functionality is split into two parts. First, a
dmesg dump function that can be used in other places:

void Linux::dumpDmesg(ThreadContext *, std::ostream &)

This function is used to implement two PCEvents: DmesgDumpEvent and
KernelPanic event. The only difference between the two is that the
latter produces a gem5 panic instead of a warning in addition to
dumping the kernel log.

Change-Id: I6d2af1d666ace57124089648ea906f6c787ac63c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
2016-06-20 14:39:49 +01:00
Andreas Sandberg
60fb5e79f3 base: Fix multiple names to one address bug in SymbolTable
The SymbolTable class currently assumes that at most one symbol can
point to a given address. If multiple symbols point to the same
address, only the first one gets added to the internal symbol table
since there is already a match in the address table.

This changeset converts the address table from a map into a multimap
to be able to handle cases where an address maps to multiple
symbols. Additionally, the insert method is changed to not fail if
there is a match in the address table.

Change-Id: I6b4f1d5560c21e49a4af33220efb2a8302961768
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
2016-06-20 14:39:48 +01:00
Tuan Ta
bb9033c26b gpu-compute: Fixed a bug in decoding Atomic ST
There is a mismatch between DataType and SrcDataType in constructing
Atomic ST instruction. The mismatch causes atomic_store and
atomic_store_explicit function to store incorrect value in memory.
2016-06-18 13:02:13 -04:00
jkalamat
3724fb15fa gpu-compute: parametrize Wavefront size
Eliminate the VSZ constant that defined the Wavefront size (in numbers of work
items); replaced it with a parameter in the GPU.py configuration script.
Changed all data structures dependent on the Wavefront size to be dynamically
sized. Legal values of Wavefront size are 16, 32, 64 for now and checked at
initialization time.
2016-06-09 11:24:55 -04:00
Mohammad Alian
e5b7b6780f dist, dev: Fixed the packet ordering in etherswitch
This patch fixes the order that packets gets pushed into the output fifo
of etherswitch. If two packets arrive at the same tick to the etherswitch,
we sort and push them based on their source port id.
In dist-gem5 simulations, if there is no ordering inforced while two
packets arrive at the same tick, it can lead to non-deterministic simulations

Committed by Jason Lowe-Power <power.jg@gmail.com>
2016-06-08 09:12:41 -05:00
Andreas Hansson
8d177d128f sim: Make clang happy
Once again appeasing clang.
2016-06-07 14:27:49 +01:00
Sergei Trofimov
0257fdee91 sim: added missing include to mathexpr.hh
mathexpr.hh uses std::function<> but was not including the appropriate
header, which resulted in an error

build/ARM/sim/mathexpr.hh:51:18: error: 'function' in namespace 'std'
does not name a template type
     typedef std::function<double(std::string)> EvalCallback;

This commit adds the missing include.

Change-Id: I6c01d77d4354c6de838538f137a38f75f9866166
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2016-06-07 14:27:35 +01:00
Andreas Sandberg
21b66f4542 sim: Only print the power state transition warning once
A lot of objects seem to request no-op power transitions which
currently results in large amounts of warnings. These warnings are
benign and risk hiding more serious warnings. Make the warning a
warn_once to prevent console flooding.

Change-Id: I86c74b4224b167f14469250ef86ab69fde7a227e
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-06-06 17:16:44 +01:00
David Guillen Fandos
12714040a2 pwr: Closing power and thermal feedback loop
This patch makes thermal models use the power figures
calculated by power models. Since there is a circular
dependency between power and thermal (and thermal was
pushed before) this patch closes that loop.

Change-Id: I8bd5acf6a5026fdbbcfac47e33d27397f24a6f7d
Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com>
2016-06-06 17:16:44 +01:00
David Guillen Fandos
7cfb59d6e5 sim: Adding support for power models
This patch adds some basic support for power models in gem5.

The power interface is defined so it can interact with thermal
models as well. It implements a simple power evaluator that
can be used for simple power models that express power in the
form of a math expression. These expressions can use stats
within the same SimObject (or down its hierarchy) and some
magic variables such as "temp" for temperature.
In future patches we will extend this functionality to allow
slightly more complex expressions.

The model allows it to be extended to use other kinds of models.

Change-Id: I76752f9638b6815e229fd74cdcb7721a305cbc4b
2016-06-06 17:16:44 +01:00
David Guillen Fandos
fb5fc11da4 pwr: Low-power idle power state for idle CPUs
Add functionality to the BaseCPU that will put the entire CPU
into a low-power idle state whenever all threads in it are idle.

Change-Id: I984d1656eb0a4863c87ceacd773d2d10de5cfd2b
2016-06-06 17:16:43 +01:00
Andreas Sandberg
d4342aff4c stats: Silence unused power stats
The power stats are currently very noisy even if no power model has
been loaded. Silence stats that are either zero or nan.

Change-Id: I7d0220c2fcf01131084a219228f140cfaddaf95b
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-06-06 17:16:43 +01:00
David Guillen Fandos
5350879f49 pwr: Add power states to ClockedObject
Add 4 power states to the ClockedObject, provides necessary access
functions to check and update the power state. Default power state
is UNDEFINED, it is responsibility of the respective simulation
model to provide the startup state and any other logic for state
change. Add number of transition stat. Add distribution of time
spent in clock gated state. Add power state residency stat. Add
dump call back function to allow stats update of distribution
and residency stats.

Change-Id: Id086090a2ed720c9fcb37812a3c98f0f724907c6
2016-06-06 17:16:43 +01:00
David Guillen Fandos
70798b1ba0 stats: Fixing regStats function for some SimObjects
Fixing an issue with regStats not calling the parent class method
for most SimObjects in Gem5. This causes issues if one adds new
stats in the base class (since they are never initialized properly!).

Change-Id: Iebc5aa66f58816ef4295dc8e48a357558d76a77c
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-06-06 17:16:43 +01:00
Stephan Diestelhorst
589033c94c sim: Call regStats of base-class as well
We want to extend the stats of objects hierarchically and thus it is necessary
to register the statistics of the base-class(es), as well.  For now, these are
empty, but generic stats will be added there.

Patch originally provided by Akash Bagdia at ARM Ltd.
2016-06-06 17:16:43 +01:00
Tuan Ta
b6d20c25c3 gpu-compute: Fixed a bug in global memory pipeline
Added a condition when inflightStores is incremented to prevent a deadlock
caused by many memory fence requests generated by a CU
2016-06-03 16:20:08 -04:00
Marco Elver
289a8ebdb1 ruby: Implement SwapReq support
This implements SwapReq for Ruby memory.

A SwapReq should be treated like a write, except that the response
packet contains the overwritten data.

Note that, in particular, the conditional checking for isStore/isLoad
needs to be reversed, as a SwapReq is both.
2016-06-03 16:20:08 -04:00
Curtis Dunham
d31c0f165d arm: refactor page table format determination
In particular, when EL0 is in AArch32 but EL1 is AArch64, AArch64
memory translation must be used.  This is essential for typical
AArch64/32 interworking use cases.
2016-06-02 16:44:57 +01:00
Andreas Sandberg
660fbd543f arm: Rewrite ERET to behave according to the ARMv8 ARM
The ERET instruction doesn't set PSTATE correctly in some cases
(particularly when returning to aarch32 code). Among other things,
this breaks EL0 thumb code when using a 64-bit kernel. This changeset
updates the ERET implementation to match the ARM ARM.

Change-Id: I408e7c69a23cce437859313dfe84e68744b07c98
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nathanael Premillieu <nathanael.premillieu@arm.com>
2016-06-02 13:41:26 +01:00
Andreas Sandberg
f48ad5b29d arm: Correctly check FP/SIMD access permission in aarch32
The current implementation of aarch32 FP/SIMD in gem5 assumes that EL1
and higher are all 32-bit. This breaks interprocessing since an
aarch64 EL1 uses different enable/disable bits. This change updates
the permission checks to according to what is prescribed by the ARM
ARM.

Change-Id: Icdcef31b00644cfeebec00216b3993aa1de12b88
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Mitch Hayenga <mitch.hayenga@arm.com>
Reviewed-by: Nathanael Premillieu <nathanael.premillieu@arm.com>
2016-06-02 13:38:30 +01:00
Andreas Sandberg
c661cc75ec arm: Enable LPAE support by default
LPAE has been tested with Linux 4.4 and seems to work just fine. Let's
enable it by default.

Change-Id: Id88c6e3c91ae9c353279d42f2aa1f8a78485bd32
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
2016-05-31 12:14:40 +01:00
Andreas Sandberg
9d4a42e8c5 arm: Correctly check translation mode (aarch64/aarch32)
According to the ARM ARM (see AArch32.TranslateAddress in the
pseudocode library), the TLB should be operating in aarch64 mode if
the EL0 is aarch32 and EL1 is aarch64. This is currently not the case
in gem5, which breaks 64/32 interprocessing. Update the check to match
the reference manual.

Change-Id: I6f1444d57c0e2eb5f8880f513f33a9197b7cb2ce
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Mitch Hayenga <mitch.hayenga@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2016-05-31 12:14:37 +01:00
Andreas Hansson
be014d4338 scons: Bump minimum gcc version to 4.8
After reaching consensus on the mailing list, this patch officially
makes gcc 4.8 the minimum.

A few checks in the SConstruct are cleaned up as a result. This patch
also adds "-fno-omit-frame-pointer" when using ASAN (which is part of
the gcc/clang  recommended flags).
2016-05-30 02:10:48 -04:00
Ilias Vougioukas
7c8d6e3660 cpu: fix lastStopped unserialisation
MinorCPU fix for corrupt numCycles when resuming from a previous simulation.
---
 src/cpu/minor/cpu.cc | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)
2016-05-27 16:55:01 +01:00
Akash Bagdia
07452aebf5 power: Allow voltage to be configured via cmd line
---
 src/python/m5/params.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
2016-05-27 16:54:59 +01:00
Andreas Sandberg
4a6bb82123 arm: Use the target EL state when determining fault format
We currently check the current state instead of the state of the
target EL when determining how we report a fault. This breaks
interprocessing since EL0 in aarch32 would report its fault status
using the aarch32 registers even if EL1 is in aarch64. Fix this to
report the fault using the format of the target EL.

Change-Id: Ic080267ac210783d1e01c722a4ddaa687dce280e
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Mitch Hayenga <mitch.hayenga@arm.com>
2016-05-27 15:02:01 +01:00
Andreas Sandberg
2ace05044c arm: Fix incorrect TLB permission check in aarch32
The TLB currently assumes that the pxn bit in an LPAE page descriptor
disables execution from unprivileged mode. However, according to the
architecture manual, this bit should disable execution from privileged
modes. Update the TLB implementation to reflect this behavior.

Change-Id: I7f1bb232d7a94a93fd601a9230223195ac952947
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2016-05-26 17:38:15 +01:00
Andreas Sandberg
e360f4db07 arm: Make EL checks available in SE mode
A lot of code assumes that it is possible to test what the highest EL
is and if it is 64 bit. These calls currently don't work in SE mode
since they rely on an instance of an ArmSystem.

Change-Id: I0d1f261926a66ce3dc4fa116845ffb2a081446f2
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Nathanael Premillieu <nathanael.premillieu@arm.com>
2016-05-26 17:33:38 +01:00
Andreas Hansson
e3e808416f mem: Fix memory leak in handling of deferred snoops
This patch fixes a memory leak where deferred snoop packets never got
deallocated. On the call to MSHR::handleSnoop these snoops were
treated as if a response will be sent, as the MSHR was
pendingModified. Consequently, a copy of the packet was created and
added to the MSHR targets. However, an preceeding target to the same
MSHR, originally from a CPU, was serviced before the snoop, and caused
the block to be invalidated. This happens for ReadExReq and
UpgradeReq.

Note that the original snoop will receive a response, just not from
the cache in question, but instead from the cache upstream that issued
the ReadExReq or UpgradeReq.

Change-Id: I4ac012fbc8a46cf693ca390fe9476105d444e6f4
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2016-05-26 11:56:24 +01:00
Andreas Sandberg
4d577ac8f1 dev, arm: Add a flag to enable/disable gem5 GIC extensions
Make it possible to disable gem5 gic extensions by setting the
gem5_extensions param to False from Python.

Change-Id: Icb255105925ef49891d69cc9fe5cc55578ca066d
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Geoffrey Blake <geoffrey.blake@arm.com>
2016-05-26 11:56:24 +01:00
Andreas Hansson
d023b7e8db cpu: Add a basic progress check to the TrafficGen
This patch adds a progress check to the TrafficGen so that it is
easier to detect deadlock scenarios where the generator gets stuck
waiting for a retry, and makes no further progress.

Change-Id: Ifb8779ad0939f52c0518d0e867bac73f99b82e2b
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>
2016-05-26 11:56:24 +01:00
Andreas Hansson
4ff4f9c531 mem: Do not set cacheResponding on MSHR snoop if not responding
This patch changes the flow control for HSHR::handleSnoop to ensure
that we only set cacheResponding on the snoop packet if we are
actually responding. This avoids situations where a responder is
stalling indefinitely on a response that never arrives.

Change-Id: I691dd01755b614b30203581aa74fc743b350eacc
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2016-05-26 11:56:24 +01:00
Andreas Hansson
90de9be2ef mem: Fix MemChecker unique_ptr type mismatch
This patch fixes the type of the unique_ptr instances, to ensure that
the data that is allocated with new[] is also deleted with
delete[]. The issue was highlighted by ASAN.

Change-Id: I2c5510424959d862a9954d83e728d901bb18d309
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com>
2016-05-26 11:56:24 +01:00
Andreas Hansson
7dc5034ff2 arm: Fix heap overflow issue in Neon64Load operation
This patch fixes an issue identified by ASAN where the Neon64Load
operation assumes the packet always contains 16 bytes.

Change-Id: If24a7e461d60cb80970dfbe61d923d7d56926698
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2016-05-26 11:56:24 +01:00
Andreas Hansson
4a3e2156ac arm, dev: Remove superfluous loop increment in flash device
As identified by clang-3.8, there was a superfluous loop increment in
the flash device which is now removed.

Change-Id: If46a1c4f72d3d4c9f219124030894ca433c790af
Reviewed-by: Rene De Jong <rene.dejong@arm.com>
2016-05-26 11:56:24 +01:00
Nikos Nikoleris
a69a0f33cb mem: fix headers include order in the cache related classes
Change-Id: Ia57cc104978861ab342720654e408dbbfcbe4b69
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-05-26 11:56:24 +01:00
Nikos Nikoleris
f9d62b63e1 mem: remove redudant check whether the cache forwards snoops
Change-Id: I57b56771086e1e2f512977fb7248d93c171ab925
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-05-26 11:56:24 +01:00
Nikos Nikoleris
d68f3577d6 mem: change NULL to nullptr in the cache related classes
Change-Id: I5042410be54935650b7d05c84d8d9efbfcc06e70
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-05-26 11:56:24 +01:00
Nikos Nikoleris
90bf50b4c7 mem: fix the line length in the cache related classes
Change-Id: I6d1feb164a958dde0da87a1cd2698096112c4a82
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-05-26 11:56:24 +01:00
Bjoern A. Zeeb
7fc668fae9 config, x86: Properly space pad the X86IntelMPBus Entry descriptions
According to the Intel Multi Processor Specification rev 1.4 (-006) (*),
section 4.3.2 Bus Entries, Bus type strings are >>6-character ASCII
(blank-filled) strings<<.
This patch properly pads the entries with the missing spaces at the end.

(*) http://www.intel.com/design/pentium/datashts/24201606.pdf

Committed by Jason Lowe-Power <power.jg@gmail.com>
2016-05-19 15:19:35 -05:00
Bjoern A. Zeeb
a6b00c07f6 arm,dev: PL011 UART_FR read status enhancement
Given we do not simulate a FIFO currently there are only two states
we can be in upon read: empty or full.  Properly signal the latter.

Add and sort constants for states in the header file.

Committed by Jason Lowe-Power <power.jg@gmail.com>
2016-05-19 15:19:35 -05:00
Bjoern A. Zeeb
5fa6b68981 x86, dev: properly space the APIC registers
Registers are 0x10 and not 0x8 apart.  The latter leads to invalid
calculations of index in array which in turn means that we will not
find the interrupt we were looking (been notified) for in the OS.

Committed by Jason Lowe-Power <power.jg@gmail.com>
2016-05-19 15:19:35 -05:00
Bjoern A. Zeeb
ce610dcab1 dev, virtio: properly set PCI address space to use IOREG
VirtIO spec < 1.0 demands IOREG to be used on PCI and not memory mapped.
Set the correct bit on the PCI address accordingly.

Committed by Jason Lowe-Power <power.jg@gmail.com>
2016-05-19 15:19:34 -05:00
Tony Gutierrez
7dad4377ec gpu-compute: fix bug in GPUDynInst::isScalarRegister() 2016-05-16 15:36:24 -04:00
Tony Gutierrez
bb83fa2051 gpu-compute: fix spacing in GPUDynInst ctor 2016-05-06 17:00:54 -04:00
Tony Gutierrez
4f3139e696 gpu-compute: fix uninitialized member bug in GPUDynInst
the n_reg field in the GPUDynInst is not currently set in the constructor.
if it is not set externally, there are assertion failures that may occur
if the random value it gets is just right. here we set it to 0 by default.
2016-05-06 16:44:38 -04:00
Andreas Sandberg
84cfa10b15 dev, arm: Update GIC to use GICv2 register naming
The GICv2 has a new and slightly more consistent register
naming. Update gem5's GIC register names to match the new
documentation.

Change-Id: I8ef114eee8a95bf0b88b37c18a18e137be78675a
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2016-05-06 15:52:34 +01:00
Andreas Sandberg
53f58b5fc1 arm: Remove BreakPCEvent on guest kernel panic
The LinuxArmSystem class normally provides support for panicing gem5
if the simulated kernel panics. When this is turned off (default),
gem5 uses a BreakPCEvent to provide a debugger hook into the simulator
when the kernel crashes. This hook unconditionally kills gem5 with a
SIGTRAP unless gem5 is compiled in fast mode. This is undesirable
since the panic_on_panic param already provides similar functionality.

Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2016-04-27 15:34:58 +01:00
Andreas Sandberg
f1575fdc4a kvm, arm: Make GIC interrupt lines configurable
Add support for overriding the number of interrupt lines in the ARM
KvmGic.

Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2016-04-27 15:34:48 +01:00
Andreas Sandberg
d5e7892350 kvm, arm: Refactor KVM GIC device
Factor out the kernel device wrapper from the KvmGIC and put it in a
separate class. This will simplify a future kernel/gem5 hybrid GIC.

Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2016-04-27 15:34:31 +01:00
Andreas Sandberg
6d74892b38 dev: Fix incorrect terminal backlog handling
The Terminal device currently uses the peek functionality in gem5's
circular buffer implementation to send existing buffered content on
the terminal when a new client attaches. This functionallity is
however not implemented correctly and re-sends the same block multiple
time.

Add the required functionality to peek with an offset into the
circular buffer and change the Terminal::accept() implementation to
send the buffered contents.

Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2016-04-27 15:33:58 +01:00
Matthew Poremba
67e93a5846 ruby: Rename pkt to m_pkt so it may be accessed via SLICC
Allow usage of packet class in ruby for convenience purposes. This may be
used to access members of the packet/request class (e.g., via helper
functions) and/or push protocol specific information to the packets
SenderState without needing to modify SLICC types and protocols in multiple
locations.
2016-04-26 12:07:51 -04:00
Andreas Hansson
5a1dea51d2 mem: Include WriteLineReq in cache demand stats
Somehow the WriteLineReq were never added to the list of commands
considered demand.
2016-04-21 04:48:20 -04:00
Andreas Hansson
a7c94f6e69 mem: Remove unused cache stats
Prune cache stats that are never actually used.
2016-04-21 04:48:19 -04:00
Andreas Hansson
13b9d4215d mem: Deallocate all write-queue entries when sent
This patch removes the write-queue entry tracking previously used for
uncacheable writes. The write-queue entry is now deallocated as soon
as the packet is sent. As a result we also forego the stats for
uncacheable writes. Additionally, there is no longer a need to attach
the write-queue entry to the packet.
2016-04-21 04:48:07 -04:00
Andreas Hansson
6c92ee49f1 mem: Align downstream cache packet creation in atomic and timing
This patch makes the control flow more uniform in atomic and timing,
ultimately making the code easier to understand.
2016-04-21 04:48:06 -04:00
Joel Hestness
39e10ced03 ruby: Fix block_on behavior
Ruby's controller block_on behavior aimed to block MessageBuffer requests into
SLICC controllers when a Locked_RMW was in flight. Unfortunately, this
functionality only partially works: When non-Locked_RMW memory accesses are
issued to the sequencer to an address with an in-flight Locked_RMW, the
sequencer may pass those accesses through to the controller. At the controller,
a number of incorrect activities can occur depending on the protocol. In
MOESI_hammer, for example, an intermediate IFETCH will cause an L1D to L2
transfer, which cannot be serviced, because the block_on functionality blocks
the trigger queue, resulting in a deadlock. Further, if an intermediate store
arrives (e.g. from a separate SMT thread), the sequencer allows the request
through to the controller, and the atomicity of the Locked_RMW may be broken.

To avoid these problems, disallow the Sequencer from passing any memory
accesses to the controller besides Locked_RMW_Write when a Locked_RMW is in-
flight.
2016-04-15 12:34:02 -05:00
Bjoern A. Zeeb
edbf748181 arm,dev: remove PMU assertion hit on reset
Remve the assertion that we always need to add a delta larger than
zero as that does not seem to be true when we hit it in the
'PMU reset cycle counter to zero' case.

Committed by Jason Lowe-Power <power.jg@gmail.com>
2016-04-15 10:03:03 -05:00
Bjoern A. Zeeb
bc45e930e4 mem: FreeBSD does not provide MAP_NORESERVE either
Like OS X, FreeBSD does not support MAP_NORESERVE.
Handle accordingly and update comment.

Committed by Jason Lowe-Power <power.jg@gmail.com>
2016-04-15 10:02:58 -05:00
Andreas Hansson
8127c4e7bf misc: Fix issues flagged by gcc 6
A few warnings (and thus errors) pop up after being added to -Wall:

1. -Wmisleading-indentation

In the auto-generated code there were instances of if/else blocks that
were not indented to gcc's liking. This is addressed by adding braces.

2. -Wshift-negative-value

gcc is clever enougn to consider ~0 a negative constant, and
rightfully complains. This is addressed by using mask() which
explicitly casts to unsigned before shifting.

That is all. Porting done.
2016-04-13 12:13:44 -04:00
Andreas Hansson
4b802a09c5 misc: Appease clang...again
Once again, clang is having issues with recently committed code.

Unfortunately HSAIL_X86 is still broken.
2016-04-12 05:28:39 -04:00
Rekai Gonzalez Alberquilla
af27586fbc mem: Add priority to QueuedPrefetcher
Queued prefetcher entries now count with a priority field. The idea is to
add packets ordered by priority and then by age.

For the existing algorithms in which priority doesn't make sense, it is set
to 0 for all deferred packets in the queue.
2016-04-07 11:32:38 -05:00
Rekai Gonzalez Alberquilla
dad7d9277b mem: Handful extra features for BasePrefetcher
Some common functionality added to the base prefetcher, mainly dealing with
extracting the block address, page address, block index inside the page and
some other information that can be inferred from the block address. This is
used for some prefetching algorithms, and having the methods in the base,
as well as the block size and other information is the sensible way.
2016-04-07 11:32:38 -05:00
Victor Garcia
df5a811833 mem: Add Program Counter to MemTraceProbe 2016-04-07 11:32:38 -05:00
Rekai Gonzalez Alberquilla
a3bf4aa6ec mem: Add unused prefetch counter in caches
Added stat to the cache to account for HardPF'ed blocks that are evicted
before being referenced (over-prefetching).
2015-05-27 13:50:01 +01:00
Mitch Hayenga
c75ff71139 mem: Remove threadId from memory request class
In general, the ThreadID parameter is unnecessary in the memory system
as the ContextID is what is used for the purposes of locks/wakeups.
Since we allocate sequential ContextIDs for each thread on MT-enabled
CPUs, ThreadID is unnecessary as the CPUs can identify the requesting
thread through sideband info (SenderState / LSQ entries) or ContextID
offset from the base ContextID for a cpu.

This is a re-spin of 20264eb after the revert (bd1c6789) and includes
some fixes of that commit.
2016-04-07 09:30:20 -05:00
Mitch Hayenga
d99deff8ea cpu: Implement per-thread GHRs
Branch predictors that use GHRs should index them on a
per-thread basis.  This makes that so.

This is a re-spin of fb51231 after the revert (bd1c6789).
2016-04-05 12:20:19 -05:00
Mitch Hayenga
0fd4bb7f12 cpu: Add an indirect branch target predictor
This patch adds a configurable indirect branch predictor that can be indexed
by a combination of GHR and path history hashes. Implements the functionality
described in:

"Target prediction for indirect jumps" by Chang, Hao, and Patt
http://dl.acm.org/citation.cfm?id=264209

This is a re-spin of fb9d142 after the revert (bd1c6789).
2016-04-05 11:48:37 -05:00
Mitch Hayenga
3f6874cb29 cpu: Fix BTB threading oversight
The extant BTB code doesn't hash on the thread id but does check the
thread id for 'btb hits'.  This results in 1-thread of a multi-threaded
workload taking a BTB entry, and all other threads missing for the same branch
missing.
2016-04-05 11:44:27 -05:00
Sascha Bischoff
1097aa1638 misc: Bail out of DVFS dot if we cannot resolve the domains
This changeset updates the dot output to bail out if it is unable to
resolve the voltage or clock domains (which will cause it to raise an
AttributeError). Additionally, the DVFS dot output is disabled by
default for speed purposes.

Minor fixup for 0aeca8f.
2016-04-06 17:55:17 +01:00
Andreas Sandberg
fd52a63e24 Revert to 74c1e6513bd0 (sim: Thermal support for Linux) 2016-04-07 10:42:07 +01:00
Andreas Sandberg
be28d96510 Revert power patch sets with unexpected interactions
The following patches had unexpected interactions with the current
upstream code and have been reverted for now:

e07fd01651f3: power: Add support for power models
831c7f2f9e39: power: Low-power idle power state for idle CPUs
4f749e00b667: power: Add power states to ClockedObject

Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>

--HG--
extra : amend_source : 0b6fb073c6bbc24be533ec431eb51fbf1b269508
2016-04-06 19:43:31 +01:00
Mitch Hayenga
8615b27174 mem: Remove threadId from memory request class
In general, the ThreadID parameter is unnecessary in the memory system
as the ContextID is what is used for the purposes of locks/wakeups.
Since we allocate sequential ContextIDs for each thread on MT-enabled
CPUs, ThreadID is unnecessary as the CPUs can identify the requesting
thread through sideband info (SenderState / LSQ entries) or ContextID
offset from the base ContextID for a cpu.
2016-04-05 12:39:21 -05:00
Curtis Dunham
76ee011a12 cpu: Implement per-thread GHRs
Branch predictors that use GHRs should index them on a
per-thread basis.  This makes that so.
2016-04-05 12:20:19 -05:00
Mitch Hayenga
1578d2d0b6 cpu: Add an indirect branch target predictor
This patch adds a configurable indirect branch predictor that can be indexed
by a combination of GHR and path history hashes. Implements the functionality
described in:

"Target prediction for indirect jumps" by Chang, Hao, and Patt
http://dl.acm.org/citation.cfm?id=264209
2016-04-05 11:48:37 -05:00
Mitch Hayenga
7bc52af771 cpu: Fix BTB threading oversight
The extant BTB code doesn't hash on the thread id but does check the
thread id for 'btb hits'.  This results in 1-thread of a multi-threaded
workload taking a BTB entry, and all other threads missing for the same branch
missing.
2016-04-05 11:44:27 -05:00
David Guillen Fandos
f902c0218a power: Add support for power models
This patch adds some basic support for power models in gem5.

The power interface is defined so it can interact with thermal
models as well. It implements a simple power evaluator that
can be used for simple power models that express power in the
form of a math expression. These expressions can use stats
within the same SimObject (or down its hierarchy) and some
magic variables such as "temp" for temperature.
In future patches we will extend this functionality to allow
slightly more complex expressions.

The model allows it to be extended to use other kinds of models.

Finally, the thermal model is updated to use the power usage as input.
2016-04-05 10:52:28 -05:00
Akash Bagdia
1c34ee20df power: Low-power idle power state for idle CPUs
Add functionality to the BaseCPU that will put the entire CPU into a low-power
idle state whenever all threads in it are idle.
2014-12-09 10:42:08 +00:00
Akash Bagdia
3ee4957b49 power: Add power states to ClockedObject
Add 4 power states to the ClockedObject, provides necessary access functions
to check and update the power state. Default power state is UNDEFINED, it is
responsibility of the respective simulation model to provide the startup state
and any other logic for state change.

Add number of transition stat.
Add distribution of time spent in clock gated state.
Add power state residency stat.

Add dump call back function to allow stats update of distribution and residency
stats.
2014-11-18 14:00:48 +00:00
David Guillen Fandos
65ecd95486 sim: Thermal support for Linux
This patch enables Linux to read the temperature using hwmon infrastructure.
In order to use this in your gem5 you need to compile the kernel using the
following configs:

CONFIG_HWMON=y
CONFIG_SENSORS_VEXPRESS=y

And a proper dts file (containing an entry such as):

dcc {
 compatible = "arm,vexpress,config-bus";
 arm,vexpress,config-bridge = <&v2m_sysreg>;

  temp@0 {
   compatible = "arm,vexpress-temp";
   arm,vexpress-sysreg,func = <4 0>;
   label = "DCC";
  };
};
2015-05-13 15:02:25 +01:00
David Guillen Fandos
75c82f1fe3 sim: Adding thermal model support
This patch adds basic thermal support to gem5. It models energy dissipation
through a circuital equivalent, which allows us to use RC networks.
This lays down the basic infrastructure to do so, but it does not "work" due
to the lack of power models. For now some hardcoded number is used as a PoC.
The solver is embedded in the patch.
2015-05-12 10:26:47 +01:00
Mitch Hayenga
85dadcd381 cpu: Add instruction opclass histogram to minor 2016-04-05 08:08:12 -05:00
Sascha Bischoff
774350b750 misc: Add secondary dot output for DVFS domains
This patch adds a secondary dot output file which shows the DVFS domains. This
has been done separately for now to avoid cluttering the already existing
diagram. Due to the way that the clock domains are assigned to components in
gem5, this output must be generated after the C++ objects have been
instantiated. This further motivates the need to generate this file separately
to the current dot output, and not to replace it entirely.
2015-12-15 09:40:56 +00:00
Sascha Bischoff
38a369c473 sim: Add additional debug information when draining
This patch adds some additional information when draining the system which
allows the user to debug which SimObject(s) in the system is failing to drain.
Only enabled for the builds with tracing enabled and is subject to the Drain
debug flag being set at runtime.
2015-12-11 17:29:53 +00:00
Sascha Bischoff
ebc9e1d426 sim: Fix clock_domain unserialization
This patch addresses an issue with the unserialization of clock
domains. Previously, the previous performance level was not restored
due to a bug in the code, which detected the post-unserialize update
as superfluous. This patch splits the setting of the clock domain into
two parts. The original interface of perfLevel is retained, but the
actual update takes place in signalPerfLevelUpdate, which is private
to the class. The perfLevel method checks that if the new performance
level is different to the previous performance level, and will only
call signalPerfLevelUpdate if there is a change. Therefore, the
performance level is only updated, and voltage domains notified, if
there is an actual change. The split functionality allows
signalPerfLevelUpdate to be called by startup() to explicitly force an
update post unserialization.
2016-04-01 16:22:44 +01:00
Geoffrey Blake
f948f9fca9 cpu: Query CPU for inst executed from Python
This patch adds the ability for the simulator to query the number of
instructions a CPU has executed so far per hw-thread. This can be used
to enable more flexible periodic events such as taking checkpoints
starting 1s into simulation and X instructions thereafter.
2016-04-05 05:29:02 -05:00
Steve Reinhardt
df36764e91 syscall_emul: remove mmapFlagTable
After all this it turns out we don't even use it.
2016-04-01 16:38:16 -07:00
Steve Reinhardt
0e214bdfd1 syscall_emul: factor out flag tables into common file
The openFlagTable and mmapFlagTables for emulated Linux
platforms are basically identical, but are specified
repetitively for every platform.  Use a common file
that gets included for each platform so that we only
have one copy, making them more consistent and simplifying
changes (like adding #ifdefs).

In the process, made some minor fixes that slipped through
due to previous inconsistencies, and added more #ifdefs
to try to fix building on alternative hosts.
2016-04-01 16:38:15 -07:00