arm: Check TLB stage 2 permissions in AArch64
This fixes a bug where stage 2 lookups used the AArch32 permissions rules even if we were executing in AArch64 mode. Change-Id: Ia40758f0599667ca7ca15268bd3bf051342c24c1
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bce923c189
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1 changed files with 12 additions and 9 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2010-2013 ARM Limited
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* Copyright (c) 2010-2013, 2016 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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@ -60,6 +60,17 @@ Stage2LookUp::getTe(ThreadContext *tc, TlbEntry *destTe)
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functional, false, tranType);
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// Call finish if we're done already
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if ((fault != NoFault) || (stage2Te != NULL)) {
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// Since we directly requested the table entry (which we need later on
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// to merge the attributes) then we've skipped some stage2 permissions
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// checking. So call translate on stage 2 to do the checking. As the
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// entry is now in the TLB this should always hit the cache.
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if (fault == NoFault) {
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if (inAArch64(tc))
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fault = stage2Tlb->checkPermissions64(stage2Te, &req, mode, tc);
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else
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fault = stage2Tlb->checkPermissions(stage2Te, &req, mode);
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}
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mergeTe(&req, mode);
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*destTe = stage1Te;
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}
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@ -69,14 +80,6 @@ Stage2LookUp::getTe(ThreadContext *tc, TlbEntry *destTe)
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void
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Stage2LookUp::mergeTe(RequestPtr req, BaseTLB::Mode mode)
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{
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// Since we directly requested the table entry (which we need later on to
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// merge the attributes) then we've skipped some stage 2 permissinos
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// checking. So call translate on stage 2 to do the checking. As the entry
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// is now in the TLB this should always hit the cache.
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if (fault == NoFault) {
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fault = stage2Tlb->checkPermissions(stage2Te, req, mode);
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}
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// Check again that we haven't got a fault
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if (fault == NoFault) {
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assert(stage2Te != NULL);
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